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d="scan'208";a="272824849" Received: from ettammin-mobl3.ger.corp.intel.com (HELO [10.245.244.155]) ([10.245.244.155]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2026 06:57:56 -0700 Message-ID: <49da6f28a4ba582d32ac6cdccd6dea65d75eefbf.camel@linux.intel.com> Subject: Re: [PATCH v2] drm/xe: Limit sg segment size to PAGE_SIZE on Xen PV From: Thomas =?ISO-8859-1?Q?Hellstr=F6m?= To: Szymon =?UTF-8?Q?Aceda=C5=84ski?= , intel-xe@lists.freedesktop.org Cc: matthew.brost@intel.com, rodrigo.vivi@intel.com, maarten.lankhorst@linux.intel.com, hch@lst.de, bob.beckett@collabora.com, dri-devel@lists.freedesktop.org, marmarek@invisiblethingslab.com, xen-devel@lists.xenproject.org, stable@vger.kernel.org Date: Mon, 21 Sep 2026 15:57:49 +0200 In-Reply-To: <20260916173030.3223833-1-accek@invisiblethingslab.com> References: <20260916173030.3223833-1-accek@invisiblethingslab.com> Organization: Intel Sweden AB, Registration Number: 556189-6027 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 (3.58.3-1.fc43) MIME-Version: 1.0 X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 2026-09-16 at 19:30 +0200, Szymon Aceda=C5=84ski wrote: > Fix display corruption on Xen PV dom0, where DMA buffers are not > guaranteed machine-contiguous, in which case bounce buffering kicks > in, breaking xe's memory coherency assumptions. >=20 > Apply the same workaround i915 carries in i915_sg_segment_size() > since > commit 78a07fe777c4 ("drm/i915: stop abusing swiotlb_max_segment"). >=20 > Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel > GPUs") > Reported-by: Marek Marczykowski-G=C3=B3recki > > Closes: > https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8382 > Link: https://lore.kernel.org/xen-devel/aYtznP_tT6xNPwf-@mail-itl/ > Link: > https://lore.kernel.org/all/20221020110308.1582518-1-hch@lst.de/=C2=A0# > i915 counterpart > Cc: Christoph Hellwig > Cc: Robert Beckett > Cc: stable@vger.kernel.org=C2=A0# v6.8+ > Signed-off-by: Szymon Aceda=C5=84ski > --- > v2: > =C2=A0- Imperative language in the commit message (Thomas Hellstr=C3=B6m) > =C2=A0- CC the authors of the original i915 workaround (Thomas Hellstr=C3= =B6m) Reviewed-by: Thomas Hellstr=C3=B6m >=20 > =C2=A0drivers/gpu/drm/xe/xe_bo.h | 19 +++++++++++++++++++ > =C2=A01 file changed, 19 insertions(+) >=20 > diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h > index 290ca62..341fa93 100644 > --- a/drivers/gpu/drm/xe/xe_bo.h > +++ b/drivers/gpu/drm/xe/xe_bo.h > @@ -9,6 +9,8 @@ > =C2=A0#include > =C2=A0#include > =C2=A0 > +#include > + > =C2=A0#include "xe_bo_types.h" > =C2=A0#include "xe_ggtt.h" > =C2=A0#include "xe_macros.h" > @@ -574,6 +576,23 @@ static inline unsigned int > xe_sg_segment_size(struct device *dev) > =C2=A0 struct scatterlist __maybe_unused sg; > =C2=A0 size_t max =3D BIT_ULL(sizeof(sg.length) * 8) - 1; > =C2=A0 > + /* > + * For Xen PV guests pages aren't contiguous in DMA > (machine) address > + * space.=C2=A0 The DMA API takes care of that both in > dma_alloc_* (by > + * calling into the hypervisor to make the pages contiguous) > and in > + * dma_map_* (by bounce buffering).=C2=A0 But xe (like i915, see > commit > + * 78a07fe777c4) ignores the coherency aspects of the DMA > API and thus > + * can't cope with bounce buffering actually happening, so > add a hack > + * here to force small allocations and mappings when running > in PV > + * mode on Xen. > + * > + * Note this will still break if bounce buffering is > required for other > + * reasons, like confidential computing hypervisors or PCIe > root ports > + * with addressing limitations. > + */ > + if (xen_pv_domain()) > + return PAGE_SIZE; > + > =C2=A0 max =3D min_t(size_t, max, dma_max_mapping_size(dev)); > =C2=A0 > =C2=A0 /* >=20 > base-commit: baafc300cd079a5210c1e70e5ea3d93518e40b38