Re: [PATCH v5] drm/xe: Allow compressible surfaces to be 1-way coherent

[Matthew Auld <matthew.auld@intel.com>]

On 09/01/2026 09:30, Xin Wang wrote:
> Previously, compressible surfaces were required to be non-coherent (allocated
> as WC) because compression and coherency were mutually exclusive. Starting
> with Xe3, hardware supports combining compression with 1-way coherency,
> allowing compressible surfaces to be allocated as WB memory. This provides
> applications with more efficient memory allocation by avoiding WC allocation
> overhead that can cause system stuttering and memory management challenges.
> 
> The implementation adds support for compressed+coherent PAT entry for the
> xe3_lpg devices and updates the driver logic to handle the new compression
> capabilities.
> 
> v2: (Matthew Auld)
>   - Improved error handling with XE_IOCTL_DBG()
>   - Enhanced documentation and comments
>   - Fixed xe_bo_needs_ccs_pages() outdated compression assumptions
> 
> v3:
>   - Improve WB compression support detection by checking PAT table instead
> of version check
> 
> v4:
>   - Add XE_CACHE_WB_COMPRESSION, which simplifies the logic.
> 
> v5:
>   - Use U16_MAX for the invalid PAT index. (Matthew Auld)
> 
> Bspec: 71582, 59361, 59399
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Xin Wang <x.wang@intel.com>

Reviewed-by: Matthew Auld <matthew.auld@intel.com>