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From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
To: Badal Nilawar <badal.nilawar@intel.com>,
	<intel-xe@lists.freedesktop.org>
Cc: <anshuman.gupta@intel.com>, <rodrigo.vivi@intel.com>,
	<alexander.usyskin@intel.com>, <michael.j.ruhl@intel.com>
Subject: Re: [PATCH v3 2/3] drm/xe/xe_late_bind_fw: Enable late binding support for CRI
Date: Tue, 14 Jul 2026 16:35:22 -0700	[thread overview]
Message-ID: <4a889ab6-ddb9-4143-afba-2016590f121c@intel.com> (raw)
In-Reply-To: <20260709143926.3980581-7-badal.nilawar@intel.com>



On 7/9/2026 7:39 AM, Badal Nilawar wrote:
> Enable late binding support for CRI

Patch 1 turns ocode fetching on for BMG, while this patch turns it back 
off. Not a blocker since the binary doesn't exist, but it might be 
cleaner to do the following:

Patch 1 - turn flag into a mask in preparation (only fan control is set)
Patch 2 - add ocode support
Patch 3 - set the mask for CRI

Also, I don't think we can merge this patch to enable the feature while 
we don't have the compatibility fetching in place, because the feature 
doesn't work as-is (this is independent from the potential rework 
mentioned above)

> Assisted-by: GitHub-Copilot:GPT-5.3
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_device.c       | 2 +-
>   drivers/gpu/drm/xe/xe_device_types.h | 4 ++--
>   drivers/gpu/drm/xe/xe_late_bind_fw.c | 5 ++++-
>   drivers/gpu/drm/xe/xe_pci.c          | 9 +++++++--
>   drivers/gpu/drm/xe/xe_pci_types.h    | 3 ++-
>   5 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index ad7f3e61d457..d819315dff43 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -740,7 +740,7 @@ static void vf_update_device_info(struct xe_device *xe)
>   	xe->info.has_heci_cscfi = 0;
>   	xe->info.has_heci_gscfi = 0;
>   	xe->info.has_i2c = 0;
> -	xe->info.has_late_bind = 0;
> +	xe->info.late_bind_mask = 0;
>   	xe->info.skip_guc_pc = 1;
>   	xe->info.skip_pcode = 1;
>   	xe->info.has_drm_ras = false;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 022e08205897..b05abcb0c9d4 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -139,6 +139,8 @@ struct xe_device {
>   		u8 vm_max_level;
>   		/** @info.va_bits: Maximum bits of a virtual address */
>   		u8 va_bits;
> +		/** @info.late_bind_mask: Device has firmware late binding support */

The description now doesn't really match what the mask does. Maybe 
switch to something like "indicates which late binding firmwares are 
supported" ?

> +		u8 late_bind_mask;
>   
>   		/*
>   		 * Keep all flags below alphabetically sorted
> @@ -168,8 +170,6 @@ struct xe_device {
>   		u8 has_heci_gscfi:1;
>   		/** @info.has_i2c: Device has I2C controller */
>   		u8 has_i2c:1;
> -		/** @info.has_late_bind: Device has firmware late binding support */
> -		u8 has_late_bind:1;
>   		/** @info.has_llc: Device has a shared CPU+GPU last level cache */
>   		u8 has_llc:1;
>   		/** @info.has_mbx_power_limits: Device has support to manage power limits using
> diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_late_bind_fw.c
> index 1f627cdea24e..a7166f48bdb7 100644
> --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c
> +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c
> @@ -400,6 +400,7 @@ static int __xe_late_bind_fw_init(struct xe_late_bind *late_bind, u32 fw_id)
>   
>   static int xe_late_bind_fw_init(struct xe_late_bind *late_bind)
>   {
> +	struct xe_device *xe = late_bind_to_xe(late_bind);
>   	int ret;
>   	int fw_id;
>   
> @@ -408,6 +409,8 @@ static int xe_late_bind_fw_init(struct xe_late_bind *late_bind)
>   		return -ENOMEM;
>   
>   	for (fw_id = 0; fw_id < XE_LB_FW_MAX_ID; fw_id++) {
> +		if (!(xe->info.late_bind_mask & BIT(fw_id)))
> +			continue;
>   		ret = __xe_late_bind_fw_init(late_bind, fw_id);
>   		if (ret)
>   			return ret;
> @@ -471,7 +474,7 @@ int xe_late_bind_init(struct xe_late_bind *late_bind)
>   	struct xe_device *xe = late_bind_to_xe(late_bind);
>   	int err;
>   
> -	if (!xe->info.has_late_bind)
> +	if (!xe->info.late_bind_mask)
>   		return 0;
>   
>   	if (!IS_ENABLED(CONFIG_INTEL_MEI_LB) || !IS_ENABLED(CONFIG_INTEL_MEI_GSC)) {
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 08c14a0202d9..78e1a0c4b15e 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -395,6 +395,8 @@ static const struct xe_device_desc lnl_desc = {
>   	.vm_max_level = 4,
>   };
>   
> +#define LATE_BIND_MASK \
> +

This define is broken, but also unused. Leftover from an older rev?

>   static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 };
>   
>   static const struct xe_device_desc bmg_desc = {
> @@ -409,10 +411,10 @@ static const struct xe_device_desc bmg_desc = {
>   	.has_gsc_nvm = 1,
>   	.has_heci_cscfi = 1,
>   	.has_i2c = true,
> -	.has_late_bind = true,
>   	.has_pre_prod_wa = 1,
>   	.has_soc_remapper_telem = true,
>   	.has_sriov = true,
> +	.late_bind_mask = BIT(XE_LB_FW_FAN_CONTROL),
>   	.max_gt_per_tile = 2,
>   	MULTI_LRC_MASK,
>   	.needs_scratch = true,
> @@ -471,6 +473,8 @@ static const struct xe_device_desc cri_desc = {
>   	.has_soc_remapper_telem = true,
>   	.has_sriov = true,
>   	.has_sysctrl = true,
> +	.late_bind_mask = BIT(XE_LB_FW_FAN_CONTROL) |
> +			  BIT(XE_LB_FW_OCODE),
>   	.max_gt_per_tile = 2,
>   	MULTI_LRC_MASK,
>   	.require_force_probe = true,
> @@ -791,7 +795,6 @@ static int xe_info_init_early(struct xe_device *xe,
>   	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
>   	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
>   	xe->info.has_i2c = desc->has_i2c;
> -	xe->info.has_late_bind = desc->has_late_bind;
>   	xe->info.has_llc = desc->has_llc;
>   	xe->info.has_mert = desc->has_mert;
>   	xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
> @@ -808,6 +811,8 @@ static int xe_info_init_early(struct xe_device *xe,
>   	xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
>   	xe->info.multi_lrc_mask = desc->multi_lrc_mask;
>   
> +	xe->info.late_bind_mask = desc->late_bind_mask;

nit: I'd avoid leaving a blank line between multi_lrc_mask and 
late_bind_mask, since all the other 1-line assignments don't have spaces 
between them.

> +
>   	xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
>   				 xe_modparam.probe_display &&
>   				 desc->has_display;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index 24d4a3d00517..a368e0dfb486 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -34,6 +34,8 @@ struct xe_device_desc {
>   	u8 va_bits;
>   	u8 vm_max_level;
>   	u8 vram_flags;
> +	u8 late_bind_mask;

This should be ordered alphabetically

> +

unneeded newline.

Daniele

>   
>   	u8 require_force_probe:1;
>   	u8 is_dgfx:1;
> @@ -47,7 +49,6 @@ struct xe_device_desc {
>   	u8 has_heci_gscfi:1;
>   	u8 has_heci_cscfi:1;
>   	u8 has_i2c:1;
> -	u8 has_late_bind:1;
>   	u8 has_llc:1;
>   	u8 has_mbx_power_limits:1;
>   	u8 has_mbx_thermal_info:1;


  reply	other threads:[~2026-07-14 23:35 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-09 14:39 [PATCH v3 0/3] Add ocode late binding support for CRI Badal Nilawar
2026-07-09 14:35 ` ✓ CI.KUnit: success for Add ocode late binding support for CRI (rev3) Patchwork
2026-07-09 14:39 ` [PATCH v3 1/3] drm/xe/xe_late_bind_fw: Add support to load Ocode firmware Badal Nilawar
2026-07-14 23:23   ` Daniele Ceraolo Spurio
2026-07-14 23:24     ` Daniele Ceraolo Spurio
2026-07-09 14:39 ` [PATCH v3 2/3] drm/xe/xe_late_bind_fw: Enable late binding support for CRI Badal Nilawar
2026-07-14 23:35   ` Daniele Ceraolo Spurio [this message]
2026-07-09 14:39 ` [PATCH v3 3/3] drm/xe/xe_late_bind_fw: Refactor pm flow Badal Nilawar
2026-07-09 15:25 ` ✓ Xe.CI.BAT: success for Add ocode late binding support for CRI (rev3) Patchwork
2026-07-09 18:14 ` ✓ Xe.CI.FULL: " Patchwork

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