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From: "Mallesh, Koujalagi" <mallesh.koujalagi@intel.com>
To: Riana Tauro <riana.tauro@intel.com>
Cc: <anshuman.gupta@intel.com>, <rodrigo.vivi@intel.com>,
	<aravind.iddamsetty@linux.intel.com>, <badal.nilawar@intel.com>,
	<raag.jadav@intel.com>, <ravi.kishore.koppuravuri@intel.com>,
	<soham.purkait@intel.com>, <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v5 1/6] drm/xe/uapi: Add additional error components to xe drm_ras
Date: Fri, 8 May 2026 12:07:32 +0530	[thread overview]
Message-ID: <4ac5d412-de6f-4e04-9000-f9b61e1bc5d3@intel.com> (raw)
In-Reply-To: <20260504065614.3832331-9-riana.tauro@intel.com>


On 04-05-2026 12:26 pm, Riana Tauro wrote:
> Add additional Error components supported by XE drm_ras (Reliability,
> Availability and Serviceability).
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> ---
>   include/uapi/drm/xe_drm.h | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index 48e9f1fdb78d..50c80af4ad4e 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -2589,6 +2589,12 @@ enum drm_xe_ras_error_component {
>   	DRM_XE_RAS_ERR_COMP_CORE_COMPUTE = 1,
>   	/** @DRM_XE_RAS_ERR_COMP_SOC_INTERNAL: SoC Internal Error */
>   	DRM_XE_RAS_ERR_COMP_SOC_INTERNAL,
> +	/** @DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY: Device Memory Error */
> +	DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY,
> +	/** @DRM_XE_RAS_ERR_COMP_PCIE: PCIe Subsystem Error */
> +	DRM_XE_RAS_ERR_COMP_PCIE,
> +	/** @DRM_XE_RAS_ERR_COMP_FABRIC: Fabric Subsystem Error */
> +	DRM_XE_RAS_ERR_COMP_FABRIC,
>   	/** @DRM_XE_RAS_ERR_COMP_MAX: Max Error */
>   	DRM_XE_RAS_ERR_COMP_MAX	/* non-ABI */
>   };
> @@ -2606,7 +2612,10 @@ enum drm_xe_ras_error_component {
>    */
>   #define DRM_XE_RAS_ERROR_COMPONENT_NAMES {				\
>   	[DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = "core-compute",		\
> -	[DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal"		\
> +	[DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal",		\
> +	[DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY] = "device-memory",		\
> +	[DRM_XE_RAS_ERR_COMP_PCIE] = "pcie",				\
> +	[DRM_XE_RAS_ERR_COMP_FABRIC] = "fabric",			\
>   }

Please add static assert check to keep names in sync.

With that addressed:

Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>

Thanks,

-/Mallesh

>   
>   #if defined(__cplusplus)

  reply	other threads:[~2026-05-08  6:37 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-04  6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
2026-05-04  6:43 ` ✗ CI.checkpatch: warning for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork
2026-05-04  6:45 ` ✓ CI.KUnit: success " Patchwork
2026-05-04  6:56 ` [PATCH v5 1/6] drm/xe/uapi: Add additional error components to xe drm_ras Riana Tauro
2026-05-08  6:37   ` Mallesh, Koujalagi [this message]
2026-05-04  6:56 ` [PATCH v5 2/6] drm/xe/xe_ras: Add support to get error counter in CRI Riana Tauro
2026-05-06  8:03   ` Mallesh, Koujalagi
2026-05-06  8:59     ` Tauro, Riana
2026-05-04  6:56 ` [PATCH v5 3/6] drm/xe/xe_ras: Add helper to clear error counter Riana Tauro
2026-05-08  7:50   ` Mallesh, Koujalagi
2026-05-04  6:56 ` [PATCH v5 4/6] drm/xe/xe_drm_ras: Wire get-error-counter and clear-error-counter support for CRI Riana Tauro
2026-05-04  6:56 ` [PATCH v5 5/6] drm/xe/xe_ras: Move xe drm_ras registration Riana Tauro
2026-05-04 10:53   ` Tauro, Riana
2026-05-04 16:22     ` Raag Jadav
2026-05-04  6:56 ` [PATCH v5 6/6] drm/xe/xe_ras: Control xe drm_ras registration with a flag Riana Tauro
2026-05-04  8:00 ` ✓ Xe.CI.BAT: success for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork

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