Re: [PATCH] drm/xe/hwmon: Read accepted power limit for CRI

["Nilawar, Badal" <badal.nilawar@intel.com>]

On 18-02-2026 17:17, Karthik Poosa wrote:
> Update xe_hwmon_pcode_read_power_limit to read the accepted
accepted by pcode firmware?
> power limit using the new mailbox param introduced from CRI.
>
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_hwmon.c     | 5 +++--
>   drivers/gpu/drm/xe/xe_pcode_api.h | 3 ++-
>   2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index baf277955b33..8e1cbf7afed0 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -192,8 +192,9 @@ static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 att
>   						  READ_PSYSGPU_POWER_LIMIT :
>   						  READ_PACKAGE_POWER_LIMIT,
>   						  hwmon->boot_power_limit_read ?
> -						  READ_PL_FROM_PCODE : READ_PL_FROM_FW),
> -						  &val0, &val1);
> +						  (hwmon->xe->info.platform >= XE_CRESCENTISLAND ?
> +						   READ_PL_RESOLVED : READ_PL_FROM_PCODE) :

I think this handling is needed in xe_hwmon_pcode_rmw_power_limit() as 
well, especially when writing PWR_LIM_TIME.

Thanks,
Badal

> +						  READ_PL_FROM_FW), &val0, &val1);
>   
>   	if (ret) {
>   		drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
> diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
> index 85cc7478b787..636b9dfb11da 100644
> --- a/drivers/gpu/drm/xe/xe_pcode_api.h
> +++ b/drivers/gpu/drm/xe/xe_pcode_api.h
> @@ -47,8 +47,9 @@
>   #define	WRITE_PSYSGPU_POWER_LIMIT		0x7
>   #define	READ_PACKAGE_POWER_LIMIT		0x8
>   #define	WRITE_PACKAGE_POWER_LIMIT		0x9
> -#define	READ_PL_FROM_FW				0x1
>   #define	READ_PL_FROM_PCODE			0x0
> +#define	READ_PL_FROM_FW				0x1
> +#define	READ_PL_RESOLVED			0x2
>   
>   #define   PCODE_THERMAL_INFO			0x25
>   #define     READ_THERMAL_LIMITS			0x0