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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by SA2PR11MB5147.namprd11.prod.outlook.com (2603:10b6:806:118::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9275.15; Wed, 5 Nov 2025 06:18:25 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%7]) with mapi id 15.20.9253.013; Wed, 5 Nov 2025 06:18:25 +0000 Message-ID: <4d642610-e84e-4663-bceb-1e3fd64af600@intel.com> Date: Wed, 5 Nov 2025 11:48:19 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [RESEND, 19/22] drm/i915/display: Add function to configure event for dc balance To: Mitul Golani , CC: , , References: <20251103053002.3002695-1-mitulkumar.ajitkumar.golani@intel.com> <20251103053002.3002695-20-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20251103053002.3002695-20-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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(Ankit) > > --v3: > - Add function as per new enable/disable configuration framework. This is a new patch, the version history is no more applicable. Regards, Ankit > Signed-off-by: Mitul Golani > --- > drivers/gpu/drm/i915/display/intel_dmc.c | 15 +++++++++++++++ > drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++ > drivers/gpu/drm/i915/display/intel_vrr.c | 5 ++++- > 3 files changed, 21 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c > index 3e3f4438d739..1460f9674a35 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc.c > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c > @@ -852,6 +852,21 @@ static void dmc_configure_event(struct intel_display *display, > dmc_id, num_handlers, event_id); > } > > +/* > + * intel_dmc_configure_dc_balance_event() - Configure event > + * for dc balance enable/disable > + * @display: display instance > + * @pipe: pipe which register use to block > + * @enable: enable/disable > + */ > +void intel_dmc_configure_dc_balance_event(struct intel_display *display, > + enum pipe pipe, bool enable) > +{ > + enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); > + > + dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); > +} > + > /** > * intel_dmc_block_pkgc() - block PKG C-state > * @display: display instance > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h > index 132d6cfc8e8b..32a9abd53a8d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc.h > +++ b/drivers/gpu/drm/i915/display/intel_dmc.h > @@ -26,6 +26,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state); > void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state); > void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, > bool block); > +void intel_dmc_configure_dc_balance_event(struct intel_display *display, > + enum pipe pipe, bool enable); > void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, > enum pipe pipe, bool enable); > void intel_dmc_fini(struct intel_display *display); > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index eb6643ec5194..4d56a4e8c7ca 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -814,8 +814,10 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state, > if (cmrr_enable) > vrr_ctl |= VRR_CTL_CMRR_ENABLE; > > - if (crtc_state->vrr.dc_balance.enable) > + if (crtc_state->vrr.dc_balance.enable) { > + intel_dmc_configure_dc_balance_event(display, pipe, true); > intel_pipedmc_dcb_enable(NULL, crtc); > + } > > intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); > } > @@ -839,6 +841,7 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state) > > if (old_crtc_state->vrr.dc_balance.enable) { > intel_pipedmc_dcb_disable(NULL, crtc); > + intel_dmc_configure_dc_balance_event(display, pipe, false); > intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0); > intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0); > intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);