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d="scan'208";a="142393415" Received: from jkrzyszt-mobl2.ger.corp.intel.com (HELO [10.245.246.108]) ([10.245.246.108]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2025 05:02:50 -0800 Message-ID: <4fedc3b10e30134edbbf930e7cde18a29c97202e.camel@linux.intel.com> Subject: Re: [PATCH v4 18/33] drm/xe: Enable CPU address mirror uAPI From: Thomas =?ISO-8859-1?Q?Hellstr=F6m?= To: Matthew Brost , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: himal.prasad.ghimiray@intel.com, apopple@nvidia.com, airlied@gmail.com, simona.vetter@ffwll.ch, felix.kuehling@amd.com, dakr@kernel.org Date: Fri, 07 Feb 2025 14:02:47 +0100 In-Reply-To: <20250129195212.745731-19-matthew.brost@intel.com> References: <20250129195212.745731-1-matthew.brost@intel.com> <20250129195212.745731-19-matthew.brost@intel.com> Organization: Intel Sweden AB, Registration Number: 556189-6027 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.3 (3.54.3-1.fc41) MIME-Version: 1.0 X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 2025-01-29 at 11:51 -0800, Matthew Brost wrote: > Support for CPU address mirror bindings in SRAM fully in place, > enable the > implementation. >=20 > v3: > =C2=A0- s/system allocator/CPU address mirror (Thomas) >=20 > Signed-off-by: Matthew Brost > Reviewed-by: Thomas Hellstr=C3=B6m > --- > =C2=A0drivers/gpu/drm/xe/xe_svm.c | 10 ++++++++++ > =C2=A0drivers/gpu/drm/xe/xe_vm.c=C2=A0 |=C2=A0 6 ------ > =C2=A02 files changed, 10 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/gpu/drm/xe/xe_svm.c > b/drivers/gpu/drm/xe/xe_svm.c > index 56ece53b2069..ee150139470f 100644 > --- a/drivers/gpu/drm/xe/xe_svm.c > +++ b/drivers/gpu/drm/xe/xe_svm.c > @@ -429,6 +429,16 @@ int xe_svm_handle_pagefault(struct xe_vm *vm, > struct xe_vma *vma, > =C2=A0 return err; > =C2=A0} > =C2=A0 > +/** > + * xe_svm_has_mapping() - SVM has mappings > + * @vm: The VM. > + * @start: Start address. > + * @end: End address. > + * > + * Check if an address range has SVM mappings. > + * > + * Return: True is address range has a SVM mapping, False otherwise > + */ > =C2=A0bool xe_svm_has_mapping(struct xe_vm *vm, u64 start, u64 end) Ah, the kerneldoc here should probably go in the previous patch. /Thomas > =C2=A0{ > =C2=A0 return drm_gpusvm_has_mapping(&vm->svm.gpusvm, start, end); > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c > index d8c78ecd54ec..3ac03e0dc41b 100644 > --- a/drivers/gpu/drm/xe/xe_vm.c > +++ b/drivers/gpu/drm/xe/xe_vm.c > @@ -3020,12 +3020,6 @@ static int vm_bind_ioctl_check_args(struct > xe_device *xe, struct xe_vm *vm, > =C2=A0 u16 pat_index =3D (*bind_ops)[i].pat_index; > =C2=A0 u16 coh_mode; > =C2=A0 > - /* FIXME: Disabling CPU address mirror for now */ > - if (XE_IOCTL_DBG(xe, is_cpu_addr_mirror)) { > - err =3D -EOPNOTSUPP; > - goto free_bind_ops; > - } > - > =C2=A0 if (XE_IOCTL_DBG(xe, is_cpu_addr_mirror && > =C2=A0 !xe_vm_in_fault_mode(vm))) { > =C2=A0 err =3D -EINVAL;