From: Riana Tauro <riana.tauro@intel.com>
To: "Mallesh, Koujalagi" <mallesh.koujalagi@intel.com>
Cc: <anshuman.gupta@intel.com>, <rodrigo.vivi@intel.com>,
<aravind.iddamsetty@linux.intel.com>, <badal.nilawar@intel.com>,
<raag.jadav@intel.com>, <ravi.kishore.koppuravuri@intel.com>,
<intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v2 11/11] drm/xe/xe_pci_error: Process errors in mmio_enabled
Date: Wed, 11 Mar 2026 20:09:40 +0530 [thread overview]
Message-ID: <4fee6a95-1101-404a-909d-7f3654a8b129@intel.com> (raw)
In-Reply-To: <b308163f-a203-4cc4-b558-1de58fb1251c@intel.com>
Hi Mallesh
On 3/11/2026 12:40 PM, Mallesh, Koujalagi wrote:
>
> On 02-03-2026 03:52 pm, Riana Tauro wrote:
>> Query system controller when any non fatal error occurs to check
>> the type of the error, contain and recover.
>>
>> The system controller is queried in the mmio_enabled callback.
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> v2: use ras recovery enum (Raag)
>> ---
>> drivers/gpu/drm/xe/xe_pci_error.c | 13 ++++++++++++-
>> 1 file changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_pci_error.c b/drivers/gpu/drm/xe/
>> xe_pci_error.c
>> index ba62868f00d4..35bc5b8cee99 100644
>> --- a/drivers/gpu/drm/xe/xe_pci_error.c
>> +++ b/drivers/gpu/drm/xe/xe_pci_error.c
>> @@ -9,6 +9,7 @@
>> #include "xe_device.h"
>> #include "xe_gt.h"
>> #include "xe_pci.h"
>> +#include "xe_ras.h"
>> #include "xe_uc.h"
>> static void xe_pci_error_handling(struct pci_dev *pdev)
>> @@ -26,6 +27,12 @@ static void xe_pci_error_handling(struct pci_dev
>> *pdev)
>> pci_disable_device(pdev);
>> }
> Explain the mapping rationale
Do you mean commit message?
In the code the naming is self explanatory
>> +static pci_ers_result_t ras_recovery_action_to_pci_result[] = {
> The mapping array should be constant, never modified.
>> + [XE_RAS_RECOVERY_ACTION_RECOVERED] = PCI_ERS_RESULT_RECOVERED,
>> + [XE_RAS_RECOVERY_ACTION_RESET] = PCI_ERS_RESULT_NEED_RESET,
>> + [XE_RAS_RECOVERY_ACTION_DISCONNECT] = PCI_ERS_RESULT_DISCONNECT,
>> +};
>> +
>> static pci_ers_result_t xe_pci_error_detected(struct pci_dev *pdev,
>> pci_channel_state_t state)
>> {
>> struct xe_device *xe = pdev_to_xe_device(pdev);
>> @@ -50,9 +57,13 @@ static pci_ers_result_t
>> xe_pci_error_detected(struct pci_dev *pdev, pci_channel_
>> static pci_ers_result_t xe_pci_error_mmio_enabled(struct pci_dev *pdev)
>> {
>> + struct xe_device *xe = pdev_to_xe_device(pdev);
>> + enum xe_ras_recovery_action action;
> Add action_max @ end of enum to validate.
Answered below, but for consistency i can add max
>> +
>> dev_err(&pdev->dev, "Xe Pci error recovery: MMIO enabled\n");
>> + action = xe_ras_process_errors(xe);
> What will happen, if RAS processing takes significant time?
System controller times out after a duration. Refer patch
https://patchwork.freedesktop.org/patch/710637/?series=159554&rev=10
If the ret is negative in process_errors
+ ret = xe_sysctrl_send_command(xe, &command, &rlen);
+ if (ret || !rlen) {
+ xe_err(xe, "[RAS]: Sysctrl error ret %d\n", ret);
+ goto err;
+ }
+
We request for a reset assuming a SC error.
>> - return PCI_ERS_RESULT_NEED_RESET;
>
> Use array bound check before using action to avoid out of bounds array
> access
The action here comes from a xe_ras_process_errors which also returns
enum. This action is explicitly sent and is not coming from user
or firmware.
Adding a check here seems unnecessary.
Thanks
Riana
>
> Thanks,
>
> -/Mallesh
>
>> + return ras_recovery_action_to_pci_result[action];
>> }
>> static pci_ers_result_t xe_pci_error_slot_reset(struct pci_dev *pdev)
next prev parent reply other threads:[~2026-03-11 14:39 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-02 10:21 [PATCH v2 00/11] Introduce Xe Uncorrectable Error Handling Riana Tauro
2026-03-02 10:21 ` [PATCH v2 01/11] drm/xe/xe_sysctrl: Add System controller patch Riana Tauro
2026-03-02 10:21 ` [PATCH v2 02/11] drm/xe/xe_survivability: Decouple survivability info from boot survivability Riana Tauro
2026-03-02 17:00 ` Raag Jadav
2026-03-03 8:18 ` Mallesh, Koujalagi
2026-03-30 12:56 ` Tauro, Riana
2026-03-30 13:00 ` Tauro, Riana
2026-03-02 10:21 ` [PATCH v2 03/11] drm/xe/xe_pci_error: Implement PCI error recovery callbacks Riana Tauro
2026-03-02 17:37 ` Raag Jadav
2026-03-03 5:09 ` Riana Tauro
2026-03-04 10:38 ` Mallesh, Koujalagi
2026-03-31 5:18 ` Tauro, Riana
2026-03-02 10:21 ` [PATCH v2 04/11] drm/xe/xe_pci_error: Group all devres to release them on PCIe slot reset Riana Tauro
2026-03-02 10:22 ` [PATCH v2 05/11] drm/xe: Skip device access during PCI error recovery Riana Tauro
2026-03-04 10:59 ` Mallesh, Koujalagi
2026-03-02 10:22 ` [PATCH v2 06/11] drm/xe/xe_ras: Initialize Uncorrectable AER Registers Riana Tauro
2026-03-02 10:22 ` [PATCH v2 07/11] drm/xe/xe_ras: Add structures and commands for Uncorrectable Core Compute Errors Riana Tauro
2026-03-04 16:32 ` Raag Jadav
2026-03-31 16:14 ` Tauro, Riana
2026-04-01 6:25 ` Raag Jadav
2026-04-01 6:39 ` Tauro, Riana
2026-03-02 10:22 ` [PATCH v2 08/11] drm/xe/xe_ras: Add support for Uncorrectable Core-Compute errors Riana Tauro
2026-03-04 16:52 ` Raag Jadav
2026-03-06 18:37 ` Raag Jadav
2026-03-31 16:24 ` Tauro, Riana
2026-04-01 6:34 ` Raag Jadav
2026-04-01 6:47 ` Tauro, Riana
2026-03-06 3:50 ` [v2,08/11] " Purkait, Soham
2026-03-31 16:16 ` Tauro, Riana
2026-03-02 10:22 ` [PATCH v2 09/11] drm/xe/xe_ras: Add structures for SoC Internal errors Riana Tauro
2026-03-10 13:02 ` Mallesh, Koujalagi
2026-03-11 14:51 ` Riana Tauro
2026-03-02 10:22 ` [PATCH v2 10/11] drm/xe/xe_ras: Handle Uncorrectable " Riana Tauro
2026-03-10 13:29 ` Mallesh, Koujalagi
2026-03-11 14:55 ` Riana Tauro
2026-03-02 10:22 ` [PATCH v2 11/11] drm/xe/xe_pci_error: Process errors in mmio_enabled Riana Tauro
2026-03-11 7:10 ` Mallesh, Koujalagi
2026-03-11 14:39 ` Riana Tauro [this message]
2026-03-12 8:08 ` Mallesh, Koujalagi
2026-03-02 16:10 ` ✗ CI.checkpatch: warning for Introduce Xe Uncorrectable Error Handling (rev2) Patchwork
2026-03-02 16:11 ` ✓ CI.KUnit: success " Patchwork
2026-03-02 16:48 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-02 18:29 ` ✗ Xe.CI.FULL: failure " Patchwork
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