Re: [PATCH v4 06/13] drm/xe/xe_ras: Add basic structures and commands for uncorrectable errors

Matt Roper
2026-04-17T17:39:03Z

On Fri, Apr 17, 2026 at 02:28:18PM +0530, Riana Tauro wrote:
> Add the commands and common structures for the get_soc_error
> sysctrl command.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> v2: use macro max error details (Mallesh)
> use static_assert
> fix kernel-doc
>
> v3: simplify check (Raag)
> add counter value
>
> v4: use not_supported instead of unknown (Raag)
> ---
> drivers/gpu/drm/xe/xe_ras.c | 57 +++++++++++
> drivers/gpu/drm/xe/xe_ras_types.h | 96 +++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 13 +++
> 3 files changed, 166 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 4f705deaeefa..bf780e953925 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -3,9 +3,66 @@
> * Copyright © 2026 Intel Corporation
> */
>
> +#include "xe_assert.h"
> #include "xe_device_types.h"
> #include "xe_ras.h"
>
> +/* Severity classification of detected errors */
> +enum xe_ras_severity {
> + XE_RAS_SEVERITY_NOT_SUPPORTED = 0,
> + XE_RAS_SEVERITY_CORRECTABLE,
> + XE_RAS_SEVERITY_UNCORRECTABLE,
> + XE_RAS_SEVERITY_INFORMATIONAL,
> + XE_RAS_SEVERITY_MAX
> +};

Drive-by comment: I notice that there's a fair amount of common changes
between this uncorrectable series and Raag's correctable series, e.g.,
https://lore.kernel.org/all/20260410102744.427150-4-raag.jadav@intel.com/
However it seems that there have been some minor style differences
between the two that would be good to reconcile (e.g., this series
writes out the full XE_RAS_SEVERITY_*, XE_RAS_COMPONENT_*, etc. whereas
Raag's series uses slightly shorter XE_RAS_SEV_*, XE_RAS_COMP_*, etc.
names). Similar differences exist on some of the functions like
severity_to_string (taking both the device and the severity) here vs
sev_to_string (taking only the serverity) in the other series.

We should probably figure out which form we actually want to go with so
that we don't have last-minute conflicts as we start applying these
series.

Matt

> +
> +/* major IP blocks where errors can originate */
> +enum xe_ras_component {
> + XE_RAS_COMPONENT_NOT_SUPPORTED = 0,
> + XE_RAS_COMPONENT_DEVICE_MEMORY,
> + XE_RAS_COMPONENT_CORE_COMPUTE,
> + XE_RAS_COMPONENT_RESERVED,
> + XE_RAS_COMPONENT_PCIE,
> + XE_RAS_COMPONENT_FABRIC,
> + XE_RAS_COMPONENT_SOC_INTERNAL,
> + XE_RAS_COMPONENT_MAX
> +};
> +
> +static const char * const xe_ras_severities[] = {
> + [XE_RAS_SEVERITY_NOT_SUPPORTED] = "Not Supported",
> + [XE_RAS_SEVERITY_CORRECTABLE] = "Correctable",
> + [XE_RAS_SEVERITY_UNCORRECTABLE] = "Uncorrectable",
> + [XE_RAS_SEVERITY_INFORMATIONAL] = "Informational",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEVERITY_MAX);
> +
> +static const char * const xe_ras_components[] = {
> + [XE_RAS_COMPONENT_NOT_SUPPORTED] = "Not Supported",
> + [XE_RAS_COMPONENT_DEVICE_MEMORY] = "Device Memory",
> + [XE_RAS_COMPONENT_CORE_COMPUTE] = "Core Compute",
> + [XE_RAS_COMPONENT_RESERVED] = "Reserved",
> + [XE_RAS_COMPONENT_PCIE] = "PCIe",
> + [XE_RAS_COMPONENT_FABRIC] = "Fabric",
> + [XE_RAS_COMPONENT_SOC_INTERNAL] = "SoC Internal",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMPONENT_MAX);
> +
> +static inline const char *severity_to_str(struct xe_device *xe, u32 severity)
> +{
> + if (severity >= XE_RAS_SEVERITY_MAX)
> + severity = XE_RAS_SEVERITY_NOT_SUPPORTED;
> +
> + return xe_ras_severities[severity];
> +}
> +
> +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> +{
> + if (comp >= XE_RAS_COMPONENT_MAX)
> + comp = XE_RAS_COMPONENT_NOT_SUPPORTED;
> +
> + return xe_ras_components[comp];
> +}
> +
> #ifdef CONFIG_PCIEAER
> static void aer_unmask_and_downgrade_internal_error(struct xe_device *xe)
> {
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> new file mode 100644
> index 000000000000..3d0f9e94a404
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -0,0 +1,96 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_TYPES_H_
> +#define _XE_RAS_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#define XE_RAS_NUM_ERROR_ARR 3
> +#define XE_RAS_MAX_ERROR_DETAILS 16
> +
> +/**
> + * struct xe_ras_error_common - Common RAS error class
> + *
> + * This structure contains error severity and component information
> + * across all products
> + */
> +struct xe_ras_error_common {
> + /** @severity: Error Severity */
> + u8 severity;
> + /** @component: IP where the error originated */
> + u8 component;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_unit - Error unit information
> + */
> +struct xe_ras_error_unit {
> + /** @tile: Tile identifier */
> + u8 tile;
> + /** @instance: Instance identifier within a component */
> + u32 instance;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_cause - Error cause information
> + */
> +struct xe_ras_error_cause {
> + /** @cause: Cause */
> + u32 cause;
> + /** @reserved: For future use */
> + u8 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_product - Error fields that are specific to the product
> + */
> +struct xe_ras_error_product {
> + /** @unit: Unit within IP block */
> + struct xe_ras_error_unit unit;
> + /** @error_cause: Cause/checker */
> + struct xe_ras_error_cause error_cause;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_class - Complete RAS Error Class
> + *
> + * This structure provides the complete error classification by combining
> + * the common error class with the product-specific error class.
> + */
> +struct xe_ras_error_class {
> + /** @common: Common error severity and component */
> + struct xe_ras_error_common common;
> + /** @product: Product-specific unit and cause */
> + struct xe_ras_error_product product;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_array - Details of the error types
> + */
> +struct xe_ras_error_array {
> + /** @counter_value: Counter value of the returned error */
> + u32 counter_value;
> + /** @error_class: Error class */
> + struct xe_ras_error_class error_class;
> + /** @timestamp: Timestamp */
> + u64 timestamp;
> + /** @error_details: Error details specific to the class */
> + u32 error_details[XE_RAS_MAX_ERROR_DETAILS];
> +} __packed;
> +
> +/**
> + * struct xe_ras_get_error_response - Response from get soc error command
> + */
> +struct xe_ras_get_error_response {
> + /** @num_errors: Number of errors reported in this response */
> + u8 num_errors;
> + /** @additional_errors: Indicates if the errors are pending */
> + u8 additional_errors;
> + /** @error_arr: Array of up to 3 errors */
> + struct xe_ras_error_array error_arr[XE_RAS_NUM_ERROR_ARR];
> +} __packed;
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> index 89456aec6097..00a0f05aab32 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> @@ -10,6 +10,19 @@
>
> #include "abi/xe_sysctrl_abi.h"
>
> +/**
> + * enum xe_sysctrl_mailbox_command_id - Command ID's for GFSP group
> + *
> + * @XE_SYSCTRL_CMD_GET_SOC_ERROR: Get basic error information
> + */
> +enum xe_sysctrl_mailbox_command_id {
> + XE_SYSCTRL_CMD_GET_SOC_ERROR = 0x01
> +};
> +
> +enum xe_sysctrl_group {
> + XE_SYSCTRL_GROUP_GFSP = 1
> +};
> +
> /**
> * struct xe_sysctrl_mailbox_command - System Controller mailbox command
> */
> --
> 2.47.1
>

--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation