RE: [PATCH v4 09/13] drm/xe/xe_ras: Handle uncorrectable device memory errors

Upadhyay, Tejas
2026-04-21T06:09:04Z

> -----Original Message-----
> From: Tauro, Riana <riana.tauro@intel.com>
> Sent: 17 April 2026 14:28
> To: intel-xe@lists.freedesktop.org
> Cc: Tauro, Riana <riana.tauro@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> aravind.iddamsetty@linux.intel.com; Nilawar, Badal
> <badal.nilawar@intel.com>; Jadav, Raag <raag.jadav@intel.com>;
> Koppuravuri, Ravi Kishore <ravi.kishore.koppuravuri@intel.com>; Koujalagi,
> Mallesh <mallesh.koujalagi@intel.com>; Purkait, Soham
> <soham.purkait@intel.com>; Upadhyay, Tejas <tejas.upadhyay@intel.com>;
> Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>
> Subject: [PATCH v4 09/13] drm/xe/xe_ras: Handle uncorrectable device
> memory errors
>
> Add support to handle uncorrectable device memory errors. Double bit ECC
> (Error Correcting Code) errors are logged. These will be handled using Page
> offlining in a later patch. The other memory error categories require a
> Secondary bus reset (SBR) to recover.
>
> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> Memory offlining patch will be integrated once
> https://patchwork.freedesktop.org/series/161473/ is merged.
> ---
> drivers/gpu/drm/xe/xe_ras.c | 23 ++++++++++++
> drivers/gpu/drm/xe/xe_ras_types.h | 61
> +++++++++++++++++++++++++++++++
> 2 files changed, 84 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c index
> 5010cf6211ea..347844b3d2bf 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -138,6 +138,26 @@ static enum xe_ras_recovery_action
> handle_soc_internal_errors(struct xe_device *
> return XE_RAS_RECOVERY_ACTION_RESET;
> }
>
> +static enum xe_ras_recovery_action handle_memory_errors(struct xe_device
> *xe,
> + struct
> xe_ras_error_array *arr)
> +{
> + struct xe_ras_memory_error *error_info = (struct
> xe_ras_memory_error *)arr->error_details;
> + struct xe_ras_error_category category = error_info->category;
> + struct xe_ras_error_common common = arr->error_class.common;
> +
> + xe_err(xe, "[RAS]: %s %s Error detected", severity_to_str(xe,
> common.severity),
> + comp_to_str(xe, common.component));

don't need \n?

> +
> + if (category.ecc_error) {
> + xe_err(xe, "[RAS]: Double bit ECC error detected at sw address
> 0x%llx\n",
> + (unsigned long long)error_info->sw_address);
> + /* TODO: page offline handling for 2-bit ECC errors and return
> accordingly */
> + }
> +
> + /* Request a RESET for other device memory error categories */
> + return XE_RAS_RECOVERY_ACTION_RESET;
> +}
> +
> static void prepare_sysctrl_command(struct xe_sysctrl_mailbox_command
> *command,
> u32 cmd_mask, void *request, size_t
> request_len,
> void *response, size_t response_len) @@ -
> 217,6 +237,9 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct
> xe_device *xe)
> case XE_RAS_COMPONENT_SOC_INTERNAL:
> action = handle_soc_internal_errors(xe, &arr);
> break;
> + case XE_RAS_COMPONENT_DEVICE_MEMORY:
> + action = handle_memory_errors(xe, &arr);
> + break;
> default:
> xe_err(xe, "[RAS]: Unknown error component
> %u\n", component);
> action = XE_RAS_RECOVERY_ACTION_RESET;
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h
> b/drivers/gpu/drm/xe/xe_ras_types.h
> index 4f640124f38f..020e3f92a057 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -199,4 +199,65 @@ struct xe_ras_ieh_error {
> /** @additional_info: Additional information */
> u32 additional_info[10];
> } __packed;
> +
> +/**
> + * struct xe_ras_hardware_address - Device memory hardware address
> +details
> + *
> + * Hardware physical address structure for device memory error reporting.
> + */
> +struct xe_ras_hardware_address {
> + /** @column: Column address */
> + u64 column:6;
> + /** @bank: Bank */
> + u64 bank:2;
> + /** @bank_group: Bank group */
> + u64 bank_group:2;
> + /** @row: Row address */
> + u64 row:16;
> + /** @channel: Memory Channel */
> + u64 channel:8;
> + /** @msu: MSU index */
> + u64 msu:8;
> + /** @reserved: Reserved for future use */
> + u64 reserved:22;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_category - Device memory error category details
> +*/ struct xe_ras_error_category {
> + /** @pma_error: PMA (Power Management Agent) error */
> + u8 pma_error:1;
> + /** @ecc_error: Double bit ECC error */
> + u8 ecc_error:1;
> + /** @poison_detected: Write poison detected */
> + u8 poison_detected:1;
> + /** @parity_error: Parity error */
> + u8 parity_error:1;
> + /** @phy_error: PHY error */
> + u8 phy_error:1;
> + /** @reserved: Reserved for future use */
> + u8 reserved:3;
> +} __packed;
> +
> +/**
> + * struct xe_ras_memory_error - Device memory error details
> + *
> + * This structure provides detailed information about a device memory error.
> + * Cast from error_details array for device memory errors.
> + */
> +struct xe_ras_memory_error {
> + /** @category: Device memory error category */
> + struct xe_ras_error_category category;
> + /** @reserved: Reserved for future use */
> + u8 reserved[7];
> + /** @hw_address: Memory hardware physical address */
> + struct xe_ras_hardware_address hw_address;
> + /** @sw_address: Software address where error occurred */

Introduced but not used, can be moved to next patch?

Tejas
> + u64 sw_address;
> + /** @log_array: Error syndromes associated with the error */
> + u32 log_array[8];
> + /** @reserved2: Reserved for future use */
> + u32 reserved2[2];
> +} __packed;
> #endif
> --
> 2.47.1