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From: "Yadav, Arvind" <arvind.yadav@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: <intel-xe@lists.freedesktop.org>,
	Nitin Gote <nitin.r.gote@intel.com>,
	Tejas Upadhyay <tejas.upadhyay@intel.com>
Subject: Re: [PATCH] drm/xe/xe2_hpg: Apply Wa_14024997852
Date: Tue, 10 Feb 2026 10:38:32 +0530	[thread overview]
Message-ID: <55856ba2-6bf9-44b3-aa08-3d48ae38b15f@intel.com> (raw)
In-Reply-To: <20260209202310.GF458797@mdroper-desk1.amr.corp.intel.com>


On 10-02-2026 01:53, Matt Roper wrote:
> On Thu, Feb 05, 2026 at 10:38:18AM +0530, Arvind Yadav wrote:
>> Applied Wa_14024997852 to Graphics version 20.02
>>
>> Cc: Nitin Gote <nitin.r.gote@intel.com>
>> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
>> Signed-off-by: Arvind Yadav <arvind.yadav@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_wa.c | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>> index 1e8d61ac581b..2f838c99596f 100644
>> --- a/drivers/gpu/drm/xe/xe_wa.c
>> +++ b/drivers/gpu/drm/xe/xe_wa.c
>> @@ -874,6 +874,17 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>>   	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
>>   	},
>>   
>> +	{ XE_RTP_NAME("14024997852"),
>> +	  XE_RTP_RULES(GRAPHICS_VERSION(2002), GRAPHICS_STEP(A0, B0),
>> +		       ENGINE_CLASS(RENDER)),
>> +	  XE_RTP_ACTIONS(SET(FF_MODE,
>> +			     DIS_MESH_PARTIAL_AUTOSTRIP |
>> +			     DIS_MESH_AUTOSTRIP),
>> +			 SET(VFLSKPD,
>> +			     DIS_PARTIAL_AUTOSTRIP |
>> +			     DIS_AUTOSTRIP))
> This workaround asks that these settings be programmed only in specific
> cases (primitive ID enabled || cut index enabled).  That's referring to
> 3D state that's controlled by the UMD and may change on a batch-by-batch
> basis.  So we shouldn't be doing this programming directly in the
> kernel, otherwise it will be in effect even at times we don't want it to
> be.  Instead we just need to whitelist these registers to allow the UMD
> to make the necessary changes on the fly.
>
> We already whitelist these for the Xe3 platforms; the necessary change
> is to also extend that whitelisting back to some of the Xe2 IPs.


Noted, sorry I missed the comment. I will send v3 by whitelisting this.

Thanks,
Arvind

>
>
> Matt
>
>> +	},
>> +
>>   	/* Xe3_LPG */
>>   	{ XE_RTP_NAME("14021490052"),
>>   	  XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0),
>> -- 
>> 2.43.0
>>

      reply	other threads:[~2026-02-10  5:08 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-05  5:08 [PATCH] drm/xe/xe2_hpg: Apply Wa_14024997852 Arvind Yadav
2026-02-05  7:45 ` ✓ CI.KUnit: success for " Patchwork
2026-02-05  8:21 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-06  3:25 ` ✓ Xe.CI.FULL: " Patchwork
2026-02-09  6:40 ` [PATCH] " Gote, Nitin R
2026-02-09 11:49   ` Yadav, Arvind
2026-02-09 20:23 ` Matt Roper
2026-02-10  5:08   ` Yadav, Arvind [this message]

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