[PATCH v3 0/3] USE drm mm instead of drm SA for CCS read/write

[PATCH v3 0/3] USE drm mm instead of drm SA for CCS read/write

[Satyanarayana K V P]

The suballocator algorithm tracks a hole cursor at the last allocation
and tries to allocate after it. This is optimized for fence-ordered
progress, where older allocations are expected to become reusable first.

In fence-enabled mode, that ordering assumption holds. In fence-disabled
mode, allocations may be freed in arbitrary order, so limiting allocation
to the current hole window can miss valid free space and fail allocations
despite sufficient total space.

Use DRM memory manager instead of sub-allocator to get rid of this issue
as CCS read/write operations do not use fences.

Used drm mm instead of drm sa based on comments from
https://lore.kernel.org/all/bbf0d48d-a95a-46e1-ac8f-e8a0daa81365@amd.com/

---
V2 -> V3:
- Used xe_mem_pool_init() and xe_mem_pool_shadow_init() to allocate BB
pools.
- Renamed xe_mm_suballoc to xe_mem_pool_manager
- Splitted xe_mm_suballoc_manager_init() into xe_mem_pool_init() and
xe_mem_pool_shadow_init() (Michal)
- Made xe_mm_sa_manager structure private. (Matt)
- Introduced init flags to initialize allocated pools.

V1 -> V2:
- Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
- Removed memset from xe_drm_mm_bb_insert() (Matt).
- Removed memset during manager init and insert (Matt)

Satyanarayana K V P (3):
  drm/xe/mm: add XE MEM POOL manager with shadow support
  drm/xe/mm: Add batch buffer allocation functions for xe_mem_pool
    manager
  drm/xe/vf: Use drm mm instead of drm sa for CCS read/write

 drivers/gpu/drm/xe/Makefile                |   1 +
 drivers/gpu/drm/xe/xe_bb.c                 |  58 ++++
 drivers/gpu/drm/xe/xe_bb.h                 |   6 +
 drivers/gpu/drm/xe/xe_bo_types.h           |   3 +-
 drivers/gpu/drm/xe/xe_mem_pool.c           | 379 +++++++++++++++++++++
 drivers/gpu/drm/xe/xe_mem_pool.h           |  33 ++
 drivers/gpu/drm/xe/xe_mem_pool_types.h     |  30 ++
 drivers/gpu/drm/xe/xe_migrate.c            |  56 +--
 drivers/gpu/drm/xe/xe_sriov_vf_ccs.c       |  48 ++-
 drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h |   5 +-
 10 files changed, 563 insertions(+), 56 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.c
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.h
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool_types.h

-- 
2.43.0

[PATCH v3 1/3] drm/xe/mm: add XE MEM POOL manager with shadow support

[Satyanarayana K V P]

Add a xe_mem_pool manager to allocate sub-ranges from a BO-backed pool
using drm_mm.

Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Maarten Lankhorst <dev@lankhorst.se>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>

---
V2 -> V3:
- Renamed xe_mm_suballoc to xe_mem_pool_manager.
- Splitted xe_mm_suballoc_manager_init() into xe_mem_pool_init() and
xe_mem_pool_shadow_init() (Michal)
- Made xe_mm_sa_manager structure private. (Matt)
- Introduced init flags to initialize allocated pools.

V1 -> V2:
- Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
- Removed memset during manager init and insert (Matt)
---
 drivers/gpu/drm/xe/Makefile            |   1 +
 drivers/gpu/drm/xe/xe_mem_pool.c       | 379 +++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_mem_pool.h       |  33 +++
 drivers/gpu/drm/xe/xe_mem_pool_types.h |  30 ++
 4 files changed, 443 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.c
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.h
 create mode 100644 drivers/gpu/drm/xe/xe_mem_pool_types.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 9dacb0579a7d..8e31b14239ec 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -88,6 +88,7 @@ xe-y += xe_bb.o \
 	xe_irq.o \
 	xe_late_bind_fw.o \
 	xe_lrc.o \
+	xe_mem_pool.o \
 	xe_migrate.o \
 	xe_mmio.o \
 	xe_mmio_gem.o \
diff --git a/drivers/gpu/drm/xe/xe_mem_pool.c b/drivers/gpu/drm/xe/xe_mem_pool.c
new file mode 100644
index 000000000000..335a70876bf1
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_mem_pool.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/kernel.h>
+
+#include <drm/drm_managed.h>
+
+#include "instructions/xe_mi_commands.h"
+#include "xe_bo.h"
+#include "xe_device_types.h"
+#include "xe_map.h"
+#include "xe_mem_pool.h"
+#include "xe_mem_pool_types.h"
+
+/**
+ * struct xe_mem_pool_manager - Memory Suballoc manager.
+ */
+
+struct xe_mem_pool_manager {
+	/** @base: Range allocator over [0, @size) in bytes */
+	struct drm_mm base;
+	/** @bo: Active pool BO (GGTT-pinned, CPU-mapped). */
+	struct xe_bo *bo;
+	/** @shadow: Shadow BO for atomic command updates. */
+	struct xe_bo *shadow;
+	/** @swap_guard: Timeline guard updating @bo and @shadow */
+	struct mutex swap_guard;
+	/** @cpu_addr: CPU virtual address of the active BO. */
+	void *cpu_addr;
+	/** @resv_alloc: Reserved allocation. */
+	struct drm_mm_node *resv_alloc;
+	/** @size: Total size of the managed address space. */
+	u64 size;
+};
+
+static void xe_mem_pool_fini(struct drm_device *drm, void *arg)
+{
+	struct xe_mem_pool_manager *pool_manager = arg;
+
+	drm_mm_takedown(&pool_manager->base);
+
+	if (pool_manager->resv_alloc) {
+		drm_mm_remove_node(pool_manager->resv_alloc);
+		kfree(pool_manager->resv_alloc);
+	}
+
+	if (pool_manager->bo->vmap.is_iomem)
+		kvfree(pool_manager->cpu_addr);
+
+	pool_manager->bo = NULL;
+	pool_manager->shadow = NULL;
+}
+
+static int xe_mem_pool_init_flags(struct xe_mem_pool_manager *mm_pool, u32 size, int flags)
+{
+	struct xe_bo *bo = mm_pool->bo;
+	struct drm_mm_node *node;
+	struct xe_device *xe;
+	u32 initializer;
+	int err;
+
+	if (!flags)
+		return 0;
+
+	if (flags & XE_MEM_POOL_BO_FLAG_INIT_ZERO_FILL)
+		initializer = 0;
+	else if (flags & XE_MEM_POOL_BO_FLAG_INIT_CMD_NOOP ||
+		 flags & XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST)
+		initializer = MI_NOOP;
+	else
+		return -EINVAL;
+
+	xe = tile_to_xe(bo->tile);
+	if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY) {
+		bo = mm_pool->shadow;
+		xe_map_memset(xe, &bo->vmap, 0, initializer, size);
+
+		node = mm_pool->resv_alloc;
+		xe_map_memcpy_to(xe, &mm_pool->shadow->vmap,
+				 node->start,
+				 mm_pool->cpu_addr + node->start,
+				 node->size);
+		return 0;
+	}
+
+	xe_map_memset(xe, &bo->vmap, 0, initializer, size);
+
+	if (flags & XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST) {
+		node = kzalloc_obj(*node);
+		if (!node)
+			return -ENOMEM;
+
+		err = drm_mm_insert_node_in_range(&mm_pool->base, node, SZ_4,
+						  0, 0, 0, size, DRM_MM_INSERT_HIGHEST);
+		if (err) {
+			kfree(node);
+			return err;
+		}
+		xe_map_wr(xe, &mm_pool->bo->vmap, node->start, u32, MI_BATCH_BUFFER_END);
+		mm_pool->resv_alloc = node;
+	}
+	return 0;
+}
+
+/**
+ * xe_mem_pool_init() - Initialize a DRM MM pool.
+ * @tile: the &xe_tile where allocate.
+ * @size: number of bytes to allocate.
+ * @flags: flags to use for BO creation.
+ *
+ * Initializes a DRM MM manager for managing memory allocations on a specific
+ * XE tile. The function allocates a buffer object to back the memory region
+ * managed by the DRM MM manager.
+ *
+ * Return: a pointer to the &xe_mem_pool_manager, or an error pointer on failure.
+ */
+struct xe_mem_pool_manager *xe_mem_pool_init(struct xe_tile *tile, u32 size, int flags)
+{
+	struct xe_device *xe = tile_to_xe(tile);
+	struct xe_mem_pool_manager *pool_manager;
+	struct xe_bo *bo;
+	int ret;
+
+	pool_manager = drmm_kzalloc(&xe->drm, sizeof(*pool_manager), GFP_KERNEL);
+	if (!pool_manager)
+		return ERR_PTR(-ENOMEM);
+
+	bo = xe_managed_bo_create_pin_map(xe, tile, size,
+					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+					  XE_BO_FLAG_GGTT |
+					  XE_BO_FLAG_GGTT_INVALIDATE |
+					  XE_BO_FLAG_PINNED_NORESTORE);
+	if (IS_ERR(bo)) {
+		drm_err(&xe->drm, "Failed to prepare %uKiB BO for DRM MM manager (%pe)\n",
+			size / SZ_1K, bo);
+		return ERR_CAST(bo);
+	}
+	pool_manager->bo = bo;
+	pool_manager->size = size;
+
+	if (bo->vmap.is_iomem) {
+		pool_manager->cpu_addr = kvzalloc(size, GFP_KERNEL);
+		if (!pool_manager->cpu_addr)
+			return ERR_PTR(-ENOMEM);
+	} else {
+		pool_manager->cpu_addr = bo->vmap.vaddr;
+	}
+
+	drm_mm_init(&pool_manager->base, 0, size);
+	ret = drmm_add_action_or_reset(&xe->drm, xe_mem_pool_fini, pool_manager);
+	if (ret)
+		return ERR_PTR(ret);
+
+	ret = xe_mem_pool_init_flags(pool_manager, size, flags);
+	if (ret)
+		return ERR_PTR(ret);
+
+	return pool_manager;
+}
+
+/**
+ * xe_mem_pool_shadow_init() - Initialize the shadow BO for a DRM MM manager.
+ * @pool_manager: the DRM MM manager to initialize the shadow BO for.
+ * @flags: flags to use for BO creation.
+ *
+ * Initializes the shadow buffer object for the specified DRM MM manager. The
+ * shadow BO is used for atomic command updates and is created with the same
+ * size and properties as the primary BO.
+ *
+ * Return: 0 on success, or a negative error code on failure.
+ */
+int xe_mem_pool_shadow_init(struct xe_mem_pool_manager *pool_manager, int flags)
+{
+	struct xe_tile *tile = pool_manager->bo->tile;
+	struct xe_device *xe = tile_to_xe(tile);
+	struct xe_bo *shadow;
+	int ret;
+
+	xe_assert(xe, !pool_manager->shadow);
+
+	ret = drmm_mutex_init(&xe->drm, &pool_manager->swap_guard);
+	if (ret)
+		return ret;
+
+	if (IS_ENABLED(CONFIG_PROVE_LOCKING)) {
+		fs_reclaim_acquire(GFP_KERNEL);
+		might_lock(&pool_manager->swap_guard);
+		fs_reclaim_release(GFP_KERNEL);
+	}
+	shadow = xe_managed_bo_create_pin_map(xe, tile, pool_manager->size,
+					      XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+					      XE_BO_FLAG_GGTT |
+					      XE_BO_FLAG_GGTT_INVALIDATE |
+					      XE_BO_FLAG_PINNED_NORESTORE);
+	if (IS_ERR(shadow))
+		return PTR_ERR(shadow);
+
+	pool_manager->shadow = shadow;
+
+	ret = xe_mem_pool_init_flags(pool_manager, pool_manager->size,
+				     flags | XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/**
+ * xe_mem_pool_swap_shadow_locked() - Swap the primary BO with the shadow BO.
+ * @pool_manager: the DRM MM manager containing the primary and shadow BOs.
+ *
+ * Swaps the primary buffer object with the shadow buffer object in the DRM MM
+ * manager. This function must be called with the swap_guard mutex held to
+ * ensure synchronization with any concurrent operations that may be accessing
+ * the BOs.
+ *
+ * Return: None.
+ */
+void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool_manager *pool_manager)
+{
+	struct xe_tile *tile = pool_manager->bo->tile;
+
+	xe_tile_assert(tile, pool_manager->shadow);
+	lockdep_assert_held(&pool_manager->swap_guard);
+
+	swap(pool_manager->bo, pool_manager->shadow);
+	if (!pool_manager->bo->vmap.is_iomem)
+		pool_manager->cpu_addr = pool_manager->bo->vmap.vaddr;
+}
+
+/**
+ * xe_mem_pool_sync_shadow_locked() - Synchronize the shadow BO with the primary BO.
+ * @pool_manager: the DRM MM manager containing the primary and shadow BOs.
+ * @node: the DRM MM node representing the region to synchronize.
+ *
+ * Copies the contents of the specified region from the primary buffer object to
+ * the shadow buffer object in the DRM MM manager.
+ * Swap_guard must be held to ensure synchronization with any concurrent swap
+ * operations.
+ *
+ * Return: None.
+ */
+void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_manager *pool_manager,
+				    struct drm_mm_node *node)
+{
+	struct xe_tile *tile = pool_manager->bo->tile;
+	struct xe_device *xe = tile_to_xe(tile);
+
+	xe_tile_assert(tile, pool_manager->shadow);
+	lockdep_assert_held(&pool_manager->swap_guard);
+
+	xe_map_memcpy_to(xe, &pool_manager->shadow->vmap,
+			 node->start,
+			 pool_manager->cpu_addr + node->start,
+			 node->size);
+}
+
+/**
+ * xe_mem_pool_insert_node() - Insert a node into the DRM MM manager.
+ * @pool_manager: the DRM MM manager to insert the node into.
+ * @node: the DRM MM node to insert.
+ * @size: the size of the node to insert.
+ *
+ * Inserts a node into the DRM MM manager and clears the corresponding memory region
+ * in both the primary and shadow buffer objects.
+ *
+ * Return: 0 on success, or a negative error code on failure.
+ */
+int xe_mem_pool_insert_node(struct xe_mem_pool_manager *pool_manager,
+			    struct drm_mm_node *node, u32 size)
+{
+	struct drm_mm *mm = &pool_manager->base;
+	int ret;
+
+	ret = drm_mm_insert_node(mm, node, size);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/**
+ * xe_mem_pool_remove_node() - Remove a node from the DRM MM manager.
+ * @node: the DRM MM node to remove.
+ *
+ * Return: None.
+ */
+void xe_mem_pool_remove_node(struct drm_mm_node *node)
+{
+	return drm_mm_remove_node(node);
+}
+
+/**
+ * xe_mem_pool_manager_gpu_addr() - Retrieve GPU address of BO within a memory manager.
+ * @pool_manager: The DRM MM memory manager.
+ *
+ * Returns: GGTT address of the back storage BO
+ */
+u64 xe_mem_pool_manager_gpu_addr(struct xe_mem_pool_manager *pool_manager)
+{
+	return xe_bo_ggtt_addr(pool_manager->bo);
+}
+
+/**
+ * xe_mem_pool_manager_cpu_addr() - Retrieve CPU address of BO within a memory manager.
+ * @pool_manager: The DRM MM memory manager.
+ *
+ * Returns: CPU virtual address of BO.
+ */
+void *xe_mem_pool_manager_cpu_addr(struct xe_mem_pool_manager *pool_manager)
+{
+	return pool_manager->cpu_addr;
+}
+
+/**
+ * xe_mem_pool_bo_swap_guard() - Retrieve the mutex used to guard swap operations
+ * on a memory manager.
+ * @pool_manager: The DRM MM memory manager.
+ *
+ * Returns: Swap guard mutex.
+ */
+struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool_manager *pool_manager)
+{
+	return &pool_manager->swap_guard;
+}
+
+/**
+ * xe_mem_pool_dump() - Dump the state of the DRM MM manager for debugging.
+ * @pool_manager: The DRM MM manager to dump.
+ * @p: The DRM printer to use for output.
+ *
+ * Returns: None.
+ */
+void xe_mem_pool_dump(struct xe_mem_pool_manager *pool_manager, struct drm_printer *p)
+{
+	drm_mm_print(&pool_manager->base, p);
+}
+
+static inline struct xe_mem_pool_manager *to_xe_mem_pool_manager(struct drm_mm *mng)
+{
+	return container_of(mng, struct xe_mem_pool_manager, base);
+}
+
+/**
+ * xe_mem_pool_bo_flush_write() - Copy the data from the sub-allocation
+ * to the GPU memory.
+ * @node: the &drm_mm_node to flush
+ */
+void xe_mem_pool_bo_flush_write(struct drm_mm_node *node)
+{
+	struct xe_mem_pool_manager *pool_manager = to_xe_mem_pool_manager(node->mm);
+	struct xe_device *xe = tile_to_xe(pool_manager->bo->tile);
+
+	if (!pool_manager->bo->vmap.is_iomem)
+		return;
+
+	xe_map_memcpy_to(xe, &pool_manager->bo->vmap, node->start,
+			 pool_manager->cpu_addr + node->start,
+			 node->size);
+}
+
+/**
+ * xe_mem_pool_bo_sync_read() - Copy the data from GPU memory to the
+ * sub-allocation.
+ * @node: the &&drm_mm_node to sync
+ */
+void xe_mem_pool_bo_sync_read(struct drm_mm_node *node)
+{
+	struct xe_mem_pool_manager *pool_manager = to_xe_mem_pool_manager(node->mm);
+	struct xe_device *xe = tile_to_xe(pool_manager->bo->tile);
+
+	if (!pool_manager->bo->vmap.is_iomem)
+		return;
+
+	xe_map_memcpy_from(xe, pool_manager->cpu_addr + node->start,
+			   &pool_manager->bo->vmap, node->start, node->size);
+}
diff --git a/drivers/gpu/drm/xe/xe_mem_pool.h b/drivers/gpu/drm/xe/xe_mem_pool.h
new file mode 100644
index 000000000000..f9c5d1e56dd9
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_mem_pool.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+#ifndef _XE_MEM_POOL_H_
+#define _XE_MEM_POOL_H_
+
+#include <linux/sizes.h>
+#include <linux/types.h>
+
+#include "drm/drm_mm.h"
+#include "xe_mem_pool_types.h"
+
+struct drm_printer;
+struct xe_mem_pool_manager;
+struct xe_tile;
+
+struct xe_mem_pool_manager *xe_mem_pool_init(struct xe_tile *tile, u32 size, int flags);
+int xe_mem_pool_shadow_init(struct xe_mem_pool_manager *drm_mm_manager, int flags);
+void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool_manager *drm_mm_manager);
+void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_manager *drm_mm_manager,
+				    struct drm_mm_node *node);
+int xe_mem_pool_insert_node(struct xe_mem_pool_manager *drm_mm_manager,
+			    struct drm_mm_node *node, u32 size);
+void xe_mem_pool_remove_node(struct drm_mm_node *node);
+u64 xe_mem_pool_manager_gpu_addr(struct xe_mem_pool_manager *drm_mm_manager);
+void *xe_mem_pool_manager_cpu_addr(struct xe_mem_pool_manager *mm_manager);
+struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool_manager *drm_mm_manager);
+void xe_mem_pool_dump(struct xe_mem_pool_manager *mm_manager, struct drm_printer *p);
+void xe_mem_pool_bo_flush_write(struct drm_mm_node *node);
+void xe_mem_pool_bo_sync_read(struct drm_mm_node *node);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_mem_pool_types.h b/drivers/gpu/drm/xe/xe_mem_pool_types.h
new file mode 100644
index 000000000000..bae7706aa8d2
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_mem_pool_types.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_MEM_POOL_TYPES_H_
+#define _XE_MEM_POOL_TYPES_H_
+
+#include <drm/drm_mm.h>
+
+struct xe_mem_pool_manager;
+
+#define XE_MEM_POOL_BO_FLAG_INIT_ZERO_FILL			BIT(0)
+#define XE_MEM_POOL_BO_FLAG_INIT_CMD_NOOP			BIT(1)
+#define XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST		BIT(2)
+#define XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY			BIT(3)
+
+/**
+ * struct xe_mem_pool_bb - Sub allocated batch buffer from mem pool.
+ */
+struct xe_mem_pool_bb {
+	/** @node: Range node for this batch buffer. */
+	struct drm_mm_node node;
+	/** @cs: Command stream for this batch buffer. */
+	u32 *cs;
+	/** @len: Length of the CS in dwords. */
+	u32 len;
+};
+
+#endif
-- 
2.43.0

Re: [PATCH v3 1/3] drm/xe/mm: add XE MEM POOL manager with shadow support

[Matthew Brost]

On Wed, Apr 01, 2026 at 04:15:26PM +0000, Satyanarayana K V P wrote:
> Add a xe_mem_pool manager to allocate sub-ranges from a BO-backed pool
> using drm_mm.
> 
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> ---
> V2 -> V3:
> - Renamed xe_mm_suballoc to xe_mem_pool_manager.
> - Splitted xe_mm_suballoc_manager_init() into xe_mem_pool_init() and
> xe_mem_pool_shadow_init() (Michal)
> - Made xe_mm_sa_manager structure private. (Matt)
> - Introduced init flags to initialize allocated pools.
> 
> V1 -> V2:
> - Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
> - Removed memset during manager init and insert (Matt)
> ---
>  drivers/gpu/drm/xe/Makefile            |   1 +
>  drivers/gpu/drm/xe/xe_mem_pool.c       | 379 +++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_mem_pool.h       |  33 +++
>  drivers/gpu/drm/xe/xe_mem_pool_types.h |  30 ++
>  4 files changed, 443 insertions(+)
>  create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.c
>  create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.h
>  create mode 100644 drivers/gpu/drm/xe/xe_mem_pool_types.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 9dacb0579a7d..8e31b14239ec 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -88,6 +88,7 @@ xe-y += xe_bb.o \
>  	xe_irq.o \
>  	xe_late_bind_fw.o \
>  	xe_lrc.o \
> +	xe_mem_pool.o \
>  	xe_migrate.o \
>  	xe_mmio.o \
>  	xe_mmio_gem.o \
> diff --git a/drivers/gpu/drm/xe/xe_mem_pool.c b/drivers/gpu/drm/xe/xe_mem_pool.c
> new file mode 100644
> index 000000000000..335a70876bf1
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_mem_pool.c
> @@ -0,0 +1,379 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <linux/kernel.h>
> +
> +#include <drm/drm_managed.h>
> +
> +#include "instructions/xe_mi_commands.h"
> +#include "xe_bo.h"
> +#include "xe_device_types.h"
> +#include "xe_map.h"
> +#include "xe_mem_pool.h"
> +#include "xe_mem_pool_types.h"
> +
> +/**
> + * struct xe_mem_pool_manager - Memory Suballoc manager.
> + */
> +
> +struct xe_mem_pool_manager {
> +	/** @base: Range allocator over [0, @size) in bytes */
> +	struct drm_mm base;
> +	/** @bo: Active pool BO (GGTT-pinned, CPU-mapped). */
> +	struct xe_bo *bo;
> +	/** @shadow: Shadow BO for atomic command updates. */
> +	struct xe_bo *shadow;
> +	/** @swap_guard: Timeline guard updating @bo and @shadow */
> +	struct mutex swap_guard;
> +	/** @cpu_addr: CPU virtual address of the active BO. */
> +	void *cpu_addr;
> +	/** @resv_alloc: Reserved allocation. */
> +	struct drm_mm_node *resv_alloc;
> +	/** @size: Total size of the managed address space. */
> +	u64 size;
> +};
> +
> +static void xe_mem_pool_fini(struct drm_device *drm, void *arg)
> +{
> +	struct xe_mem_pool_manager *pool_manager = arg;
> +
> +	drm_mm_takedown(&pool_manager->base);

CI [1] doesn't like this takedown for whatever reason...

[1] https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/bat-ptl-vm/igt@core_hotunplug@unbind-rebind.html

It is likely pool_manager->resv_alloc needs to be called before drm_mm_takedown.

> +
> +	if (pool_manager->resv_alloc) {
> +		drm_mm_remove_node(pool_manager->resv_alloc);
> +		kfree(pool_manager->resv_alloc);
> +	}
> +
> +	if (pool_manager->bo->vmap.is_iomem)
> +		kvfree(pool_manager->cpu_addr);
> +
> +	pool_manager->bo = NULL;
> +	pool_manager->shadow = NULL;
> +}
> +
> +static int xe_mem_pool_init_flags(struct xe_mem_pool_manager *mm_pool, u32 size, int flags)
> +{
> +	struct xe_bo *bo = mm_pool->bo;
> +	struct drm_mm_node *node;
> +	struct xe_device *xe;
> +	u32 initializer;
> +	int err;
> +
> +	if (!flags)
> +		return 0;
> +
> +	if (flags & XE_MEM_POOL_BO_FLAG_INIT_ZERO_FILL)
> +		initializer = 0;
> +	else if (flags & XE_MEM_POOL_BO_FLAG_INIT_CMD_NOOP ||
> +		 flags & XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST)
> +		initializer = MI_NOOP;
> +	else
> +		return -EINVAL;
> +
> +	xe = tile_to_xe(bo->tile);
> +	if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY) {
> +		bo = mm_pool->shadow;
> +		xe_map_memset(xe, &bo->vmap, 0, initializer, size);
> +
> +		node = mm_pool->resv_alloc;
> +		xe_map_memcpy_to(xe, &mm_pool->shadow->vmap,
> +				 node->start,
> +				 mm_pool->cpu_addr + node->start,
> +				 node->size);
> +		return 0;
> +	}
> +
> +	xe_map_memset(xe, &bo->vmap, 0, initializer, size);
> +
> +	if (flags & XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST) {
> +		node = kzalloc_obj(*node);
> +		if (!node)
> +			return -ENOMEM;
> +
> +		err = drm_mm_insert_node_in_range(&mm_pool->base, node, SZ_4,
> +						  0, 0, 0, size, DRM_MM_INSERT_HIGHEST);
> +		if (err) {
> +			kfree(node);
> +			return err;
> +		}
> +		xe_map_wr(xe, &mm_pool->bo->vmap, node->start, u32, MI_BATCH_BUFFER_END);
> +		mm_pool->resv_alloc = node;
> +	}

I thought my suggestion was let the caller own setting of the memory contents?

Also I corrected myself that you don't actually need node here either [1]. Search for 'Isn’t this what you were'...


[1] https://patchwork.freedesktop.org/patch/713119/?series=163588&rev=1#comment_1315911

> +	return 0;
> +}
> +
> +/**
> + * xe_mem_pool_init() - Initialize a DRM MM pool.
> + * @tile: the &xe_tile where allocate.
> + * @size: number of bytes to allocate.
> + * @flags: flags to use for BO creation.
> + *
> + * Initializes a DRM MM manager for managing memory allocations on a specific
> + * XE tile. The function allocates a buffer object to back the memory region
> + * managed by the DRM MM manager.
> + *
> + * Return: a pointer to the &xe_mem_pool_manager, or an error pointer on failure.
> + */
> +struct xe_mem_pool_manager *xe_mem_pool_init(struct xe_tile *tile, u32 size, int flags)
> +{
> +	struct xe_device *xe = tile_to_xe(tile);
> +	struct xe_mem_pool_manager *pool_manager;
> +	struct xe_bo *bo;
> +	int ret;
> +
> +	pool_manager = drmm_kzalloc(&xe->drm, sizeof(*pool_manager), GFP_KERNEL);
> +	if (!pool_manager)
> +		return ERR_PTR(-ENOMEM);
> +
> +	bo = xe_managed_bo_create_pin_map(xe, tile, size,
> +					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> +					  XE_BO_FLAG_GGTT |
> +					  XE_BO_FLAG_GGTT_INVALIDATE |
> +					  XE_BO_FLAG_PINNED_NORESTORE);
> +	if (IS_ERR(bo)) {
> +		drm_err(&xe->drm, "Failed to prepare %uKiB BO for DRM MM manager (%pe)\n",
> +			size / SZ_1K, bo);
> +		return ERR_CAST(bo);
> +	}
> +	pool_manager->bo = bo;
> +	pool_manager->size = size;
> +
> +	if (bo->vmap.is_iomem) {
> +		pool_manager->cpu_addr = kvzalloc(size, GFP_KERNEL);
> +		if (!pool_manager->cpu_addr)
> +			return ERR_PTR(-ENOMEM);
> +	} else {
> +		pool_manager->cpu_addr = bo->vmap.vaddr;
> +	}
> +
> +	drm_mm_init(&pool_manager->base, 0, size);
> +	ret = drmm_add_action_or_reset(&xe->drm, xe_mem_pool_fini, pool_manager);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
> +	ret = xe_mem_pool_init_flags(pool_manager, size, flags);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
> +	return pool_manager;
> +}
> +
> +/**
> + * xe_mem_pool_shadow_init() - Initialize the shadow BO for a DRM MM manager.
> + * @pool_manager: the DRM MM manager to initialize the shadow BO for.
> + * @flags: flags to use for BO creation.
> + *
> + * Initializes the shadow buffer object for the specified DRM MM manager. The
> + * shadow BO is used for atomic command updates and is created with the same
> + * size and properties as the primary BO.
> + *
> + * Return: 0 on success, or a negative error code on failure.
> + */
> +int xe_mem_pool_shadow_init(struct xe_mem_pool_manager *pool_manager, int flags)

I'm not so sure about two init functions... Was that Michal's
suggestion? I can't say I agree... One init call with shadow flag makes
more sense to me. 

> +{
> +	struct xe_tile *tile = pool_manager->bo->tile;
> +	struct xe_device *xe = tile_to_xe(tile);
> +	struct xe_bo *shadow;
> +	int ret;
> +
> +	xe_assert(xe, !pool_manager->shadow);
> +
> +	ret = drmm_mutex_init(&xe->drm, &pool_manager->swap_guard);
> +	if (ret)
> +		return ret;
> +
> +	if (IS_ENABLED(CONFIG_PROVE_LOCKING)) {
> +		fs_reclaim_acquire(GFP_KERNEL);
> +		might_lock(&pool_manager->swap_guard);
> +		fs_reclaim_release(GFP_KERNEL);
> +	}
> +	shadow = xe_managed_bo_create_pin_map(xe, tile, pool_manager->size,
> +					      XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> +					      XE_BO_FLAG_GGTT |
> +					      XE_BO_FLAG_GGTT_INVALIDATE |
> +					      XE_BO_FLAG_PINNED_NORESTORE);
> +	if (IS_ERR(shadow))
> +		return PTR_ERR(shadow);
> +
> +	pool_manager->shadow = shadow;
> +
> +	ret = xe_mem_pool_init_flags(pool_manager, pool_manager->size,
> +				     flags | XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_mem_pool_swap_shadow_locked() - Swap the primary BO with the shadow BO.
> + * @pool_manager: the DRM MM manager containing the primary and shadow BOs.
> + *
> + * Swaps the primary buffer object with the shadow buffer object in the DRM MM
> + * manager. This function must be called with the swap_guard mutex held to
> + * ensure synchronization with any concurrent operations that may be accessing
> + * the BOs.
> + *
> + * Return: None.
> + */
> +void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool_manager *pool_manager)
> +{
> +	struct xe_tile *tile = pool_manager->bo->tile;
> +
> +	xe_tile_assert(tile, pool_manager->shadow);
> +	lockdep_assert_held(&pool_manager->swap_guard);
> +
> +	swap(pool_manager->bo, pool_manager->shadow);
> +	if (!pool_manager->bo->vmap.is_iomem)
> +		pool_manager->cpu_addr = pool_manager->bo->vmap.vaddr;
> +}
> +
> +/**
> + * xe_mem_pool_sync_shadow_locked() - Synchronize the shadow BO with the primary BO.
> + * @pool_manager: the DRM MM manager containing the primary and shadow BOs.
> + * @node: the DRM MM node representing the region to synchronize.
> + *
> + * Copies the contents of the specified region from the primary buffer object to
> + * the shadow buffer object in the DRM MM manager.
> + * Swap_guard must be held to ensure synchronization with any concurrent swap
> + * operations.
> + *
> + * Return: None.
> + */
> +void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_manager *pool_manager,
> +				    struct drm_mm_node *node)

s/struct drm_mm_node/struct xe_mem_pool_bb as the argument?

> +{
> +	struct xe_tile *tile = pool_manager->bo->tile;
> +	struct xe_device *xe = tile_to_xe(tile);
> +
> +	xe_tile_assert(tile, pool_manager->shadow);
> +	lockdep_assert_held(&pool_manager->swap_guard);
> +
> +	xe_map_memcpy_to(xe, &pool_manager->shadow->vmap,
> +			 node->start,
> +			 pool_manager->cpu_addr + node->start,
> +			 node->size);
> +}
> +
> +/**
> + * xe_mem_pool_insert_node() - Insert a node into the DRM MM manager.
> + * @pool_manager: the DRM MM manager to insert the node into.
> + * @node: the DRM MM node to insert.
> + * @size: the size of the node to insert.
> + *
> + * Inserts a node into the DRM MM manager and clears the corresponding memory region
> + * in both the primary and shadow buffer objects.
> + *
> + * Return: 0 on success, or a negative error code on failure.
> + */
> +int xe_mem_pool_insert_node(struct xe_mem_pool_manager *pool_manager,
> +			    struct drm_mm_node *node, u32 size)

s/struct drm_mm_node/struct xe_mem_pool_bb as the argument?

> +{
> +	struct drm_mm *mm = &pool_manager->base;
> +	int ret;
> +
> +	ret = drm_mm_insert_node(mm, node, size);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_mem_pool_remove_node() - Remove a node from the DRM MM manager.
> + * @node: the DRM MM node to remove.
> + *
> + * Return: None.
> + */
> +void xe_mem_pool_remove_node(struct drm_mm_node *node)
> +{

s/struct drm_mm_node/struct xe_mem_pool_bb as the argument?

> +	return drm_mm_remove_node(node);
> +}
> +
> +/**
> + * xe_mem_pool_manager_gpu_addr() - Retrieve GPU address of BO within a memory manager.
> + * @pool_manager: The DRM MM memory manager.
> + *
> + * Returns: GGTT address of the back storage BO
> + */
> +u64 xe_mem_pool_manager_gpu_addr(struct xe_mem_pool_manager *pool_manager)
> +{
> +	return xe_bo_ggtt_addr(pool_manager->bo);
> +}
> +
> +/**
> + * xe_mem_pool_manager_cpu_addr() - Retrieve CPU address of BO within a memory manager.
> + * @pool_manager: The DRM MM memory manager.
> + *
> + * Returns: CPU virtual address of BO.
> + */
> +void *xe_mem_pool_manager_cpu_addr(struct xe_mem_pool_manager *pool_manager)
> +{
> +	return pool_manager->cpu_addr;
> +}
> +
> +/**
> + * xe_mem_pool_bo_swap_guard() - Retrieve the mutex used to guard swap operations
> + * on a memory manager.
> + * @pool_manager: The DRM MM memory manager.
> + *
> + * Returns: Swap guard mutex.
> + */
> +struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool_manager *pool_manager)
> +{
> +	return &pool_manager->swap_guard;
> +}
> +
> +/**
> + * xe_mem_pool_dump() - Dump the state of the DRM MM manager for debugging.
> + * @pool_manager: The DRM MM manager to dump.
> + * @p: The DRM printer to use for output.
> + *
> + * Returns: None.
> + */
> +void xe_mem_pool_dump(struct xe_mem_pool_manager *pool_manager, struct drm_printer *p)
> +{
> +	drm_mm_print(&pool_manager->base, p);
> +}
> +
> +static inline struct xe_mem_pool_manager *to_xe_mem_pool_manager(struct drm_mm *mng)
> +{
> +	return container_of(mng, struct xe_mem_pool_manager, base);
> +}
> +
> +/**
> + * xe_mem_pool_bo_flush_write() - Copy the data from the sub-allocation
> + * to the GPU memory.
> + * @node: the &drm_mm_node to flush
> + */
> +void xe_mem_pool_bo_flush_write(struct drm_mm_node *node)

s/struct drm_mm_node/struct xe_mem_pool_bb as the argument?

> +{
> +	struct xe_mem_pool_manager *pool_manager = to_xe_mem_pool_manager(node->mm);
> +	struct xe_device *xe = tile_to_xe(pool_manager->bo->tile);
> +
> +	if (!pool_manager->bo->vmap.is_iomem)
> +		return;
> +
> +	xe_map_memcpy_to(xe, &pool_manager->bo->vmap, node->start,
> +			 pool_manager->cpu_addr + node->start,
> +			 node->size);
> +}
> +
> +/**
> + * xe_mem_pool_bo_sync_read() - Copy the data from GPU memory to the
> + * sub-allocation.
> + * @node: the &&drm_mm_node to sync
> + */
> +void xe_mem_pool_bo_sync_read(struct drm_mm_node *node)
> +{

s/struct drm_mm_node/struct xe_mem_pool_bb as the argument?

Matt

> +	struct xe_mem_pool_manager *pool_manager = to_xe_mem_pool_manager(node->mm);
> +	struct xe_device *xe = tile_to_xe(pool_manager->bo->tile);
> +
> +	if (!pool_manager->bo->vmap.is_iomem)
> +		return;
> +
> +	xe_map_memcpy_from(xe, pool_manager->cpu_addr + node->start,
> +			   &pool_manager->bo->vmap, node->start, node->size);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_mem_pool.h b/drivers/gpu/drm/xe/xe_mem_pool.h
> new file mode 100644
> index 000000000000..f9c5d1e56dd9
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_mem_pool.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +#ifndef _XE_MEM_POOL_H_
> +#define _XE_MEM_POOL_H_
> +
> +#include <linux/sizes.h>
> +#include <linux/types.h>
> +
> +#include "drm/drm_mm.h"
> +#include "xe_mem_pool_types.h"
> +
> +struct drm_printer;
> +struct xe_mem_pool_manager;
> +struct xe_tile;
> +
> +struct xe_mem_pool_manager *xe_mem_pool_init(struct xe_tile *tile, u32 size, int flags);
> +int xe_mem_pool_shadow_init(struct xe_mem_pool_manager *drm_mm_manager, int flags);
> +void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool_manager *drm_mm_manager);
> +void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_manager *drm_mm_manager,
> +				    struct drm_mm_node *node);
> +int xe_mem_pool_insert_node(struct xe_mem_pool_manager *drm_mm_manager,
> +			    struct drm_mm_node *node, u32 size);
> +void xe_mem_pool_remove_node(struct drm_mm_node *node);
> +u64 xe_mem_pool_manager_gpu_addr(struct xe_mem_pool_manager *drm_mm_manager);
> +void *xe_mem_pool_manager_cpu_addr(struct xe_mem_pool_manager *mm_manager);
> +struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool_manager *drm_mm_manager);
> +void xe_mem_pool_dump(struct xe_mem_pool_manager *mm_manager, struct drm_printer *p);
> +void xe_mem_pool_bo_flush_write(struct drm_mm_node *node);
> +void xe_mem_pool_bo_sync_read(struct drm_mm_node *node);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_mem_pool_types.h b/drivers/gpu/drm/xe/xe_mem_pool_types.h
> new file mode 100644
> index 000000000000..bae7706aa8d2
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_mem_pool_types.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_MEM_POOL_TYPES_H_
> +#define _XE_MEM_POOL_TYPES_H_
> +
> +#include <drm/drm_mm.h>
> +
> +struct xe_mem_pool_manager;
> +
> +#define XE_MEM_POOL_BO_FLAG_INIT_ZERO_FILL			BIT(0)
> +#define XE_MEM_POOL_BO_FLAG_INIT_CMD_NOOP			BIT(1)
> +#define XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST		BIT(2)
> +#define XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY			BIT(3)
> +
> +/**
> + * struct xe_mem_pool_bb - Sub allocated batch buffer from mem pool.
> + */
> +struct xe_mem_pool_bb {
> +	/** @node: Range node for this batch buffer. */
> +	struct drm_mm_node node;
> +	/** @cs: Command stream for this batch buffer. */
> +	u32 *cs;
> +	/** @len: Length of the CS in dwords. */
> +	u32 len;
> +};
> +
> +#endif
> -- 
> 2.43.0
> 

Re: [PATCH v3 1/3] drm/xe/mm: add XE MEM POOL manager with shadow support

[Thomas Hellström]

On Wed, 2026-04-01 at 16:15 +0000, Satyanarayana K V P wrote:
> Add a xe_mem_pool manager to allocate sub-ranges from a BO-backed
> pool
> using drm_mm.
> 
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> ---
> V2 -> V3:
> - Renamed xe_mm_suballoc to xe_mem_pool_manager.
> - Splitted xe_mm_suballoc_manager_init() into xe_mem_pool_init() and
> xe_mem_pool_shadow_init() (Michal)
> - Made xe_mm_sa_manager structure private. (Matt)
> - Introduced init flags to initialize allocated pools.
> 
> V1 -> V2:
> - Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
> - Removed memset during manager init and insert (Matt)

Hey, Run a kreview using review-prompts with Claude:

> diff --git a/drivers/gpu/drm/xe/xe_mem_pool.c
b/drivers/gpu/drm/xe/xe_mem_pool.c
> new file mode 100644

[ ... ]

> +static void xe_mem_pool_fini(struct drm_device *drm, void *arg)
> +{
> +	struct xe_mem_pool_manager *pool_manager = arg;
> +
> +	drm_mm_takedown(&pool_manager->base);
> +
> +	if (pool_manager->resv_alloc) {
> +		drm_mm_remove_node(pool_manager->resv_alloc);
> +		kfree(pool_manager->resv_alloc);
> +	}

The node removal happens after drm_mm_takedown(), but drm_mm_takedown()
requires the allocator to be clean before it is called.

When XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST is used,
xe_mem_pool_init()
calls xe_mem_pool_init_flags() which inserts a reserved node and stores
it
in pool_manager->resv_alloc.  On device teardown, xe_mem_pool_fini() is
invoked with that node still allocated inside the drm_mm.

drm_mm_takedown() in drivers/gpu/drm/drm_mm.c does:

    void drm_mm_takedown(struct drm_mm *mm)
    {
        if (WARN(!drm_mm_clean(mm),
                 "Memory manager not clean during takedown.\n"))
            show_leaks(mm);
    }

drm_mm_clean() returns list_empty(drm_mm_nodes(mm)), which is false
when
resv_alloc is still inserted.  So the WARN fires on every teardown of a
pool created with BB_END_HIGHEST.

Shouldn't drm_mm_remove_node(pool_manager->resv_alloc) be called before
drm_mm_takedown(), so the allocator is clean at the point of takedown?

[ ... ]

> +/**
> + * xe_mem_pool_remove_node() - Remove a node from the DRM MM
manager.
> + * @node: the DRM MM node to remove.
> + *
> + * Return: None.
> + */
> +void xe_mem_pool_remove_node(struct drm_mm_node *node)
> +{
> +	return drm_mm_remove_node(node);
> +}

This isn't a bug, but returning a void expression from a void function
is unusual - the return statement here implies a return value where
there
is none.  The body could just be drm_mm_remove_node(node) without the
return.

Re: [PATCH v3 1/3] drm/xe/mm: add XE MEM POOL manager with shadow support

[Michal Wajdeczko]

nit: title

	drm/xe: Add memory pool with shadow support

On 4/1/2026 6:15 PM, Satyanarayana K V P wrote:
> Add a xe_mem_pool manager to allocate sub-ranges from a BO-backed pool
> using drm_mm.
> 
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> ---
> V2 -> V3:
> - Renamed xe_mm_suballoc to xe_mem_pool_manager.
> - Splitted xe_mm_suballoc_manager_init() into xe_mem_pool_init() and
> xe_mem_pool_shadow_init() (Michal)

well, my point was that we could have two separate components:

 1. xe_pool - that provides simple sub-allocations, similar to xe_sa but without use of fences
 2. xe_shadow_pool - that is built on top of xe_pool and provides "shadow bo" feature (as needed by CCS)

but that all of this could wait as any refactoring (and reuse in xe_guc_buf) can be later, after fixing hot CCS issue

> - Made xe_mm_sa_manager structure private. (Matt)
> - Introduced init flags to initialize allocated pools.
> 
> V1 -> V2:
> - Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
> - Removed memset during manager init and insert (Matt)
> ---
>  drivers/gpu/drm/xe/Makefile            |   1 +
>  drivers/gpu/drm/xe/xe_mem_pool.c       | 379 +++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_mem_pool.h       |  33 +++
>  drivers/gpu/drm/xe/xe_mem_pool_types.h |  30 ++
>  4 files changed, 443 insertions(+)
>  create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.c
>  create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.h
>  create mode 100644 drivers/gpu/drm/xe/xe_mem_pool_types.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 9dacb0579a7d..8e31b14239ec 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -88,6 +88,7 @@ xe-y += xe_bb.o \
>  	xe_irq.o \
>  	xe_late_bind_fw.o \
>  	xe_lrc.o \
> +	xe_mem_pool.o \
>  	xe_migrate.o \
>  	xe_mmio.o \
>  	xe_mmio_gem.o \
> diff --git a/drivers/gpu/drm/xe/xe_mem_pool.c b/drivers/gpu/drm/xe/xe_mem_pool.c
> new file mode 100644
> index 000000000000..335a70876bf1
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_mem_pool.c
> @@ -0,0 +1,379 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <linux/kernel.h>
> +
> +#include <drm/drm_managed.h>
> +
> +#include "instructions/xe_mi_commands.h"
> +#include "xe_bo.h"
> +#include "xe_device_types.h"
> +#include "xe_map.h"
> +#include "xe_mem_pool.h"
> +#include "xe_mem_pool_types.h"
> +
> +/**
> + * struct xe_mem_pool_manager - Memory Suballoc manager.

we can drop _manager suffix - there is just a "pool" instance we care of

> + */
> +

extra line

> +struct xe_mem_pool_manager {
> +	/** @base: Range allocator over [0, @size) in bytes */
> +	struct drm_mm base;
> +	/** @bo: Active pool BO (GGTT-pinned, CPU-mapped). */
> +	struct xe_bo *bo;
> +	/** @shadow: Shadow BO for atomic command updates. */
> +	struct xe_bo *shadow;

hmm, this "atomic command updates" seems to be a quite big extension of
the original goal: "allocate sub-ranges from a BO-backed pool"

> +	/** @swap_guard: Timeline guard updating @bo and @shadow */
> +	struct mutex swap_guard;
> +	/** @cpu_addr: CPU virtual address of the active BO. */
> +	void *cpu_addr;
> +	/** @resv_alloc: Reserved allocation. */
> +	struct drm_mm_node *resv_alloc;

do we need this to be dynamically allocated?

> +	/** @size: Total size of the managed address space. */
> +	u64 size;

do we need this field? there is xe_bo_size() we can use

> +};
> +
> +static void xe_mem_pool_fini(struct drm_device *drm, void *arg)

no need to use xe_ prefix in static functions, this could be:

	void fini_pool_action(...

> +{
> +	struct xe_mem_pool_manager *pool_manager = arg;
> +
> +	drm_mm_takedown(&pool_manager->base);

this should be a last step (and CI already complained)

> +
> +	if (pool_manager->resv_alloc) {
> +		drm_mm_remove_node(pool_manager->resv_alloc);
> +		kfree(pool_manager->resv_alloc);
> +	}
> +
> +	if (pool_manager->bo->vmap.is_iomem)
> +		kvfree(pool_manager->cpu_addr);
> +
> +	pool_manager->bo = NULL;
> +	pool_manager->shadow = NULL;

not sure if this is needed, pool was also allocated as managed object
and it will be released in the very next drmm action

> +}
> +
> +static int xe_mem_pool_init_flags(struct xe_mem_pool_manager *mm_pool, u32 size, int flags)
> +{
> +	struct xe_bo *bo = mm_pool->bo;
> +	struct drm_mm_node *node;
> +	struct xe_device *xe;
> +	u32 initializer;
> +	int err;
> +
> +	if (!flags)
> +		return 0;
> +
> +	if (flags & XE_MEM_POOL_BO_FLAG_INIT_ZERO_FILL)
> +		initializer = 0;
> +	else if (flags & XE_MEM_POOL_BO_FLAG_INIT_CMD_NOOP ||
> +		 flags & XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST)
> +		initializer = MI_NOOP;

this seems to be CCS usecase specific
not sure if this should be part of the generic pool
besides, isn't MI_NOOP == 0x0 anyway?

> +	else
> +		return -EINVAL;

it would be our programming fault, so assert should be sufficient

> +
> +	xe = tile_to_xe(bo->tile);
> +	if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY) {

this flag is N/A to plain pool init
and there is no clear separation between supported features (plain vs shadow)

you must decide whether this is generic vs CCS-specific component

> +		bo = mm_pool->shadow;
> +		xe_map_memset(xe, &bo->vmap, 0, initializer, size);
> +
> +		node = mm_pool->resv_alloc;
> +		xe_map_memcpy_to(xe, &mm_pool->shadow->vmap,
> +				 node->start,
> +				 mm_pool->cpu_addr + node->start,
> +				 node->size);
> +		return 0;
> +	}
> +
> +	xe_map_memset(xe, &bo->vmap, 0, initializer, size);
> +
> +	if (flags & XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST) {
> +		node = kzalloc_obj(*node);
> +		if (!node)
> +			return -ENOMEM;
> +
> +		err = drm_mm_insert_node_in_range(&mm_pool->base, node, SZ_4,
> +						  0, 0, 0, size, DRM_MM_INSERT_HIGHEST);

this SZ_4 seems to be very specific to the CCS usecase,
and IMO it does not fit as part of the generic "sub-ranges from a BO-backed pool"

> +		if (err) {
> +			kfree(node);
> +			return err;
> +		}
> +		xe_map_wr(xe, &mm_pool->bo->vmap, node->start, u32, MI_BATCH_BUFFER_END);
> +		mm_pool->resv_alloc = node;
> +	}
> +	return 0;
> +}
> +
> +/**
> + * xe_mem_pool_init() - Initialize a DRM MM pool.

... Initialize memory pool

> + * @tile: the &xe_tile where allocate.
> + * @size: number of bytes to allocate.
> + * @flags: flags to use for BO creation.
> + *
> + * Initializes a DRM MM manager for managing memory allocations on a specific
> + * XE tile. The function allocates a buffer object to back the memory region
> + * managed by the DRM MM manager.
> + *
> + * Return: a pointer to the &xe_mem_pool_manager, or an error pointer on failure.
> + */

maybe we should have two functions:

	int xe_mem_pool_init(struct xe_mem_pool *p, ...)
	struct xe_mem_pool *xe_mem_pool_create(...)


> +struct xe_mem_pool_manager *xe_mem_pool_init(struct xe_tile *tile, u32 size, int flags)
> +{
> +	struct xe_device *xe = tile_to_xe(tile);
> +	struct xe_mem_pool_manager *pool_manager;
> +	struct xe_bo *bo;
> +	int ret;
> +
> +	pool_manager = drmm_kzalloc(&xe->drm, sizeof(*pool_manager), GFP_KERNEL);
> +	if (!pool_manager)
> +		return ERR_PTR(-ENOMEM);
> +
> +	bo = xe_managed_bo_create_pin_map(xe, tile, size,
> +					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> +					  XE_BO_FLAG_GGTT |
> +					  XE_BO_FLAG_GGTT_INVALIDATE |
> +					  XE_BO_FLAG_PINNED_NORESTORE);
> +	if (IS_ERR(bo)) {
> +		drm_err(&xe->drm, "Failed to prepare %uKiB BO for DRM MM manager (%pe)\n",

we have a tile here, so:

	xe_tile_err(tile, ...

and this is not about "DRM MM manager"

> +			size / SZ_1K, bo);
> +		return ERR_CAST(bo);
> +	}
> +	pool_manager->bo = bo;
> +	pool_manager->size = size;
> +
> +	if (bo->vmap.is_iomem) {
> +		pool_manager->cpu_addr = kvzalloc(size, GFP_KERNEL);
> +		if (!pool_manager->cpu_addr)
> +			return ERR_PTR(-ENOMEM);
> +	} else {
> +		pool_manager->cpu_addr = bo->vmap.vaddr;
> +	}
> +
> +	drm_mm_init(&pool_manager->base, 0, size);
> +	ret = drmm_add_action_or_reset(&xe->drm, xe_mem_pool_fini, pool_manager);
> +	if (ret)
> +		return ERR_PTR(ret);
> +
> +	ret = xe_mem_pool_init_flags(pool_manager, size, flags);

I'm not sure this helper really helps here...

> +	if (ret)
> +		return ERR_PTR(ret);
> +
> +	return pool_manager;
> +}
> +
> +/**
> + * xe_mem_pool_shadow_init() - Initialize the shadow BO for a DRM MM manager.

hmm, since you don't have a separate

	struct xe_mem_pool_shadow

then this init() function is little confusing
note that xe_mem_pool_manager is already polluted with 'shadow' logic

> + * @pool_manager: the DRM MM manager to initialize the shadow BO for.
> + * @flags: flags to use for BO creation.
> + *
> + * Initializes the shadow buffer object for the specified DRM MM manager. The

hmm, DRM MM is just our implementation detail
what we init here is "sub-range allocator"
please revisit all comments/descriptions

> + * shadow BO is used for atomic command updates and is created with the same
> + * size and properties as the primary BO.
> + *
> + * Return: 0 on success, or a negative error code on failure.
> + */
> +int xe_mem_pool_shadow_init(struct xe_mem_pool_manager *pool_manager, int flags)
> +{
> +	struct xe_tile *tile = pool_manager->bo->tile;
> +	struct xe_device *xe = tile_to_xe(tile);
> +	struct xe_bo *shadow;
> +	int ret;
> +
> +	xe_assert(xe, !pool_manager->shadow);
> +
> +	ret = drmm_mutex_init(&xe->drm, &pool_manager->swap_guard);
> +	if (ret)
> +		return ret;
> +
> +	if (IS_ENABLED(CONFIG_PROVE_LOCKING)) {
> +		fs_reclaim_acquire(GFP_KERNEL);
> +		might_lock(&pool_manager->swap_guard);
> +		fs_reclaim_release(GFP_KERNEL);
> +	}
> +	shadow = xe_managed_bo_create_pin_map(xe, tile, pool_manager->size,
> +					      XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> +					      XE_BO_FLAG_GGTT |
> +					      XE_BO_FLAG_GGTT_INVALIDATE |
> +					      XE_BO_FLAG_PINNED_NORESTORE);

nit: btw, maybe for the 'shadow' we don't need a separate BO
but just allocate primary BO twice big? and the just adjust offset?

> +	if (IS_ERR(shadow))
> +		return PTR_ERR(shadow);
> +
> +	pool_manager->shadow = shadow;
> +
> +	ret = xe_mem_pool_init_flags(pool_manager, pool_manager->size,
> +				     flags | XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_mem_pool_swap_shadow_locked() - Swap the primary BO with the shadow BO.
> + * @pool_manager: the DRM MM manager containing the primary and shadow BOs.
> + *
> + * Swaps the primary buffer object with the shadow buffer object in the DRM MM
> + * manager. This function must be called with the swap_guard mutex held to
> + * ensure synchronization with any concurrent operations that may be accessing
> + * the BOs.
> + *
> + * Return: None.
> + */
> +void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool_manager *pool_manager)
> +{
> +	struct xe_tile *tile = pool_manager->bo->tile;
> +
> +	xe_tile_assert(tile, pool_manager->shadow);
> +	lockdep_assert_held(&pool_manager->swap_guard);
> +
> +	swap(pool_manager->bo, pool_manager->shadow);
> +	if (!pool_manager->bo->vmap.is_iomem)
> +		pool_manager->cpu_addr = pool_manager->bo->vmap.vaddr;
> +}
> +
> +/**
> + * xe_mem_pool_sync_shadow_locked() - Synchronize the shadow BO with the primary BO.
> + * @pool_manager: the DRM MM manager containing the primary and shadow BOs.
> + * @node: the DRM MM node representing the region to synchronize.
> + *
> + * Copies the contents of the specified region from the primary buffer object to
> + * the shadow buffer object in the DRM MM manager.
> + * Swap_guard must be held to ensure synchronization with any concurrent swap
> + * operations.
> + *
> + * Return: None.
> + */
> +void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_manager *pool_manager,
> +				    struct drm_mm_node *node)

we shouldn't expose/use pure drm_mm_node in our API

> +{
> +	struct xe_tile *tile = pool_manager->bo->tile;
> +	struct xe_device *xe = tile_to_xe(tile);
> +
> +	xe_tile_assert(tile, pool_manager->shadow);
> +	lockdep_assert_held(&pool_manager->swap_guard);
> +
> +	xe_map_memcpy_to(xe, &pool_manager->shadow->vmap,
> +			 node->start,
> +			 pool_manager->cpu_addr + node->start,
> +			 node->size);
> +}
> +
> +/**
> + * xe_mem_pool_insert_node() - Insert a node into the DRM MM manager.
> + * @pool_manager: the DRM MM manager to insert the node into.
> + * @node: the DRM MM node to insert.
> + * @size: the size of the node to insert.
> + *
> + * Inserts a node into the DRM MM manager and clears the corresponding memory region
> + * in both the primary and shadow buffer objects.
> + *
> + * Return: 0 on success, or a negative error code on failure.
> + */
> +int xe_mem_pool_insert_node(struct xe_mem_pool_manager *pool_manager,
> +			    struct drm_mm_node *node, u32 size)
> +{
> +	struct drm_mm *mm = &pool_manager->base;
> +	int ret;
> +
> +	ret = drm_mm_insert_node(mm, node, size);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_mem_pool_remove_node() - Remove a node from the DRM MM manager.
> + * @node: the DRM MM node to remove.
> + *
> + * Return: None.
> + */
> +void xe_mem_pool_remove_node(struct drm_mm_node *node)
> +{
> +	return drm_mm_remove_node(node);
> +}
> +
> +/**
> + * xe_mem_pool_manager_gpu_addr() - Retrieve GPU address of BO within a memory manager.
> + * @pool_manager: The DRM MM memory manager.
> + *
> + * Returns: GGTT address of the back storage BO
> + */
> +u64 xe_mem_pool_manager_gpu_addr(struct xe_mem_pool_manager *pool_manager)
> +{
> +	return xe_bo_ggtt_addr(pool_manager->bo);
> +}
> +
> +/**
> + * xe_mem_pool_manager_cpu_addr() - Retrieve CPU address of BO within a memory manager.
> + * @pool_manager: The DRM MM memory manager.
> + *
> + * Returns: CPU virtual address of BO.
> + */
> +void *xe_mem_pool_manager_cpu_addr(struct xe_mem_pool_manager *pool_manager)

shouldn't this be per node?

> +{
> +	return pool_manager->cpu_addr;
> +}
> +
> +/**
> + * xe_mem_pool_bo_swap_guard() - Retrieve the mutex used to guard swap operations
> + * on a memory manager.
> + * @pool_manager: The DRM MM memory manager.
> + *
> + * Returns: Swap guard mutex.
> + */
> +struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool_manager *pool_manager)
> +{
> +	return &pool_manager->swap_guard;
> +}
> +
> +/**
> + * xe_mem_pool_dump() - Dump the state of the DRM MM manager for debugging.
> + * @pool_manager: The DRM MM manager to dump.
> + * @p: The DRM printer to use for output.
> + *
> + * Returns: None.
> + */
> +void xe_mem_pool_dump(struct xe_mem_pool_manager *pool_manager, struct drm_printer *p)
> +{
> +	drm_mm_print(&pool_manager->base, p);

maybe also print info about the BO and shadow BO (like their GGTT)

> +}
> +
> +static inline struct xe_mem_pool_manager *to_xe_mem_pool_manager(struct drm_mm *mng)

please, no "inline" in .c

> +{
> +	return container_of(mng, struct xe_mem_pool_manager, base);
> +}
> +
> +/**
> + * xe_mem_pool_bo_flush_write() - Copy the data from the sub-allocation
> + * to the GPU memory.
> + * @node: the &drm_mm_node to flush
> + */
> +void xe_mem_pool_bo_flush_write(struct drm_mm_node *node)
> +{
> +	struct xe_mem_pool_manager *pool_manager = to_xe_mem_pool_manager(node->mm);
> +	struct xe_device *xe = tile_to_xe(pool_manager->bo->tile);
> +
> +	if (!pool_manager->bo->vmap.is_iomem)
> +		return;
> +
> +	xe_map_memcpy_to(xe, &pool_manager->bo->vmap, node->start,
> +			 pool_manager->cpu_addr + node->start,
> +			 node->size);
> +}
> +
> +/**
> + * xe_mem_pool_bo_sync_read() - Copy the data from GPU memory to the
> + * sub-allocation.
> + * @node: the &&drm_mm_node to sync
> + */
> +void xe_mem_pool_bo_sync_read(struct drm_mm_node *node)
> +{
> +	struct xe_mem_pool_manager *pool_manager = to_xe_mem_pool_manager(node->mm);
> +	struct xe_device *xe = tile_to_xe(pool_manager->bo->tile);
> +
> +	if (!pool_manager->bo->vmap.is_iomem)
> +		return;
> +
> +	xe_map_memcpy_from(xe, pool_manager->cpu_addr + node->start,
> +			   &pool_manager->bo->vmap, node->start, node->size);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_mem_pool.h b/drivers/gpu/drm/xe/xe_mem_pool.h
> new file mode 100644
> index 000000000000..f9c5d1e56dd9
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_mem_pool.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +#ifndef _XE_MEM_POOL_H_
> +#define _XE_MEM_POOL_H_
> +
> +#include <linux/sizes.h>
> +#include <linux/types.h>
> +
> +#include "drm/drm_mm.h"

use <>

> +#include "xe_mem_pool_types.h"
> +
> +struct drm_printer;
> +struct xe_mem_pool_manager;
> +struct xe_tile;
> +
> +struct xe_mem_pool_manager *xe_mem_pool_init(struct xe_tile *tile, u32 size, int flags);
> +int xe_mem_pool_shadow_init(struct xe_mem_pool_manager *drm_mm_manager, int flags);

"drm_mm_manager" - seems to be a wrong name, just "pool" ?

> +void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool_manager *drm_mm_manager);
> +void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_manager *drm_mm_manager,
> +				    struct drm_mm_node *node);
> +int xe_mem_pool_insert_node(struct xe_mem_pool_manager *drm_mm_manager,
> +			    struct drm_mm_node *node, u32 size);
> +void xe_mem_pool_remove_node(struct drm_mm_node *node);
> +u64 xe_mem_pool_manager_gpu_addr(struct xe_mem_pool_manager *drm_mm_manager);
> +void *xe_mem_pool_manager_cpu_addr(struct xe_mem_pool_manager *mm_manager);
> +struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool_manager *drm_mm_manager);
> +void xe_mem_pool_dump(struct xe_mem_pool_manager *mm_manager, struct drm_printer *p);
> +void xe_mem_pool_bo_flush_write(struct drm_mm_node *node);
> +void xe_mem_pool_bo_sync_read(struct drm_mm_node *node);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_mem_pool_types.h b/drivers/gpu/drm/xe/xe_mem_pool_types.h
> new file mode 100644
> index 000000000000..bae7706aa8d2
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_mem_pool_types.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_MEM_POOL_TYPES_H_
> +#define _XE_MEM_POOL_TYPES_H_
> +
> +#include <drm/drm_mm.h>
> +
> +struct xe_mem_pool_manager;

unused here?

> +
> +#define XE_MEM_POOL_BO_FLAG_INIT_ZERO_FILL			BIT(0)
> +#define XE_MEM_POOL_BO_FLAG_INIT_CMD_NOOP			BIT(1)
> +#define XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST		BIT(2)
> +#define XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY			BIT(3)
> +
> +/**
> + * struct xe_mem_pool_bb - Sub allocated batch buffer from mem pool.

hmm, suddenly from "sub-range allocations" we jumped to "batch-buffer" specifics

> + */
> +struct xe_mem_pool_bb {

maybe:
	xe_mem_pool_node ?

and it looks little strange that

  * we hide xe_mem_pool_manager details
  * then in functions accept drm_mm_node
  * but expose xe_mem_pool_bb here instead

> +	/** @node: Range node for this batch buffer. */
> +	struct drm_mm_node node;
> +	/** @cs: Command stream for this batch buffer. */
> +	u32 *cs;

maybe we should just have a function to return CPU pointer of the xe_pool_node?

	return pool->cpu_addr + node->start;

> +	/** @len: Length of the CS in dwords. */
> +	u32 len;

do we need this? there is:

	node->size

> +};
> +
> +#endif

[PATCH v3 2/3] drm/xe/mm: Add batch buffer allocation functions for xe_mem_pool manager

[Satyanarayana K V P]

New APIs xe_pool_bb_alloc(), xe_pool_bb_insert() and
xe_pool_bb_free() are created to manage allocations from the
xe_mem_pool manager.

Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Maarten Lankhorst <dev@lankhorst.se>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>

---
V2 -> V3:
- Renamed xe_mm_suballoc to xe_mem_pool.

V1 -> V2:
- Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
- Removed memset from xe_drm_mm_bb_insert() (Matt).
---
 drivers/gpu/drm/xe/xe_bb.c | 58 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_bb.h |  6 ++++
 2 files changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
index b896b6f6615c..26e2430c0dc1 100644
--- a/drivers/gpu/drm/xe/xe_bb.c
+++ b/drivers/gpu/drm/xe/xe_bb.c
@@ -10,6 +10,7 @@
 #include "xe_device_types.h"
 #include "xe_exec_queue_types.h"
 #include "xe_gt.h"
+#include "xe_mem_pool.h"
 #include "xe_sa.h"
 #include "xe_sched_job.h"
 #include "xe_vm_types.h"
@@ -172,3 +173,60 @@ void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence)
 	xe_sa_bo_free(bb->bo, fence);
 	kfree(bb);
 }
+
+/**
+ * xe_pool_bb_alloc() - Allocate a new batch buffer structure for drm_mm
+ *
+ * Allocates a new xe_pool_bb structure for use with xe_pool memory
+ * management.
+ *
+ * Returns: Batch buffer structure or an ERR_PTR(-ENOMEM).
+ */
+struct xe_mem_pool_bb *xe_pool_bb_alloc(void)
+{
+	struct xe_mem_pool_bb *bb = kzalloc_obj(*bb);
+
+	if (!bb)
+		return ERR_PTR(-ENOMEM);
+
+	return bb;
+}
+
+/**
+ * xe_pool_bb_insert() - Initialize a batch buffer and insert a hole
+ * @bb: Batch buffer structure to initialize
+ * @bb_pool: drm_mm manager to allocate from
+ * @dwords: Number of dwords to be allocated
+ *
+ * Initializes the batch buffer by allocating memory from the specified
+ * drm_mm manager.
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+int xe_pool_bb_insert(struct xe_mem_pool_bb *bb,
+		      struct xe_mem_pool_manager *bb_pool, u32 dwords)
+{
+	int err;
+
+	err = xe_mem_pool_insert_node(bb_pool, &bb->node, 4 * dwords);
+	if (err)
+		return err;
+
+	bb->cs = xe_mem_pool_manager_cpu_addr(bb_pool) + bb->node.start;
+	bb->len = 0;
+
+	return 0;
+}
+
+/**
+ * xe_pool_bb_free() - Free a batch buffer allocated with drm_mm
+ * @bb: Batch buffer structure to free
+ */
+void xe_pool_bb_free(struct xe_mem_pool_bb *bb)
+{
+	if (!bb)
+		return;
+
+	xe_mem_pool_remove_node(&bb->node);
+	kfree(bb);
+}
diff --git a/drivers/gpu/drm/xe/xe_bb.h b/drivers/gpu/drm/xe/xe_bb.h
index 231870b24c2f..638d8fc53f1a 100644
--- a/drivers/gpu/drm/xe/xe_bb.h
+++ b/drivers/gpu/drm/xe/xe_bb.h
@@ -12,6 +12,8 @@ struct dma_fence;
 
 struct xe_gt;
 struct xe_exec_queue;
+struct xe_mem_pool_bb;
+struct xe_mem_pool_manager;
 struct xe_sa_manager;
 struct xe_sched_job;
 
@@ -24,5 +26,9 @@ struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q,
 						struct xe_bb *bb, u64 batch_ofs,
 						u32 second_idx);
 void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence);
+struct xe_mem_pool_bb *xe_pool_bb_alloc(void);
+int xe_pool_bb_insert(struct xe_mem_pool_bb *bb,
+		      struct xe_mem_pool_manager *bb_pool, u32 dwords);
+void xe_pool_bb_free(struct xe_mem_pool_bb *bb);
 
 #endif
-- 
2.43.0

Re: [PATCH v3 2/3] drm/xe/mm: Add batch buffer allocation functions for xe_mem_pool manager

[Matthew Brost]

On Wed, Apr 01, 2026 at 04:15:27PM +0000, Satyanarayana K V P wrote:
> New APIs xe_pool_bb_alloc(), xe_pool_bb_insert() and
> xe_pool_bb_free() are created to manage allocations from the
> xe_mem_pool manager.
> 

It seems like you could stick this entire thing in xe_mem_pool.c...

Matt

> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> ---
> V2 -> V3:
> - Renamed xe_mm_suballoc to xe_mem_pool.
> 
> V1 -> V2:
> - Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
> - Removed memset from xe_drm_mm_bb_insert() (Matt).
> ---
>  drivers/gpu/drm/xe/xe_bb.c | 58 ++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_bb.h |  6 ++++
>  2 files changed, 64 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
> index b896b6f6615c..26e2430c0dc1 100644
> --- a/drivers/gpu/drm/xe/xe_bb.c
> +++ b/drivers/gpu/drm/xe/xe_bb.c
> @@ -10,6 +10,7 @@
>  #include "xe_device_types.h"
>  #include "xe_exec_queue_types.h"
>  #include "xe_gt.h"
> +#include "xe_mem_pool.h"
>  #include "xe_sa.h"
>  #include "xe_sched_job.h"
>  #include "xe_vm_types.h"
> @@ -172,3 +173,60 @@ void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence)
>  	xe_sa_bo_free(bb->bo, fence);
>  	kfree(bb);
>  }
> +
> +/**
> + * xe_pool_bb_alloc() - Allocate a new batch buffer structure for drm_mm
> + *
> + * Allocates a new xe_pool_bb structure for use with xe_pool memory
> + * management.
> + *
> + * Returns: Batch buffer structure or an ERR_PTR(-ENOMEM).
> + */
> +struct xe_mem_pool_bb *xe_pool_bb_alloc(void)
> +{
> +	struct xe_mem_pool_bb *bb = kzalloc_obj(*bb);
> +
> +	if (!bb)
> +		return ERR_PTR(-ENOMEM);
> +
> +	return bb;
> +}
> +
> +/**
> + * xe_pool_bb_insert() - Initialize a batch buffer and insert a hole
> + * @bb: Batch buffer structure to initialize
> + * @bb_pool: drm_mm manager to allocate from
> + * @dwords: Number of dwords to be allocated
> + *
> + * Initializes the batch buffer by allocating memory from the specified
> + * drm_mm manager.
> + *
> + * Return: 0 on success, negative error code on failure.
> + */
> +int xe_pool_bb_insert(struct xe_mem_pool_bb *bb,
> +		      struct xe_mem_pool_manager *bb_pool, u32 dwords)
> +{
> +	int err;
> +
> +	err = xe_mem_pool_insert_node(bb_pool, &bb->node, 4 * dwords);
> +	if (err)
> +		return err;
> +
> +	bb->cs = xe_mem_pool_manager_cpu_addr(bb_pool) + bb->node.start;
> +	bb->len = 0;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_pool_bb_free() - Free a batch buffer allocated with drm_mm
> + * @bb: Batch buffer structure to free
> + */
> +void xe_pool_bb_free(struct xe_mem_pool_bb *bb)
> +{
> +	if (!bb)
> +		return;
> +
> +	xe_mem_pool_remove_node(&bb->node);
> +	kfree(bb);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_bb.h b/drivers/gpu/drm/xe/xe_bb.h
> index 231870b24c2f..638d8fc53f1a 100644
> --- a/drivers/gpu/drm/xe/xe_bb.h
> +++ b/drivers/gpu/drm/xe/xe_bb.h
> @@ -12,6 +12,8 @@ struct dma_fence;
>  
>  struct xe_gt;
>  struct xe_exec_queue;
> +struct xe_mem_pool_bb;
> +struct xe_mem_pool_manager;
>  struct xe_sa_manager;
>  struct xe_sched_job;
>  
> @@ -24,5 +26,9 @@ struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q,
>  						struct xe_bb *bb, u64 batch_ofs,
>  						u32 second_idx);
>  void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence);
> +struct xe_mem_pool_bb *xe_pool_bb_alloc(void);
> +int xe_pool_bb_insert(struct xe_mem_pool_bb *bb,
> +		      struct xe_mem_pool_manager *bb_pool, u32 dwords);
> +void xe_pool_bb_free(struct xe_mem_pool_bb *bb);
>  
>  #endif
> -- 
> 2.43.0
> 

Re: [PATCH v3 2/3] drm/xe/mm: Add batch buffer allocation functions for xe_mem_pool manager

[Thomas Hellström]

On Wed, 2026-04-01 at 16:15 +0000, Satyanarayana K V P wrote:
> New APIs xe_pool_bb_alloc(), xe_pool_bb_insert() and
> xe_pool_bb_free() are created to manage allocations from the
> xe_mem_pool manager.
> 
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> ---
> V2 -> V3:
> - Renamed xe_mm_suballoc to xe_mem_pool.
> 
> V1 -> V2:
> - Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
> - Removed memset from xe_drm_mm_bb_insert() (Matt).
> ---

Claude's kreview:

> diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c

[ ... ]

> +/**
> + * xe_pool_bb_alloc() - Allocate a new batch buffer structure for
drm_mm
> + *
> + * Allocates a new xe_pool_bb structure for use with xe_pool memory
> + * management.
> + *
> + * Returns: Batch buffer structure or an ERR_PTR(-ENOMEM).
> + */
> +struct xe_mem_pool_bb *xe_pool_bb_alloc(void)

The kerneldoc says "Allocates a new xe_pool_bb structure" but the
returned type is struct xe_mem_pool_bb. The type xe_pool_bb does not
exist. Should the description read "xe_mem_pool_bb structure"?

> +/**
> + * xe_pool_bb_insert() - Initialize a batch buffer and insert a hole
> + * @bb: Batch buffer structure to initialize
> + * @bb_pool: drm_mm manager to allocate from
> + * @dwords: Number of dwords to be allocated
> + *
> + * Initializes the batch buffer by allocating memory from the
specified
> + * drm_mm manager.
> + *
> + * Return: 0 on success, negative error code on failure.
> + */
> +int xe_pool_bb_insert(struct xe_mem_pool_bb *bb,
> +		      struct xe_mem_pool_manager *bb_pool, u32 dwords)

The one-line description says "insert a hole", but in drm_mm
terminology a hole is available free space. This function calls
xe_mem_pool_insert_node() which calls drm_mm_insert_node() to
allocate a node from within a hole. Should the description say
"insert a node" instead of "insert a hole"?

Also, xe_mem_pool_insert_node() and xe_mem_pool_remove_node() have
no internal locking. The current caller in xe_migrate.c wraps both
xe_pool_bb_insert() and xe_pool_bb_free() inside:

    scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) {

but neither function documents this requirement. Would it make sense
to add a locking precondition to the kerneldoc of both functions,
similar to the _locked suffix convention used elsewhere in this file?

> +/**
> + * xe_pool_bb_free() - Free a batch buffer allocated with drm_mm
> + * @bb: Batch buffer structure to free
> + */
> +void xe_pool_bb_free(struct xe_mem_pool_bb *bb)

Same locking question as xe_pool_bb_insert() above --
drm_mm_remove_node()
requires external locking and the caller holds swap_guard, but this
is not documented here.

Also, this isn't a bug, but the new functions are named xe_pool_bb_*
while the type they operate on is struct xe_mem_pool_bb and the
manager type is struct xe_mem_pool_manager. The existing infrastructure
uses the xe_mem_pool_ prefix consistently. Would
xe_mem_pool_bb_alloc(),
xe_mem_pool_bb_insert(), and xe_mem_pool_bb_free() be more consistent
with the rest of the subsystem?

/Thomas

Re: [PATCH v3 2/3] drm/xe/mm: Add batch buffer allocation functions for xe_mem_pool manager

[Michal Wajdeczko]

On 4/1/2026 6:15 PM, Satyanarayana K V P wrote:
> New APIs xe_pool_bb_alloc(), xe_pool_bb_insert() and
> xe_pool_bb_free() are created to manage allocations from the
> xe_mem_pool manager.

if those are generic "allocations" from the pool, then don't call them BB

> 
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> ---
> V2 -> V3:
> - Renamed xe_mm_suballoc to xe_mem_pool.
> 
> V1 -> V2:
> - Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
> - Removed memset from xe_drm_mm_bb_insert() (Matt).
> ---
>  drivers/gpu/drm/xe/xe_bb.c | 58 ++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_bb.h |  6 ++++
>  2 files changed, 64 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
> index b896b6f6615c..26e2430c0dc1 100644
> --- a/drivers/gpu/drm/xe/xe_bb.c
> +++ b/drivers/gpu/drm/xe/xe_bb.c
> @@ -10,6 +10,7 @@
>  #include "xe_device_types.h"
>  #include "xe_exec_queue_types.h"
>  #include "xe_gt.h"
> +#include "xe_mem_pool.h"
>  #include "xe_sa.h"
>  #include "xe_sched_job.h"
>  #include "xe_vm_types.h"
> @@ -172,3 +173,60 @@ void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence)
>  	xe_sa_bo_free(bb->bo, fence);
>  	kfree(bb);
>  }

why all of this is in xe_bo.c and not in xe_mem_pool.c ?

> +
> +/**
> + * xe_pool_bb_alloc() - Allocate a new batch buffer structure for drm_mm

xe_mem_pool_alloc_node() - Allocate new sub-allocation node for use in xe_mem_pool

> + *
> + * Allocates a new xe_pool_bb structure for use with xe_pool memory
> + * management.
> + *
> + * Returns: Batch buffer structure or an ERR_PTR(-ENOMEM).
> + */
> +struct xe_mem_pool_bb *xe_pool_bb_alloc(void)
> +{
> +	struct xe_mem_pool_bb *bb = kzalloc_obj(*bb);
> +
> +	if (!bb)
> +		return ERR_PTR(-ENOMEM);
> +
> +	return bb;
> +}
> +
> +/**
> + * xe_pool_bb_insert() - Initialize a batch buffer and insert a hole

xe_mem_pool_insert_node(pool, node)

> + * @bb: Batch buffer structure to initialize
> + * @bb_pool: drm_mm manager to allocate from
> + * @dwords: Number of dwords to be allocated

why not bytes?

> + *
> + * Initializes the batch buffer by allocating memory from the specified
> + * drm_mm manager.

drm_mm ?

> + *
> + * Return: 0 on success, negative error code on failure.
> + */
> +int xe_pool_bb_insert(struct xe_mem_pool_bb *bb,
> +		      struct xe_mem_pool_manager *bb_pool, u32 dwords)
> +{
> +	int err;
> +
> +	err = xe_mem_pool_insert_node(bb_pool, &bb->node, 4 * dwords);

this magic 4 is sizeof(u32)

> +	if (err)
> +		return err;
> +
> +	bb->cs = xe_mem_pool_manager_cpu_addr(bb_pool) + bb->node.start;
> +	bb->len = 0;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_pool_bb_free() - Free a batch buffer allocated with drm_mm
> + * @bb: Batch buffer structure to free
> + */
> +void xe_pool_bb_free(struct xe_mem_pool_bb *bb)
> +{
> +	if (!bb)
> +		return;
> +
> +	xe_mem_pool_remove_node(&bb->node);
> +	kfree(bb);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_bb.h b/drivers/gpu/drm/xe/xe_bb.h
> index 231870b24c2f..638d8fc53f1a 100644
> --- a/drivers/gpu/drm/xe/xe_bb.h
> +++ b/drivers/gpu/drm/xe/xe_bb.h
> @@ -12,6 +12,8 @@ struct dma_fence;
>  
>  struct xe_gt;
>  struct xe_exec_queue;
> +struct xe_mem_pool_bb;
> +struct xe_mem_pool_manager;
>  struct xe_sa_manager;
>  struct xe_sched_job;
>  
> @@ -24,5 +26,9 @@ struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q,
>  						struct xe_bb *bb, u64 batch_ofs,
>  						u32 second_idx);
>  void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence);
> +struct xe_mem_pool_bb *xe_pool_bb_alloc(void);
> +int xe_pool_bb_insert(struct xe_mem_pool_bb *bb,
> +		      struct xe_mem_pool_manager *bb_pool, u32 dwords);
> +void xe_pool_bb_free(struct xe_mem_pool_bb *bb);

wrong .h ?

>  
>  #endif

[PATCH v3 3/3] drm/xe/vf: Use drm mm instead of drm sa for CCS read/write

[Satyanarayana K V P]

The suballocator algorithm tracks a hole cursor at the last allocation
and tries to allocate after it. This is optimized for fence-ordered
progress, where older allocations are expected to become reusable first.

In fence-enabled mode, that ordering assumption holds. In fence-disabled
mode, allocations may be freed in arbitrary order, so limiting allocation
to the current hole window can miss valid free space and fail allocations
despite sufficient total space.

Use DRM memory manager instead of sub-allocator to get rid of this issue
as CCS read/write operations do not use fences.

Fixes: 864690cf4dd62 ("drm/xe/vf: Attach and detach CCS copy commands with BO")
Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Maarten Lankhorst <dev@lankhorst.se>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>

---
V2 -> V3:
- Used xe_mem_pool_init() and xe_mem_pool_shadow_init() to allocate BB
pools.

V1 -> V2:
- Renamed xe_drm_mm to xe_mm_suballoc (Thomas)
---
 drivers/gpu/drm/xe/xe_bo_types.h           |  3 +-
 drivers/gpu/drm/xe/xe_migrate.c            | 56 ++++++++++++----------
 drivers/gpu/drm/xe/xe_sriov_vf_ccs.c       | 48 +++++++++----------
 drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h |  5 +-
 4 files changed, 56 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index ff8317bfc1ae..50eec31cb717 100644
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -18,6 +18,7 @@
 #include "xe_ggtt_types.h"
 
 struct xe_device;
+struct xe_mm_sa_bb;
 struct xe_vm;
 
 #define XE_BO_MAX_PLACEMENTS	3
@@ -88,7 +89,7 @@ struct xe_bo {
 	bool ccs_cleared;
 
 	/** @bb_ccs: BB instructions of CCS read/write. Valid only for VF */
-	struct xe_bb *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
+	struct xe_mem_pool_bb *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
 
 	/**
 	 * @cpu_caching: CPU caching mode. Currently only used for userspace
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index fc918b4fba54..fb6827ecea4b 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -29,6 +29,7 @@
 #include "xe_hw_engine.h"
 #include "xe_lrc.h"
 #include "xe_map.h"
+#include "xe_mem_pool.h"
 #include "xe_mocs.h"
 #include "xe_printk.h"
 #include "xe_pt.h"
@@ -1166,11 +1167,12 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 	u32 batch_size, batch_size_allocated;
 	struct xe_device *xe = gt_to_xe(gt);
 	struct xe_res_cursor src_it, ccs_it;
+	struct xe_mem_pool_manager *bb_pool;
 	struct xe_sriov_vf_ccs_ctx *ctx;
-	struct xe_sa_manager *bb_pool;
 	u64 size = xe_bo_size(src_bo);
-	struct xe_bb *bb = NULL;
+	struct xe_mem_pool_bb *bb;
 	u64 src_L0, src_L0_ofs;
+	struct xe_bb xe_bb_tmp;
 	u32 src_L0_pt;
 	int err;
 
@@ -1208,18 +1210,18 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 		size -= src_L0;
 	}
 
-	bb = xe_bb_alloc(gt);
+	bb = xe_pool_bb_alloc();
 	if (IS_ERR(bb))
 		return PTR_ERR(bb);
 
 	bb_pool = ctx->mem.ccs_bb_pool;
-	scoped_guard(mutex, xe_sa_bo_swap_guard(bb_pool)) {
-		xe_sa_bo_swap_shadow(bb_pool);
+	scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) {
+		xe_mem_pool_swap_shadow_locked(bb_pool);
 
-		err = xe_bb_init(bb, bb_pool, batch_size);
+		err = xe_pool_bb_insert(bb, bb_pool, batch_size);
 		if (err) {
 			xe_gt_err(gt, "BB allocation failed.\n");
-			xe_bb_free(bb, NULL);
+			kfree(bb);
 			return err;
 		}
 
@@ -1227,6 +1229,7 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 		size = xe_bo_size(src_bo);
 		batch_size = 0;
 
+		xe_bb_tmp = (struct xe_bb){ .cs = bb->cs, .len = 0 };
 		/*
 		 * Emit PTE and copy commands here.
 		 * The CCS copy command can only support limited size. If the size to be
@@ -1255,24 +1258,27 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 			xe_assert(xe, IS_ALIGNED(ccs_it.start, PAGE_SIZE));
 			batch_size += EMIT_COPY_CCS_DW;
 
-			emit_pte(m, bb, src_L0_pt, false, true, &src_it, src_L0, src);
+			emit_pte(m, &xe_bb_tmp, src_L0_pt, false, true, &src_it, src_L0, src);
 
-			emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src);
+			emit_pte(m, &xe_bb_tmp, ccs_pt, false, false, &ccs_it, ccs_size, src);
 
-			bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags);
-			flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_pltt,
+			xe_bb_tmp.len = emit_flush_invalidate(xe_bb_tmp.cs, xe_bb_tmp.len,
+							      flush_flags);
+			flush_flags = xe_migrate_ccs_copy(m, &xe_bb_tmp, src_L0_ofs, src_is_pltt,
 							  src_L0_ofs, dst_is_pltt,
 							  src_L0, ccs_ofs, true);
-			bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags);
+			xe_bb_tmp.len = emit_flush_invalidate(xe_bb_tmp.cs, xe_bb_tmp.len,
+							      flush_flags);
 
 			size -= src_L0;
 		}
 
-		xe_assert(xe, (batch_size_allocated == bb->len));
+		xe_assert(xe, (batch_size_allocated == xe_bb_tmp.len));
+		bb->len = xe_bb_tmp.len;
 		src_bo->bb_ccs[read_write] = bb;
 
 		xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
-		xe_sa_bo_sync_shadow(bb->bo);
+		xe_mem_pool_sync_shadow_locked(bb_pool, &bb->node);
 	}
 
 	return 0;
@@ -1297,10 +1303,10 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
 				  enum xe_sriov_vf_ccs_rw_ctxs read_write)
 {
-	struct xe_bb *bb = src_bo->bb_ccs[read_write];
+	struct xe_mem_pool_bb *bb = src_bo->bb_ccs[read_write];
 	struct xe_device *xe = xe_bo_device(src_bo);
+	struct xe_mem_pool_manager *bb_pool;
 	struct xe_sriov_vf_ccs_ctx *ctx;
-	struct xe_sa_manager *bb_pool;
 	u32 *cs;
 
 	xe_assert(xe, IS_SRIOV_VF(xe));
@@ -1308,17 +1314,17 @@ void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
 	ctx = &xe->sriov.vf.ccs.contexts[read_write];
 	bb_pool = ctx->mem.ccs_bb_pool;
 
-	guard(mutex) (xe_sa_bo_swap_guard(bb_pool));
-	xe_sa_bo_swap_shadow(bb_pool);
-
-	cs = xe_sa_bo_cpu_addr(bb->bo);
-	memset(cs, MI_NOOP, bb->len * sizeof(u32));
-	xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
+	scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) {
+		xe_mem_pool_swap_shadow_locked(bb_pool);
 
-	xe_sa_bo_sync_shadow(bb->bo);
+		cs = xe_mem_pool_manager_cpu_addr(bb_pool) + bb->node.start;
+		memset(cs, MI_NOOP, bb->len * sizeof(u32));
+		xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
 
-	xe_bb_free(bb, NULL);
-	src_bo->bb_ccs[read_write] = NULL;
+		xe_mem_pool_sync_shadow_locked(bb_pool, &bb->node);
+		xe_pool_bb_free(bb);
+		src_bo->bb_ccs[read_write] = NULL;
+	}
 }
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
index db023fb66a27..3a0abe519536 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
@@ -14,9 +14,9 @@
 #include "xe_guc.h"
 #include "xe_guc_submit.h"
 #include "xe_lrc.h"
+#include "xe_mem_pool.h"
 #include "xe_migrate.h"
 #include "xe_pm.h"
-#include "xe_sa.h"
 #include "xe_sriov_printk.h"
 #include "xe_sriov_vf.h"
 #include "xe_sriov_vf_ccs.h"
@@ -141,43 +141,39 @@ static u64 get_ccs_bb_pool_size(struct xe_device *xe)
 
 static int alloc_bb_pool(struct xe_tile *tile, struct xe_sriov_vf_ccs_ctx *ctx)
 {
+	struct xe_mem_pool_manager *pool_manager;
 	struct xe_device *xe = tile_to_xe(tile);
-	struct xe_sa_manager *sa_manager;
 	u64 bb_pool_size;
-	int offset, err;
+	int err, flags;
 
 	bb_pool_size = get_ccs_bb_pool_size(xe);
 	xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n",
 		      ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M);
 
-	sa_manager = __xe_sa_bo_manager_init(tile, bb_pool_size, SZ_4K, SZ_16,
-					     XE_SA_BO_MANAGER_FLAG_SHADOW);
+	flags = XE_MEM_POOL_BO_FLAG_INIT_CMD_NOOP |
+		XE_MEM_POOL_BO_FLAG_INIT_CMD_BB_END_HIGHEST;
 
-	if (IS_ERR(sa_manager)) {
-		xe_sriov_err(xe, "Suballocator init failed with error: %pe\n",
-			     sa_manager);
-		err = PTR_ERR(sa_manager);
+	pool_manager = xe_mem_pool_init(tile, bb_pool_size, flags);
+	if (IS_ERR(pool_manager)) {
+		xe_sriov_err(xe, "xe_mem_pool_init init failed with error: %pe\n",
+			     pool_manager);
+		err = PTR_ERR(pool_manager);
 		return err;
 	}
 
-	offset = 0;
-	xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP,
-		      bb_pool_size);
-	xe_map_memset(xe, &sa_manager->shadow->vmap, offset, MI_NOOP,
-		      bb_pool_size);
-
-	offset = bb_pool_size - sizeof(u32);
-	xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END);
-	xe_map_wr(xe, &sa_manager->shadow->vmap, offset, u32, MI_BATCH_BUFFER_END);
-
-	ctx->mem.ccs_bb_pool = sa_manager;
+	err = xe_mem_pool_shadow_init(pool_manager, flags);
+	if (err) {
+		xe_sriov_err(xe, "Shadow pool init failed with error: %d\n", err);
+		return err;
+	}
 
+	ctx->mem.ccs_bb_pool = pool_manager;
 	return 0;
 }
 
 static void ccs_rw_update_ring(struct xe_sriov_vf_ccs_ctx *ctx)
 {
-	u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool);
+	u64 addr = xe_mem_pool_manager_gpu_addr(ctx->mem.ccs_bb_pool);
 	struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q);
 	u32 dw[10], i = 0;
 
@@ -388,7 +384,7 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe)
 #define XE_SRIOV_VF_CCS_RW_BB_ADDR_OFFSET	(2 * sizeof(u32))
 void xe_sriov_vf_ccs_rw_update_bb_addr(struct xe_sriov_vf_ccs_ctx *ctx)
 {
-	u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool);
+	u64 addr = xe_mem_pool_manager_gpu_addr(ctx->mem.ccs_bb_pool);
 	struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q);
 	struct xe_device *xe = gt_to_xe(ctx->mig_q->gt);
 
@@ -412,8 +408,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo)
 	struct xe_device *xe = xe_bo_device(bo);
 	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
 	struct xe_sriov_vf_ccs_ctx *ctx;
+	struct xe_mem_pool_bb *bb;
 	struct xe_tile *tile;
-	struct xe_bb *bb;
 	int err = 0;
 
 	xe_assert(xe, IS_VF_CCS_READY(xe));
@@ -445,7 +441,7 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
 {
 	struct xe_device *xe = xe_bo_device(bo);
 	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
-	struct xe_bb *bb;
+	struct xe_mem_pool_bb *bb;
 
 	xe_assert(xe, IS_VF_CCS_READY(xe));
 
@@ -471,8 +467,8 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
  */
 void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p)
 {
-	struct xe_sa_manager *bb_pool;
 	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
+	struct xe_mem_pool_manager *bb_pool;
 
 	if (!IS_VF_CCS_READY(xe))
 		return;
@@ -485,7 +481,7 @@ void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p)
 
 		drm_printf(p, "ccs %s bb suballoc info\n", ctx_id ? "write" : "read");
 		drm_printf(p, "-------------------------\n");
-		drm_suballoc_dump_debug_info(&bb_pool->base, p, xe_sa_manager_gpu_addr(bb_pool));
+		xe_mem_pool_dump(bb_pool, p);
 		drm_puts(p, "\n");
 	}
 }
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
index 22c499943d2a..84584a9b2a4e 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
@@ -17,9 +17,6 @@ enum xe_sriov_vf_ccs_rw_ctxs {
 	XE_SRIOV_VF_CCS_CTX_COUNT
 };
 
-struct xe_migrate;
-struct xe_sa_manager;
-
 /**
  * struct xe_sriov_vf_ccs_ctx - VF CCS migration context data.
  */
@@ -33,7 +30,7 @@ struct xe_sriov_vf_ccs_ctx {
 	/** @mem: memory data */
 	struct {
 		/** @mem.ccs_bb_pool: Pool from which batch buffers are allocated. */
-		struct xe_sa_manager *ccs_bb_pool;
+		struct xe_mem_pool_manager *ccs_bb_pool;
 	} mem;
 };
 
-- 
2.43.0

Re: [PATCH v3 3/3] drm/xe/vf: Use drm mm instead of drm sa for CCS read/write

[Thomas Hellström]

On Wed, 2026-04-01 at 16:15 +0000, Satyanarayana K V P wrote:
> The suballocator algorithm tracks a hole cursor at the last
> allocation
> and tries to allocate after it. This is optimized for fence-ordered
> progress, where older allocations are expected to become reusable
> first.
> 
> In fence-enabled mode, that ordering assumption holds. In fence-
> disabled
> mode, allocations may be freed in arbitrary order, so limiting
> allocation
> to the current hole window can miss valid free space and fail
> allocations
> despite sufficient total space.
> 
> Use DRM memory manager instead of sub-allocator to get rid of this
> issue
> as CCS read/write operations do not use fences.
> 
> Fixes: 864690cf4dd62 ("drm/xe/vf: Attach and detach CCS copy commands
> with BO")
> Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> 
> ---
> V2 -> V3:
> - Used xe_mem_pool_init() and xe_mem_pool_shadow_init() to allocate
> BB
> pools.
> 
> V1 -> V2:
> - Renamed xe_drm_mm to xe_mm_suballoc (Thomas)

Claude's kreview:

commit 937a5e27ca20b0216530e9df59e85acfe2e3c1fb
Author: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>

drm/xe/vf: Use drm mm instead of drm sa for CCS read/write

The suballocator used for CCS batch buffer pools tracks a hole cursor
optimized for fence-ordered frees; in fence-disabled mode, out-of-order
frees can leave valid free space unreachable, causing allocation
failures
despite sufficient total space.  This patch replaces the suballocator
with drm_mm, which does not have that ordering constraint.

> diff --git a/drivers/gpu/drm/xe/xe_bo_types.h
b/drivers/gpu/drm/xe/xe_bo_types.h
> index d4fe3c8dca5b..97d8f9107434 100644
> --- a/drivers/gpu/drm/xe/xe_bo_types.h
> +++ b/drivers/gpu/drm/xe/xe_bo_types.h
> @@ -18,6 +18,7 @@
>  #include "xe_ggtt_types.h"
>
>  struct xe_device;
> +struct xe_mm_sa_bb;
>  struct xe_vm;

This isn't a bug, but the forward declaration names a type xe_mm_sa_bb
that does not appear to be defined anywhere in the driver.  The field
added below uses struct xe_mem_pool_bb, not struct xe_mm_sa_bb.

Should this be:

    struct xe_mem_pool_bb;

or removed entirely?

> [...]
>
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> index db023fb66a27..3a0abe519536 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
> @@ -141,43 +141,39 @@ static u64 get_ccs_bb_pool_size(struct
xe_device *xe)
>
>  static int alloc_bb_pool(struct xe_tile *tile, struct
xe_sriov_vf_ccs_ctx *ctx)
>  {
> [ ... ]
> +	pool_manager = xe_mem_pool_init(tile, bb_pool_size, flags);
> +	if (IS_ERR(pool_manager)) {
> +		xe_sriov_err(xe, "xe_mem_pool_init init failed with
error: %pe\n",
> +			     pool_manager);

The error string "xe_mem_pool_init init" has the word "init" twice.
Was this meant to be "xe_mem_pool_init failed" or "pool init failed"?

Additionally, this patch fixes a bug introduced by:

    Fixes: 864690cf4dd62 ("drm/xe/vf: Attach and detach CCS copy
                           commands with BO")

That commit carries a lore.kernel.org link and a maintainer Signed-off-
by,
suggesting it has landed in a released kernel.  Should this patch carry
a
Cc: stable@vger.kernel.org tag?

Thomas's comment:
Please use "dim fixes <SHA1>" do craft Fixes: tags.

Thanks,
Thomas

✗ CI.checkpatch: warning for USE drm mm instead of drm SA for CCS read/write (rev3)

[Patchwork]

== Series Details ==

Series: USE drm mm instead of drm SA for CCS read/write (rev3)
URL   : https://patchwork.freedesktop.org/series/163588/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit a557f7c3904d1aaa79358e20fc26d1b8ebb5c63f
Author: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
Date:   Wed Apr 1 16:15:28 2026 +0000

    drm/xe/vf: Use drm mm instead of drm sa for CCS read/write
    
    The suballocator algorithm tracks a hole cursor at the last allocation
    and tries to allocate after it. This is optimized for fence-ordered
    progress, where older allocations are expected to become reusable first.
    
    In fence-enabled mode, that ordering assumption holds. In fence-disabled
    mode, allocations may be freed in arbitrary order, so limiting allocation
    to the current hole window can miss valid free space and fail allocations
    despite sufficient total space.
    
    Use DRM memory manager instead of sub-allocator to get rid of this issue
    as CCS read/write operations do not use fences.
    
    Fixes: 864690cf4dd62 ("drm/xe/vf: Attach and detach CCS copy commands with BO")
    Signed-off-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com>
    Cc: Matthew Brost <matthew.brost@intel.com>
    Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
    Cc: Maarten Lankhorst <dev@lankhorst.se>
    Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
+ /mt/dim checkpatch 35dad892ec87d448384f492ba061d0da7e3710a5 drm-intel
5c7b07392973 drm/xe/mm: add XE MEM POOL manager with shadow support
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#31: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 449 lines checked
a7bf18421411 drm/xe/mm: Add batch buffer allocation functions for xe_mem_pool manager
a557f7c3904d drm/xe/vf: Use drm mm instead of drm sa for CCS read/write

✓ CI.KUnit: success for USE drm mm instead of drm SA for CCS read/write (rev3)

[Patchwork]

== Series Details ==

Series: USE drm mm instead of drm SA for CCS read/write (rev3)
URL   : https://patchwork.freedesktop.org/series/163588/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[16:20:12] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:20:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:20:48] Starting KUnit Kernel (1/1)...
[16:20:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:20:49] ================== guc_buf (11 subtests) ===================
[16:20:49] [PASSED] test_smallest
[16:20:49] [PASSED] test_largest
[16:20:49] [PASSED] test_granular
[16:20:49] [PASSED] test_unique
[16:20:49] [PASSED] test_overlap
[16:20:49] [PASSED] test_reusable
[16:20:49] [PASSED] test_too_big
[16:20:49] [PASSED] test_flush
[16:20:49] [PASSED] test_lookup
[16:20:49] [PASSED] test_data
[16:20:49] [PASSED] test_class
[16:20:49] ===================== [PASSED] guc_buf =====================
[16:20:49] =================== guc_dbm (7 subtests) ===================
[16:20:49] [PASSED] test_empty
[16:20:49] [PASSED] test_default
[16:20:49] ======================== test_size  ========================
[16:20:49] [PASSED] 4
[16:20:49] [PASSED] 8
[16:20:49] [PASSED] 32
[16:20:49] [PASSED] 256
[16:20:49] ==================== [PASSED] test_size ====================
[16:20:49] ======================= test_reuse  ========================
[16:20:49] [PASSED] 4
[16:20:49] [PASSED] 8
[16:20:49] [PASSED] 32
[16:20:49] [PASSED] 256
[16:20:49] =================== [PASSED] test_reuse ====================
[16:20:49] =================== test_range_overlap  ====================
[16:20:49] [PASSED] 4
[16:20:49] [PASSED] 8
[16:20:49] [PASSED] 32
[16:20:49] [PASSED] 256
[16:20:49] =============== [PASSED] test_range_overlap ================
[16:20:49] =================== test_range_compact  ====================
[16:20:49] [PASSED] 4
[16:20:49] [PASSED] 8
[16:20:49] [PASSED] 32
[16:20:49] [PASSED] 256
[16:20:49] =============== [PASSED] test_range_compact ================
[16:20:49] ==================== test_range_spare  =====================
[16:20:49] [PASSED] 4
[16:20:49] [PASSED] 8
[16:20:49] [PASSED] 32
[16:20:49] [PASSED] 256
[16:20:49] ================ [PASSED] test_range_spare =================
[16:20:49] ===================== [PASSED] guc_dbm =====================
[16:20:49] =================== guc_idm (6 subtests) ===================
[16:20:49] [PASSED] bad_init
[16:20:49] [PASSED] no_init
[16:20:49] [PASSED] init_fini
[16:20:49] [PASSED] check_used
[16:20:49] [PASSED] check_quota
[16:20:49] [PASSED] check_all
[16:20:49] ===================== [PASSED] guc_idm =====================
[16:20:49] ================== no_relay (3 subtests) ===================
[16:20:49] [PASSED] xe_drops_guc2pf_if_not_ready
[16:20:49] [PASSED] xe_drops_guc2vf_if_not_ready
[16:20:49] [PASSED] xe_rejects_send_if_not_ready
[16:20:49] ==================== [PASSED] no_relay =====================
[16:20:49] ================== pf_relay (14 subtests) ==================
[16:20:49] [PASSED] pf_rejects_guc2pf_too_short
[16:20:49] [PASSED] pf_rejects_guc2pf_too_long
[16:20:49] [PASSED] pf_rejects_guc2pf_no_payload
[16:20:49] [PASSED] pf_fails_no_payload
[16:20:49] [PASSED] pf_fails_bad_origin
[16:20:49] [PASSED] pf_fails_bad_type
[16:20:49] [PASSED] pf_txn_reports_error
[16:20:49] [PASSED] pf_txn_sends_pf2guc
[16:20:49] [PASSED] pf_sends_pf2guc
[16:20:49] [SKIPPED] pf_loopback_nop
[16:20:49] [SKIPPED] pf_loopback_echo
[16:20:49] [SKIPPED] pf_loopback_fail
[16:20:49] [SKIPPED] pf_loopback_busy
[16:20:49] [SKIPPED] pf_loopback_retry
[16:20:49] ==================== [PASSED] pf_relay =====================
[16:20:49] ================== vf_relay (3 subtests) ===================
[16:20:49] [PASSED] vf_rejects_guc2vf_too_short
[16:20:49] [PASSED] vf_rejects_guc2vf_too_long
[16:20:49] [PASSED] vf_rejects_guc2vf_no_payload
[16:20:49] ==================== [PASSED] vf_relay =====================
[16:20:49] ================ pf_gt_config (9 subtests) =================
[16:20:49] [PASSED] fair_contexts_1vf
[16:20:49] [PASSED] fair_doorbells_1vf
[16:20:49] [PASSED] fair_ggtt_1vf
[16:20:49] ====================== fair_vram_1vf  ======================
[16:20:49] [PASSED] 3.50 GiB
[16:20:49] [PASSED] 11.5 GiB
[16:20:49] [PASSED] 15.5 GiB
[16:20:49] [PASSED] 31.5 GiB
[16:20:49] [PASSED] 63.5 GiB
[16:20:49] [PASSED] 1.91 GiB
[16:20:49] ================== [PASSED] fair_vram_1vf ==================
[16:20:49] ================ fair_vram_1vf_admin_only  =================
[16:20:49] [PASSED] 3.50 GiB
[16:20:49] [PASSED] 11.5 GiB
[16:20:49] [PASSED] 15.5 GiB
[16:20:49] [PASSED] 31.5 GiB
[16:20:49] [PASSED] 63.5 GiB
[16:20:49] [PASSED] 1.91 GiB
[16:20:49] ============ [PASSED] fair_vram_1vf_admin_only =============
[16:20:49] ====================== fair_contexts  ======================
[16:20:49] [PASSED] 1 VF
[16:20:49] [PASSED] 2 VFs
[16:20:49] [PASSED] 3 VFs
[16:20:49] [PASSED] 4 VFs
[16:20:49] [PASSED] 5 VFs
[16:20:49] [PASSED] 6 VFs
[16:20:49] [PASSED] 7 VFs
[16:20:49] [PASSED] 8 VFs
[16:20:49] [PASSED] 9 VFs
[16:20:49] [PASSED] 10 VFs
[16:20:49] [PASSED] 11 VFs
[16:20:49] [PASSED] 12 VFs
[16:20:49] [PASSED] 13 VFs
[16:20:49] [PASSED] 14 VFs
[16:20:49] [PASSED] 15 VFs
[16:20:49] [PASSED] 16 VFs
[16:20:49] [PASSED] 17 VFs
[16:20:49] [PASSED] 18 VFs
[16:20:49] [PASSED] 19 VFs
[16:20:49] [PASSED] 20 VFs
[16:20:49] [PASSED] 21 VFs
[16:20:49] [PASSED] 22 VFs
[16:20:49] [PASSED] 23 VFs
[16:20:49] [PASSED] 24 VFs
[16:20:49] [PASSED] 25 VFs
[16:20:49] [PASSED] 26 VFs
[16:20:49] [PASSED] 27 VFs
[16:20:49] [PASSED] 28 VFs
[16:20:49] [PASSED] 29 VFs
[16:20:49] [PASSED] 30 VFs
[16:20:49] [PASSED] 31 VFs
[16:20:49] [PASSED] 32 VFs
[16:20:49] [PASSED] 33 VFs
[16:20:49] [PASSED] 34 VFs
[16:20:49] [PASSED] 35 VFs
[16:20:49] [PASSED] 36 VFs
[16:20:49] [PASSED] 37 VFs
[16:20:49] [PASSED] 38 VFs
[16:20:49] [PASSED] 39 VFs
[16:20:49] [PASSED] 40 VFs
[16:20:49] [PASSED] 41 VFs
[16:20:49] [PASSED] 42 VFs
[16:20:49] [PASSED] 43 VFs
[16:20:49] [PASSED] 44 VFs
[16:20:49] [PASSED] 45 VFs
[16:20:49] [PASSED] 46 VFs
[16:20:49] [PASSED] 47 VFs
[16:20:49] [PASSED] 48 VFs
[16:20:49] [PASSED] 49 VFs
[16:20:49] [PASSED] 50 VFs
[16:20:49] [PASSED] 51 VFs
[16:20:49] [PASSED] 52 VFs
[16:20:49] [PASSED] 53 VFs
[16:20:49] [PASSED] 54 VFs
[16:20:49] [PASSED] 55 VFs
[16:20:49] [PASSED] 56 VFs
[16:20:49] [PASSED] 57 VFs
[16:20:49] [PASSED] 58 VFs
[16:20:49] [PASSED] 59 VFs
[16:20:49] [PASSED] 60 VFs
[16:20:49] [PASSED] 61 VFs
[16:20:49] [PASSED] 62 VFs
[16:20:49] [PASSED] 63 VFs
[16:20:49] ================== [PASSED] fair_contexts ==================
[16:20:49] ===================== fair_doorbells  ======================
[16:20:49] [PASSED] 1 VF
[16:20:49] [PASSED] 2 VFs
[16:20:49] [PASSED] 3 VFs
[16:20:49] [PASSED] 4 VFs
[16:20:49] [PASSED] 5 VFs
[16:20:49] [PASSED] 6 VFs
[16:20:49] [PASSED] 7 VFs
[16:20:49] [PASSED] 8 VFs
[16:20:49] [PASSED] 9 VFs
[16:20:49] [PASSED] 10 VFs
[16:20:49] [PASSED] 11 VFs
[16:20:49] [PASSED] 12 VFs
[16:20:49] [PASSED] 13 VFs
[16:20:49] [PASSED] 14 VFs
[16:20:49] [PASSED] 15 VFs
[16:20:49] [PASSED] 16 VFs
[16:20:49] [PASSED] 17 VFs
[16:20:49] [PASSED] 18 VFs
[16:20:49] [PASSED] 19 VFs
[16:20:49] [PASSED] 20 VFs
[16:20:49] [PASSED] 21 VFs
[16:20:49] [PASSED] 22 VFs
[16:20:49] [PASSED] 23 VFs
[16:20:49] [PASSED] 24 VFs
[16:20:49] [PASSED] 25 VFs
[16:20:49] [PASSED] 26 VFs
[16:20:49] [PASSED] 27 VFs
[16:20:49] [PASSED] 28 VFs
[16:20:49] [PASSED] 29 VFs
[16:20:49] [PASSED] 30 VFs
[16:20:49] [PASSED] 31 VFs
[16:20:49] [PASSED] 32 VFs
[16:20:49] [PASSED] 33 VFs
[16:20:49] [PASSED] 34 VFs
[16:20:49] [PASSED] 35 VFs
[16:20:49] [PASSED] 36 VFs
[16:20:49] [PASSED] 37 VFs
[16:20:49] [PASSED] 38 VFs
[16:20:49] [PASSED] 39 VFs
[16:20:49] [PASSED] 40 VFs
[16:20:49] [PASSED] 41 VFs
[16:20:49] [PASSED] 42 VFs
[16:20:49] [PASSED] 43 VFs
[16:20:49] [PASSED] 44 VFs
[16:20:49] [PASSED] 45 VFs
[16:20:49] [PASSED] 46 VFs
[16:20:49] [PASSED] 47 VFs
[16:20:49] [PASSED] 48 VFs
[16:20:49] [PASSED] 49 VFs
[16:20:49] [PASSED] 50 VFs
[16:20:49] [PASSED] 51 VFs
[16:20:49] [PASSED] 52 VFs
[16:20:49] [PASSED] 53 VFs
[16:20:49] [PASSED] 54 VFs
[16:20:49] [PASSED] 55 VFs
[16:20:49] [PASSED] 56 VFs
[16:20:49] [PASSED] 57 VFs
[16:20:49] [PASSED] 58 VFs
[16:20:49] [PASSED] 59 VFs
[16:20:49] [PASSED] 60 VFs
[16:20:49] [PASSED] 61 VFs
[16:20:49] [PASSED] 62 VFs
[16:20:49] [PASSED] 63 VFs
[16:20:49] ================= [PASSED] fair_doorbells ==================
[16:20:49] ======================== fair_ggtt  ========================
[16:20:49] [PASSED] 1 VF
[16:20:49] [PASSED] 2 VFs
[16:20:49] [PASSED] 3 VFs
[16:20:49] [PASSED] 4 VFs
[16:20:49] [PASSED] 5 VFs
[16:20:49] [PASSED] 6 VFs
[16:20:49] [PASSED] 7 VFs
[16:20:49] [PASSED] 8 VFs
[16:20:49] [PASSED] 9 VFs
[16:20:49] [PASSED] 10 VFs
[16:20:49] [PASSED] 11 VFs
[16:20:49] [PASSED] 12 VFs
[16:20:49] [PASSED] 13 VFs
[16:20:49] [PASSED] 14 VFs
[16:20:49] [PASSED] 15 VFs
[16:20:49] [PASSED] 16 VFs
[16:20:49] [PASSED] 17 VFs
[16:20:49] [PASSED] 18 VFs
[16:20:49] [PASSED] 19 VFs
[16:20:49] [PASSED] 20 VFs
[16:20:49] [PASSED] 21 VFs
[16:20:49] [PASSED] 22 VFs
[16:20:49] [PASSED] 23 VFs
[16:20:49] [PASSED] 24 VFs
[16:20:49] [PASSED] 25 VFs
[16:20:49] [PASSED] 26 VFs
[16:20:49] [PASSED] 27 VFs
[16:20:49] [PASSED] 28 VFs
[16:20:49] [PASSED] 29 VFs
[16:20:49] [PASSED] 30 VFs
[16:20:49] [PASSED] 31 VFs
[16:20:49] [PASSED] 32 VFs
[16:20:49] [PASSED] 33 VFs
[16:20:49] [PASSED] 34 VFs
[16:20:49] [PASSED] 35 VFs
[16:20:49] [PASSED] 36 VFs
[16:20:49] [PASSED] 37 VFs
[16:20:49] [PASSED] 38 VFs
[16:20:49] [PASSED] 39 VFs
[16:20:49] [PASSED] 40 VFs
[16:20:49] [PASSED] 41 VFs
[16:20:49] [PASSED] 42 VFs
[16:20:49] [PASSED] 43 VFs
[16:20:49] [PASSED] 44 VFs
[16:20:49] [PASSED] 45 VFs
[16:20:49] [PASSED] 46 VFs
[16:20:49] [PASSED] 47 VFs
[16:20:49] [PASSED] 48 VFs
[16:20:49] [PASSED] 49 VFs
[16:20:49] [PASSED] 50 VFs
[16:20:49] [PASSED] 51 VFs
[16:20:49] [PASSED] 52 VFs
[16:20:49] [PASSED] 53 VFs
[16:20:49] [PASSED] 54 VFs
[16:20:49] [PASSED] 55 VFs
[16:20:49] [PASSED] 56 VFs
[16:20:49] [PASSED] 57 VFs
[16:20:49] [PASSED] 58 VFs
[16:20:49] [PASSED] 59 VFs
[16:20:49] [PASSED] 60 VFs
[16:20:49] [PASSED] 61 VFs
[16:20:49] [PASSED] 62 VFs
[16:20:49] [PASSED] 63 VFs
[16:20:49] ==================== [PASSED] fair_ggtt ====================
[16:20:49] ======================== fair_vram  ========================
[16:20:49] [PASSED] 1 VF
[16:20:49] [PASSED] 2 VFs
[16:20:49] [PASSED] 3 VFs
[16:20:49] [PASSED] 4 VFs
[16:20:49] [PASSED] 5 VFs
[16:20:49] [PASSED] 6 VFs
[16:20:49] [PASSED] 7 VFs
[16:20:49] [PASSED] 8 VFs
[16:20:49] [PASSED] 9 VFs
[16:20:49] [PASSED] 10 VFs
[16:20:49] [PASSED] 11 VFs
[16:20:49] [PASSED] 12 VFs
[16:20:49] [PASSED] 13 VFs
[16:20:49] [PASSED] 14 VFs
[16:20:49] [PASSED] 15 VFs
[16:20:49] [PASSED] 16 VFs
[16:20:49] [PASSED] 17 VFs
[16:20:49] [PASSED] 18 VFs
[16:20:49] [PASSED] 19 VFs
[16:20:49] [PASSED] 20 VFs
[16:20:49] [PASSED] 21 VFs
[16:20:49] [PASSED] 22 VFs
[16:20:49] [PASSED] 23 VFs
[16:20:49] [PASSED] 24 VFs
[16:20:49] [PASSED] 25 VFs
[16:20:49] [PASSED] 26 VFs
[16:20:49] [PASSED] 27 VFs
[16:20:49] [PASSED] 28 VFs
[16:20:49] [PASSED] 29 VFs
[16:20:49] [PASSED] 30 VFs
[16:20:49] [PASSED] 31 VFs
[16:20:49] [PASSED] 32 VFs
[16:20:49] [PASSED] 33 VFs
[16:20:49] [PASSED] 34 VFs
[16:20:49] [PASSED] 35 VFs
[16:20:49] [PASSED] 36 VFs
[16:20:49] [PASSED] 37 VFs
[16:20:49] [PASSED] 38 VFs
[16:20:49] [PASSED] 39 VFs
[16:20:49] [PASSED] 40 VFs
[16:20:49] [PASSED] 41 VFs
[16:20:49] [PASSED] 42 VFs
[16:20:49] [PASSED] 43 VFs
[16:20:49] [PASSED] 44 VFs
[16:20:49] [PASSED] 45 VFs
[16:20:49] [PASSED] 46 VFs
[16:20:49] [PASSED] 47 VFs
[16:20:49] [PASSED] 48 VFs
[16:20:49] [PASSED] 49 VFs
[16:20:49] [PASSED] 50 VFs
[16:20:49] [PASSED] 51 VFs
[16:20:49] [PASSED] 52 VFs
[16:20:49] [PASSED] 53 VFs
[16:20:49] [PASSED] 54 VFs
[16:20:49] [PASSED] 55 VFs
[16:20:49] [PASSED] 56 VFs
[16:20:49] [PASSED] 57 VFs
[16:20:49] [PASSED] 58 VFs
[16:20:49] [PASSED] 59 VFs
[16:20:49] [PASSED] 60 VFs
[16:20:49] [PASSED] 61 VFs
[16:20:49] [PASSED] 62 VFs
[16:20:49] [PASSED] 63 VFs
[16:20:49] ==================== [PASSED] fair_vram ====================
[16:20:49] ================== [PASSED] pf_gt_config ===================
[16:20:49] ===================== lmtt (1 subtest) =====================
[16:20:49] ======================== test_ops  =========================
[16:20:49] [PASSED] 2-level
[16:20:49] [PASSED] multi-level
[16:20:49] ==================== [PASSED] test_ops =====================
[16:20:49] ====================== [PASSED] lmtt =======================
[16:20:49] ================= pf_service (11 subtests) =================
[16:20:49] [PASSED] pf_negotiate_any
[16:20:49] [PASSED] pf_negotiate_base_match
[16:20:49] [PASSED] pf_negotiate_base_newer
[16:20:49] [PASSED] pf_negotiate_base_next
[16:20:49] [SKIPPED] pf_negotiate_base_older
[16:20:49] [PASSED] pf_negotiate_base_prev
[16:20:49] [PASSED] pf_negotiate_latest_match
[16:20:49] [PASSED] pf_negotiate_latest_newer
[16:20:49] [PASSED] pf_negotiate_latest_next
[16:20:49] [SKIPPED] pf_negotiate_latest_older
[16:20:49] [SKIPPED] pf_negotiate_latest_prev
[16:20:49] =================== [PASSED] pf_service ====================
[16:20:49] ================= xe_guc_g2g (2 subtests) ==================
[16:20:49] ============== xe_live_guc_g2g_kunit_default  ==============
[16:20:49] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[16:20:49] ============== xe_live_guc_g2g_kunit_allmem  ===============
[16:20:49] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[16:20:49] =================== [SKIPPED] xe_guc_g2g ===================
[16:20:49] =================== xe_mocs (2 subtests) ===================
[16:20:49] ================ xe_live_mocs_kernel_kunit  ================
[16:20:49] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[16:20:49] ================ xe_live_mocs_reset_kunit  =================
[16:20:49] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[16:20:49] ==================== [SKIPPED] xe_mocs =====================
[16:20:49] ================= xe_migrate (2 subtests) ==================
[16:20:49] ================= xe_migrate_sanity_kunit  =================
[16:20:49] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[16:20:49] ================== xe_validate_ccs_kunit  ==================
[16:20:49] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[16:20:49] =================== [SKIPPED] xe_migrate ===================
[16:20:49] ================== xe_dma_buf (1 subtest) ==================
[16:20:49] ==================== xe_dma_buf_kunit  =====================
[16:20:49] ================ [SKIPPED] xe_dma_buf_kunit ================
[16:20:49] =================== [SKIPPED] xe_dma_buf ===================
[16:20:49] ================= xe_bo_shrink (1 subtest) =================
[16:20:49] =================== xe_bo_shrink_kunit  ====================
[16:20:49] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[16:20:49] ================== [SKIPPED] xe_bo_shrink ==================
[16:20:49] ==================== xe_bo (2 subtests) ====================
[16:20:49] ================== xe_ccs_migrate_kunit  ===================
[16:20:49] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[16:20:49] ==================== xe_bo_evict_kunit  ====================
[16:20:49] =============== [SKIPPED] xe_bo_evict_kunit ================
[16:20:49] ===================== [SKIPPED] xe_bo ======================
[16:20:49] ==================== args (13 subtests) ====================
[16:20:49] [PASSED] count_args_test
[16:20:49] [PASSED] call_args_example
[16:20:49] [PASSED] call_args_test
[16:20:49] [PASSED] drop_first_arg_example
[16:20:49] [PASSED] drop_first_arg_test
[16:20:49] [PASSED] first_arg_example
[16:20:49] [PASSED] first_arg_test
[16:20:49] [PASSED] last_arg_example
[16:20:49] [PASSED] last_arg_test
[16:20:49] [PASSED] pick_arg_example
[16:20:49] [PASSED] if_args_example
[16:20:49] [PASSED] if_args_test
[16:20:49] [PASSED] sep_comma_example
[16:20:49] ====================== [PASSED] args =======================
[16:20:49] =================== xe_pci (3 subtests) ====================
[16:20:49] ==================== check_graphics_ip  ====================
[16:20:49] [PASSED] 12.00 Xe_LP
[16:20:49] [PASSED] 12.10 Xe_LP+
[16:20:49] [PASSED] 12.55 Xe_HPG
[16:20:49] [PASSED] 12.60 Xe_HPC
[16:20:49] [PASSED] 12.70 Xe_LPG
[16:20:49] [PASSED] 12.71 Xe_LPG
[16:20:49] [PASSED] 12.74 Xe_LPG+
[16:20:49] [PASSED] 20.01 Xe2_HPG
[16:20:49] [PASSED] 20.02 Xe2_HPG
[16:20:49] [PASSED] 20.04 Xe2_LPG
[16:20:49] [PASSED] 30.00 Xe3_LPG
[16:20:49] [PASSED] 30.01 Xe3_LPG
[16:20:49] [PASSED] 30.03 Xe3_LPG
[16:20:49] [PASSED] 30.04 Xe3_LPG
[16:20:49] [PASSED] 30.05 Xe3_LPG
[16:20:49] [PASSED] 35.10 Xe3p_LPG
[16:20:49] [PASSED] 35.11 Xe3p_XPC
[16:20:49] ================ [PASSED] check_graphics_ip ================
[16:20:49] ===================== check_media_ip  ======================
[16:20:49] [PASSED] 12.00 Xe_M
[16:20:49] [PASSED] 12.55 Xe_HPM
[16:20:49] [PASSED] 13.00 Xe_LPM+
[16:20:49] [PASSED] 13.01 Xe2_HPM
[16:20:49] [PASSED] 20.00 Xe2_LPM
[16:20:49] [PASSED] 30.00 Xe3_LPM
[16:20:49] [PASSED] 30.02 Xe3_LPM
[16:20:49] [PASSED] 35.00 Xe3p_LPM
[16:20:49] [PASSED] 35.03 Xe3p_HPM
[16:20:49] ================= [PASSED] check_media_ip ==================
[16:20:49] =================== check_platform_desc  ===================
[16:20:49] [PASSED] 0x9A60 (TIGERLAKE)
[16:20:49] [PASSED] 0x9A68 (TIGERLAKE)
[16:20:49] [PASSED] 0x9A70 (TIGERLAKE)
[16:20:49] [PASSED] 0x9A40 (TIGERLAKE)
[16:20:49] [PASSED] 0x9A49 (TIGERLAKE)
[16:20:49] [PASSED] 0x9A59 (TIGERLAKE)
[16:20:49] [PASSED] 0x9A78 (TIGERLAKE)
[16:20:49] [PASSED] 0x9AC0 (TIGERLAKE)
[16:20:49] [PASSED] 0x9AC9 (TIGERLAKE)
[16:20:49] [PASSED] 0x9AD9 (TIGERLAKE)
[16:20:49] [PASSED] 0x9AF8 (TIGERLAKE)
[16:20:49] [PASSED] 0x4C80 (ROCKETLAKE)
[16:20:49] [PASSED] 0x4C8A (ROCKETLAKE)
[16:20:49] [PASSED] 0x4C8B (ROCKETLAKE)
[16:20:49] [PASSED] 0x4C8C (ROCKETLAKE)
[16:20:49] [PASSED] 0x4C90 (ROCKETLAKE)
[16:20:49] [PASSED] 0x4C9A (ROCKETLAKE)
[16:20:49] [PASSED] 0x4680 (ALDERLAKE_S)
[16:20:49] [PASSED] 0x4682 (ALDERLAKE_S)
[16:20:49] [PASSED] 0x4688 (ALDERLAKE_S)
[16:20:49] [PASSED] 0x468A (ALDERLAKE_S)
[16:20:49] [PASSED] 0x468B (ALDERLAKE_S)
[16:20:49] [PASSED] 0x4690 (ALDERLAKE_S)
[16:20:49] [PASSED] 0x4692 (ALDERLAKE_S)
[16:20:49] [PASSED] 0x4693 (ALDERLAKE_S)
[16:20:49] [PASSED] 0x46A0 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46A1 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46A2 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46A3 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46A6 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46A8 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46AA (ALDERLAKE_P)
[16:20:49] [PASSED] 0x462A (ALDERLAKE_P)
[16:20:49] [PASSED] 0x4626 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x4628 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46B0 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46B1 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46B2 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46B3 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46C0 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46C1 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46C2 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46C3 (ALDERLAKE_P)
[16:20:49] [PASSED] 0x46D0 (ALDERLAKE_N)
[16:20:49] [PASSED] 0x46D1 (ALDERLAKE_N)
[16:20:49] [PASSED] 0x46D2 (ALDERLAKE_N)
[16:20:49] [PASSED] 0x46D3 (ALDERLAKE_N)
[16:20:49] [PASSED] 0x46D4 (ALDERLAKE_N)
[16:20:49] [PASSED] 0xA721 (ALDERLAKE_P)
[16:20:49] [PASSED] 0xA7A1 (ALDERLAKE_P)
[16:20:49] [PASSED] 0xA7A9 (ALDERLAKE_P)
[16:20:49] [PASSED] 0xA7AC (ALDERLAKE_P)
[16:20:49] [PASSED] 0xA7AD (ALDERLAKE_P)
[16:20:49] [PASSED] 0xA720 (ALDERLAKE_P)
[16:20:49] [PASSED] 0xA7A0 (ALDERLAKE_P)
[16:20:49] [PASSED] 0xA7A8 (ALDERLAKE_P)
[16:20:49] [PASSED] 0xA7AA (ALDERLAKE_P)
[16:20:49] [PASSED] 0xA7AB (ALDERLAKE_P)
[16:20:49] [PASSED] 0xA780 (ALDERLAKE_S)
[16:20:49] [PASSED] 0xA781 (ALDERLAKE_S)
[16:20:49] [PASSED] 0xA782 (ALDERLAKE_S)
[16:20:49] [PASSED] 0xA783 (ALDERLAKE_S)
[16:20:49] [PASSED] 0xA788 (ALDERLAKE_S)
[16:20:49] [PASSED] 0xA789 (ALDERLAKE_S)
[16:20:49] [PASSED] 0xA78A (ALDERLAKE_S)
[16:20:49] [PASSED] 0xA78B (ALDERLAKE_S)
[16:20:49] [PASSED] 0x4905 (DG1)
[16:20:49] [PASSED] 0x4906 (DG1)
[16:20:49] [PASSED] 0x4907 (DG1)
[16:20:49] [PASSED] 0x4908 (DG1)
[16:20:49] [PASSED] 0x4909 (DG1)
[16:20:49] [PASSED] 0x56C0 (DG2)
[16:20:49] [PASSED] 0x56C2 (DG2)
[16:20:49] [PASSED] 0x56C1 (DG2)
[16:20:49] [PASSED] 0x7D51 (METEORLAKE)
[16:20:49] [PASSED] 0x7DD1 (METEORLAKE)
[16:20:49] [PASSED] 0x7D41 (METEORLAKE)
[16:20:49] [PASSED] 0x7D67 (METEORLAKE)
[16:20:49] [PASSED] 0xB640 (METEORLAKE)
[16:20:49] [PASSED] 0x56A0 (DG2)
[16:20:49] [PASSED] 0x56A1 (DG2)
[16:20:49] [PASSED] 0x56A2 (DG2)
[16:20:49] [PASSED] 0x56BE (DG2)
[16:20:49] [PASSED] 0x56BF (DG2)
[16:20:49] [PASSED] 0x5690 (DG2)
[16:20:49] [PASSED] 0x5691 (DG2)
[16:20:49] [PASSED] 0x5692 (DG2)
[16:20:49] [PASSED] 0x56A5 (DG2)
[16:20:49] [PASSED] 0x56A6 (DG2)
[16:20:49] [PASSED] 0x56B0 (DG2)
[16:20:49] [PASSED] 0x56B1 (DG2)
[16:20:49] [PASSED] 0x56BA (DG2)
[16:20:49] [PASSED] 0x56BB (DG2)
[16:20:49] [PASSED] 0x56BC (DG2)
[16:20:49] [PASSED] 0x56BD (DG2)
[16:20:49] [PASSED] 0x5693 (DG2)
[16:20:49] [PASSED] 0x5694 (DG2)
[16:20:49] [PASSED] 0x5695 (DG2)
[16:20:49] [PASSED] 0x56A3 (DG2)
[16:20:49] [PASSED] 0x56A4 (DG2)
[16:20:49] [PASSED] 0x56B2 (DG2)
[16:20:49] [PASSED] 0x56B3 (DG2)
[16:20:49] [PASSED] 0x5696 (DG2)
[16:20:49] [PASSED] 0x5697 (DG2)
[16:20:49] [PASSED] 0xB69 (PVC)
[16:20:49] [PASSED] 0xB6E (PVC)
[16:20:49] [PASSED] 0xBD4 (PVC)
[16:20:49] [PASSED] 0xBD5 (PVC)
[16:20:49] [PASSED] 0xBD6 (PVC)
[16:20:49] [PASSED] 0xBD7 (PVC)
[16:20:49] [PASSED] 0xBD8 (PVC)
[16:20:49] [PASSED] 0xBD9 (PVC)
[16:20:49] [PASSED] 0xBDA (PVC)
[16:20:49] [PASSED] 0xBDB (PVC)
[16:20:49] [PASSED] 0xBE0 (PVC)
[16:20:49] [PASSED] 0xBE1 (PVC)
[16:20:49] [PASSED] 0xBE5 (PVC)
[16:20:49] [PASSED] 0x7D40 (METEORLAKE)
[16:20:49] [PASSED] 0x7D45 (METEORLAKE)
[16:20:49] [PASSED] 0x7D55 (METEORLAKE)
[16:20:49] [PASSED] 0x7D60 (METEORLAKE)
[16:20:49] [PASSED] 0x7DD5 (METEORLAKE)
[16:20:49] [PASSED] 0x6420 (LUNARLAKE)
[16:20:49] [PASSED] 0x64A0 (LUNARLAKE)
[16:20:49] [PASSED] 0x64B0 (LUNARLAKE)
[16:20:49] [PASSED] 0xE202 (BATTLEMAGE)
[16:20:49] [PASSED] 0xE209 (BATTLEMAGE)
[16:20:49] [PASSED] 0xE20B (BATTLEMAGE)
[16:20:49] [PASSED] 0xE20C (BATTLEMAGE)
[16:20:49] [PASSED] 0xE20D (BATTLEMAGE)
[16:20:49] [PASSED] 0xE210 (BATTLEMAGE)
[16:20:49] [PASSED] 0xE211 (BATTLEMAGE)
[16:20:49] [PASSED] 0xE212 (BATTLEMAGE)
[16:20:49] [PASSED] 0xE216 (BATTLEMAGE)
[16:20:49] [PASSED] 0xE220 (BATTLEMAGE)
[16:20:49] [PASSED] 0xE221 (BATTLEMAGE)
[16:20:49] [PASSED] 0xE222 (BATTLEMAGE)
[16:20:49] [PASSED] 0xE223 (BATTLEMAGE)
[16:20:49] [PASSED] 0xB080 (PANTHERLAKE)
[16:20:49] [PASSED] 0xB081 (PANTHERLAKE)
[16:20:49] [PASSED] 0xB082 (PANTHERLAKE)
[16:20:49] [PASSED] 0xB083 (PANTHERLAKE)
[16:20:49] [PASSED] 0xB084 (PANTHERLAKE)
[16:20:49] [PASSED] 0xB085 (PANTHERLAKE)
[16:20:49] [PASSED] 0xB086 (PANTHERLAKE)
[16:20:49] [PASSED] 0xB087 (PANTHERLAKE)
[16:20:49] [PASSED] 0xB08F (PANTHERLAKE)
[16:20:49] [PASSED] 0xB090 (PANTHERLAKE)
[16:20:49] [PASSED] 0xB0A0 (PANTHERLAKE)
[16:20:49] [PASSED] 0xB0B0 (PANTHERLAKE)
[16:20:49] [PASSED] 0xFD80 (PANTHERLAKE)
[16:20:49] [PASSED] 0xFD81 (PANTHERLAKE)
[16:20:49] [PASSED] 0xD740 (NOVALAKE_S)
[16:20:49] [PASSED] 0xD741 (NOVALAKE_S)
[16:20:49] [PASSED] 0xD742 (NOVALAKE_S)
[16:20:49] [PASSED] 0xD743 (NOVALAKE_S)
[16:20:49] [PASSED] 0xD744 (NOVALAKE_S)
[16:20:49] [PASSED] 0xD745 (NOVALAKE_S)
[16:20:49] [PASSED] 0x674C (CRESCENTISLAND)
[16:20:49] [PASSED] 0xD750 (NOVALAKE_P)
[16:20:49] [PASSED] 0xD751 (NOVALAKE_P)
[16:20:49] [PASSED] 0xD752 (NOVALAKE_P)
[16:20:49] [PASSED] 0xD753 (NOVALAKE_P)
[16:20:49] [PASSED] 0xD754 (NOVALAKE_P)
[16:20:49] [PASSED] 0xD755 (NOVALAKE_P)
[16:20:49] [PASSED] 0xD756 (NOVALAKE_P)
[16:20:49] [PASSED] 0xD757 (NOVALAKE_P)
[16:20:49] [PASSED] 0xD75F (NOVALAKE_P)
[16:20:49] =============== [PASSED] check_platform_desc ===============
[16:20:49] ===================== [PASSED] xe_pci ======================
[16:20:49] =================== xe_rtp (2 subtests) ====================
[16:20:49] =============== xe_rtp_process_to_sr_tests  ================
[16:20:49] [PASSED] coalesce-same-reg
[16:20:49] [PASSED] no-match-no-add
[16:20:49] [PASSED] match-or
[16:20:49] [PASSED] match-or-xfail
[16:20:49] [PASSED] no-match-no-add-multiple-rules
[16:20:49] [PASSED] two-regs-two-entries
[16:20:49] [PASSED] clr-one-set-other
[16:20:49] [PASSED] set-field
[16:20:49] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[16:20:49] [PASSED] conflict-not-disjoint
[16:20:49] [PASSED] conflict-reg-type
[16:20:49] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[16:20:49] ================== xe_rtp_process_tests  ===================
[16:20:49] [PASSED] active1
[16:20:49] [PASSED] active2
[16:20:49] [PASSED] active-inactive
[16:20:49] [PASSED] inactive-active
[16:20:49] [PASSED] inactive-1st_or_active-inactive
[16:20:49] [PASSED] inactive-2nd_or_active-inactive
[16:20:49] [PASSED] inactive-last_or_active-inactive
[16:20:49] [PASSED] inactive-no_or_active-inactive
[16:20:49] ============== [PASSED] xe_rtp_process_tests ===============
[16:20:49] ===================== [PASSED] xe_rtp ======================
[16:20:49] ==================== xe_wa (1 subtest) =====================
[16:20:49] ======================== xe_wa_gt  =========================
[16:20:49] [PASSED] TIGERLAKE B0
[16:20:49] [PASSED] DG1 A0
[16:20:49] [PASSED] DG1 B0
[16:20:49] [PASSED] ALDERLAKE_S A0
[16:20:49] [PASSED] ALDERLAKE_S B0
[16:20:49] [PASSED] ALDERLAKE_S C0
[16:20:49] [PASSED] ALDERLAKE_S D0
[16:20:49] [PASSED] ALDERLAKE_P A0
[16:20:49] [PASSED] ALDERLAKE_P B0
[16:20:49] [PASSED] ALDERLAKE_P C0
[16:20:49] [PASSED] ALDERLAKE_S RPLS D0
[16:20:49] [PASSED] ALDERLAKE_P RPLU E0
[16:20:49] [PASSED] DG2 G10 C0
[16:20:49] [PASSED] DG2 G11 B1
[16:20:49] [PASSED] DG2 G12 A1
[16:20:49] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:20:49] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:20:49] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[16:20:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[16:20:49] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[16:20:49] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[16:20:49] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[16:20:49] ==================== [PASSED] xe_wa_gt =====================
[16:20:49] ====================== [PASSED] xe_wa ======================
[16:20:49] ============================================================
[16:20:49] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[16:20:49] Elapsed time: 36.469s total, 4.267s configuring, 31.585s building, 0.600s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[16:20:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:20:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:21:16] Starting KUnit Kernel (1/1)...
[16:21:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:21:16] ============ drm_test_pick_cmdline (2 subtests) ============
[16:21:16] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[16:21:16] =============== drm_test_pick_cmdline_named  ===============
[16:21:16] [PASSED] NTSC
[16:21:16] [PASSED] NTSC-J
[16:21:16] [PASSED] PAL
[16:21:16] [PASSED] PAL-M
[16:21:16] =========== [PASSED] drm_test_pick_cmdline_named ===========
[16:21:16] ============== [PASSED] drm_test_pick_cmdline ==============
[16:21:16] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[16:21:16] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[16:21:16] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[16:21:16] =========== drm_validate_clone_mode (2 subtests) ===========
[16:21:16] ============== drm_test_check_in_clone_mode  ===============
[16:21:16] [PASSED] in_clone_mode
[16:21:16] [PASSED] not_in_clone_mode
[16:21:16] ========== [PASSED] drm_test_check_in_clone_mode ===========
[16:21:16] =============== drm_test_check_valid_clones  ===============
[16:21:16] [PASSED] not_in_clone_mode
[16:21:16] [PASSED] valid_clone
[16:21:16] [PASSED] invalid_clone
[16:21:16] =========== [PASSED] drm_test_check_valid_clones ===========
[16:21:16] ============= [PASSED] drm_validate_clone_mode =============
[16:21:16] ============= drm_validate_modeset (1 subtest) =============
[16:21:16] [PASSED] drm_test_check_connector_changed_modeset
[16:21:16] ============== [PASSED] drm_validate_modeset ===============
[16:21:16] ====== drm_test_bridge_get_current_state (2 subtests) ======
[16:21:16] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[16:21:16] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[16:21:16] ======== [PASSED] drm_test_bridge_get_current_state ========
[16:21:16] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[16:21:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[16:21:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[16:21:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[16:21:16] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[16:21:16] ============== drm_bridge_alloc (2 subtests) ===============
[16:21:16] [PASSED] drm_test_drm_bridge_alloc_basic
[16:21:16] [PASSED] drm_test_drm_bridge_alloc_get_put
[16:21:16] ================ [PASSED] drm_bridge_alloc =================
[16:21:16] ============= drm_cmdline_parser (40 subtests) =============
[16:21:16] [PASSED] drm_test_cmdline_force_d_only
[16:21:16] [PASSED] drm_test_cmdline_force_D_only_dvi
[16:21:16] [PASSED] drm_test_cmdline_force_D_only_hdmi
[16:21:16] [PASSED] drm_test_cmdline_force_D_only_not_digital
[16:21:16] [PASSED] drm_test_cmdline_force_e_only
[16:21:16] [PASSED] drm_test_cmdline_res
[16:21:16] [PASSED] drm_test_cmdline_res_vesa
[16:21:16] [PASSED] drm_test_cmdline_res_vesa_rblank
[16:21:16] [PASSED] drm_test_cmdline_res_rblank
[16:21:16] [PASSED] drm_test_cmdline_res_bpp
[16:21:16] [PASSED] drm_test_cmdline_res_refresh
[16:21:16] [PASSED] drm_test_cmdline_res_bpp_refresh
[16:21:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[16:21:16] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[16:21:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[16:21:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[16:21:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[16:21:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[16:21:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[16:21:16] [PASSED] drm_test_cmdline_res_margins_force_on
[16:21:16] [PASSED] drm_test_cmdline_res_vesa_margins
[16:21:16] [PASSED] drm_test_cmdline_name
[16:21:16] [PASSED] drm_test_cmdline_name_bpp
[16:21:16] [PASSED] drm_test_cmdline_name_option
[16:21:16] [PASSED] drm_test_cmdline_name_bpp_option
[16:21:16] [PASSED] drm_test_cmdline_rotate_0
[16:21:16] [PASSED] drm_test_cmdline_rotate_90
[16:21:16] [PASSED] drm_test_cmdline_rotate_180
[16:21:16] [PASSED] drm_test_cmdline_rotate_270
[16:21:16] [PASSED] drm_test_cmdline_hmirror
[16:21:16] [PASSED] drm_test_cmdline_vmirror
[16:21:16] [PASSED] drm_test_cmdline_margin_options
[16:21:16] [PASSED] drm_test_cmdline_multiple_options
[16:21:16] [PASSED] drm_test_cmdline_bpp_extra_and_option
[16:21:16] [PASSED] drm_test_cmdline_extra_and_option
[16:21:16] [PASSED] drm_test_cmdline_freestanding_options
[16:21:16] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[16:21:16] [PASSED] drm_test_cmdline_panel_orientation
[16:21:16] ================ drm_test_cmdline_invalid  =================
[16:21:16] [PASSED] margin_only
[16:21:16] [PASSED] interlace_only
[16:21:16] [PASSED] res_missing_x
[16:21:16] [PASSED] res_missing_y
[16:21:16] [PASSED] res_bad_y
[16:21:16] [PASSED] res_missing_y_bpp
[16:21:16] [PASSED] res_bad_bpp
[16:21:16] [PASSED] res_bad_refresh
[16:21:16] [PASSED] res_bpp_refresh_force_on_off
[16:21:16] [PASSED] res_invalid_mode
[16:21:16] [PASSED] res_bpp_wrong_place_mode
[16:21:16] [PASSED] name_bpp_refresh
[16:21:16] [PASSED] name_refresh
[16:21:16] [PASSED] name_refresh_wrong_mode
[16:21:16] [PASSED] name_refresh_invalid_mode
[16:21:16] [PASSED] rotate_multiple
[16:21:16] [PASSED] rotate_invalid_val
[16:21:16] [PASSED] rotate_truncated
[16:21:16] [PASSED] invalid_option
[16:21:16] [PASSED] invalid_tv_option
[16:21:16] [PASSED] truncated_tv_option
[16:21:16] ============ [PASSED] drm_test_cmdline_invalid =============
[16:21:16] =============== drm_test_cmdline_tv_options  ===============
[16:21:16] [PASSED] NTSC
[16:21:16] [PASSED] NTSC_443
[16:21:16] [PASSED] NTSC_J
[16:21:16] [PASSED] PAL
[16:21:16] [PASSED] PAL_M
[16:21:16] [PASSED] PAL_N
[16:21:16] [PASSED] SECAM
[16:21:16] [PASSED] MONO_525
[16:21:16] [PASSED] MONO_625
[16:21:16] =========== [PASSED] drm_test_cmdline_tv_options ===========
[16:21:16] =============== [PASSED] drm_cmdline_parser ================
[16:21:16] ========== drmm_connector_hdmi_init (20 subtests) ==========
[16:21:16] [PASSED] drm_test_connector_hdmi_init_valid
[16:21:16] [PASSED] drm_test_connector_hdmi_init_bpc_8
[16:21:16] [PASSED] drm_test_connector_hdmi_init_bpc_10
[16:21:16] [PASSED] drm_test_connector_hdmi_init_bpc_12
[16:21:16] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[16:21:16] [PASSED] drm_test_connector_hdmi_init_bpc_null
[16:21:16] [PASSED] drm_test_connector_hdmi_init_formats_empty
[16:21:16] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[16:21:16] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[16:21:16] [PASSED] supported_formats=0x9 yuv420_allowed=1
[16:21:16] [PASSED] supported_formats=0x9 yuv420_allowed=0
[16:21:16] [PASSED] supported_formats=0x5 yuv420_allowed=1
[16:21:16] [PASSED] supported_formats=0x5 yuv420_allowed=0
[16:21:16] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[16:21:16] [PASSED] drm_test_connector_hdmi_init_null_ddc
[16:21:16] [PASSED] drm_test_connector_hdmi_init_null_product
[16:21:16] [PASSED] drm_test_connector_hdmi_init_null_vendor
[16:21:16] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[16:21:16] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[16:21:16] [PASSED] drm_test_connector_hdmi_init_product_valid
[16:21:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[16:21:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[16:21:16] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[16:21:16] ========= drm_test_connector_hdmi_init_type_valid  =========
[16:21:16] [PASSED] HDMI-A
[16:21:16] [PASSED] HDMI-B
[16:21:16] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[16:21:16] ======== drm_test_connector_hdmi_init_type_invalid  ========
[16:21:16] [PASSED] Unknown
[16:21:16] [PASSED] VGA
[16:21:16] [PASSED] DVI-I
[16:21:16] [PASSED] DVI-D
[16:21:16] [PASSED] DVI-A
[16:21:16] [PASSED] Composite
[16:21:16] [PASSED] SVIDEO
[16:21:16] [PASSED] LVDS
[16:21:16] [PASSED] Component
[16:21:16] [PASSED] DIN
[16:21:16] [PASSED] DP
[16:21:16] [PASSED] TV
[16:21:16] [PASSED] eDP
[16:21:16] [PASSED] Virtual
[16:21:16] [PASSED] DSI
[16:21:16] [PASSED] DPI
[16:21:16] [PASSED] Writeback
[16:21:16] [PASSED] SPI
[16:21:16] [PASSED] USB
[16:21:16] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[16:21:16] ============ [PASSED] drmm_connector_hdmi_init =============
[16:21:16] ============= drmm_connector_init (3 subtests) =============
[16:21:16] [PASSED] drm_test_drmm_connector_init
[16:21:16] [PASSED] drm_test_drmm_connector_init_null_ddc
[16:21:16] ========= drm_test_drmm_connector_init_type_valid  =========
[16:21:16] [PASSED] Unknown
[16:21:16] [PASSED] VGA
[16:21:16] [PASSED] DVI-I
[16:21:16] [PASSED] DVI-D
[16:21:16] [PASSED] DVI-A
[16:21:16] [PASSED] Composite
[16:21:16] [PASSED] SVIDEO
[16:21:16] [PASSED] LVDS
[16:21:16] [PASSED] Component
[16:21:16] [PASSED] DIN
[16:21:16] [PASSED] DP
[16:21:16] [PASSED] HDMI-A
[16:21:16] [PASSED] HDMI-B
[16:21:16] [PASSED] TV
[16:21:16] [PASSED] eDP
[16:21:16] [PASSED] Virtual
[16:21:16] [PASSED] DSI
[16:21:16] [PASSED] DPI
[16:21:16] [PASSED] Writeback
[16:21:16] [PASSED] SPI
[16:21:16] [PASSED] USB
[16:21:16] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[16:21:16] =============== [PASSED] drmm_connector_init ===============
[16:21:16] ========= drm_connector_dynamic_init (6 subtests) ==========
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_init
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_init_properties
[16:21:16] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[16:21:16] [PASSED] Unknown
[16:21:16] [PASSED] VGA
[16:21:16] [PASSED] DVI-I
[16:21:16] [PASSED] DVI-D
[16:21:16] [PASSED] DVI-A
[16:21:16] [PASSED] Composite
[16:21:16] [PASSED] SVIDEO
[16:21:16] [PASSED] LVDS
[16:21:16] [PASSED] Component
[16:21:16] [PASSED] DIN
[16:21:16] [PASSED] DP
[16:21:16] [PASSED] HDMI-A
[16:21:16] [PASSED] HDMI-B
[16:21:16] [PASSED] TV
[16:21:16] [PASSED] eDP
[16:21:16] [PASSED] Virtual
[16:21:16] [PASSED] DSI
[16:21:16] [PASSED] DPI
[16:21:16] [PASSED] Writeback
[16:21:16] [PASSED] SPI
[16:21:16] [PASSED] USB
[16:21:16] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[16:21:16] ======== drm_test_drm_connector_dynamic_init_name  =========
[16:21:16] [PASSED] Unknown
[16:21:16] [PASSED] VGA
[16:21:16] [PASSED] DVI-I
[16:21:16] [PASSED] DVI-D
[16:21:16] [PASSED] DVI-A
[16:21:16] [PASSED] Composite
[16:21:16] [PASSED] SVIDEO
[16:21:16] [PASSED] LVDS
[16:21:16] [PASSED] Component
[16:21:16] [PASSED] DIN
[16:21:16] [PASSED] DP
[16:21:16] [PASSED] HDMI-A
[16:21:16] [PASSED] HDMI-B
[16:21:16] [PASSED] TV
[16:21:16] [PASSED] eDP
[16:21:16] [PASSED] Virtual
[16:21:16] [PASSED] DSI
[16:21:16] [PASSED] DPI
[16:21:16] [PASSED] Writeback
[16:21:16] [PASSED] SPI
[16:21:16] [PASSED] USB
[16:21:16] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[16:21:16] =========== [PASSED] drm_connector_dynamic_init ============
[16:21:16] ==== drm_connector_dynamic_register_early (4 subtests) =====
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[16:21:16] ====== [PASSED] drm_connector_dynamic_register_early =======
[16:21:16] ======= drm_connector_dynamic_register (7 subtests) ========
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[16:21:16] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[16:21:16] ========= [PASSED] drm_connector_dynamic_register ==========
[16:21:16] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[16:21:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[16:21:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[16:21:16] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[16:21:16] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[16:21:16] ========== drm_test_get_tv_mode_from_name_valid  ===========
[16:21:16] [PASSED] NTSC
[16:21:16] [PASSED] NTSC-443
[16:21:16] [PASSED] NTSC-J
[16:21:16] [PASSED] PAL
[16:21:16] [PASSED] PAL-M
[16:21:16] [PASSED] PAL-N
[16:21:16] [PASSED] SECAM
[16:21:16] [PASSED] Mono
[16:21:16] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[16:21:16] [PASSED] drm_test_get_tv_mode_from_name_truncated
[16:21:16] ============ [PASSED] drm_get_tv_mode_from_name ============
[16:21:16] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[16:21:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[16:21:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[16:21:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[16:21:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[16:21:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[16:21:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[16:21:16] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[16:21:16] [PASSED] VIC 96
[16:21:16] [PASSED] VIC 97
[16:21:16] [PASSED] VIC 101
[16:21:16] [PASSED] VIC 102
[16:21:16] [PASSED] VIC 106
[16:21:16] [PASSED] VIC 107
[16:21:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[16:21:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[16:21:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[16:21:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[16:21:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[16:21:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[16:21:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[16:21:16] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[16:21:16] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[16:21:16] [PASSED] Automatic
[16:21:16] [PASSED] Full
[16:21:16] [PASSED] Limited 16:235
[16:21:16] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[16:21:16] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[16:21:16] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[16:21:16] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[16:21:16] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[16:21:16] [PASSED] RGB
[16:21:16] [PASSED] YUV 4:2:0
[16:21:16] [PASSED] YUV 4:2:2
[16:21:16] [PASSED] YUV 4:4:4
[16:21:16] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[16:21:16] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[16:21:16] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[16:21:16] ============= drm_damage_helper (21 subtests) ==============
[16:21:16] [PASSED] drm_test_damage_iter_no_damage
[16:21:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[16:21:16] [PASSED] drm_test_damage_iter_no_damage_src_moved
[16:21:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[16:21:16] [PASSED] drm_test_damage_iter_no_damage_not_visible
[16:21:16] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[16:21:16] [PASSED] drm_test_damage_iter_no_damage_no_fb
[16:21:16] [PASSED] drm_test_damage_iter_simple_damage
[16:21:16] [PASSED] drm_test_damage_iter_single_damage
[16:21:16] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[16:21:16] [PASSED] drm_test_damage_iter_single_damage_outside_src
[16:21:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[16:21:16] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[16:21:16] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[16:21:16] [PASSED] drm_test_damage_iter_single_damage_src_moved
[16:21:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[16:21:16] [PASSED] drm_test_damage_iter_damage
[16:21:16] [PASSED] drm_test_damage_iter_damage_one_intersect
[16:21:16] [PASSED] drm_test_damage_iter_damage_one_outside
[16:21:16] [PASSED] drm_test_damage_iter_damage_src_moved
[16:21:16] [PASSED] drm_test_damage_iter_damage_not_visible
[16:21:16] ================ [PASSED] drm_damage_helper ================
[16:21:16] ============== drm_dp_mst_helper (3 subtests) ==============
[16:21:16] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[16:21:16] [PASSED] Clock 154000 BPP 30 DSC disabled
[16:21:16] [PASSED] Clock 234000 BPP 30 DSC disabled
[16:21:16] [PASSED] Clock 297000 BPP 24 DSC disabled
[16:21:16] [PASSED] Clock 332880 BPP 24 DSC enabled
[16:21:16] [PASSED] Clock 324540 BPP 24 DSC enabled
[16:21:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[16:21:16] ============== drm_test_dp_mst_calc_pbn_div  ===============
[16:21:16] [PASSED] Link rate 2000000 lane count 4
[16:21:16] [PASSED] Link rate 2000000 lane count 2
[16:21:16] [PASSED] Link rate 2000000 lane count 1
[16:21:16] [PASSED] Link rate 1350000 lane count 4
[16:21:16] [PASSED] Link rate 1350000 lane count 2
[16:21:16] [PASSED] Link rate 1350000 lane count 1
[16:21:16] [PASSED] Link rate 1000000 lane count 4
[16:21:16] [PASSED] Link rate 1000000 lane count 2
[16:21:16] [PASSED] Link rate 1000000 lane count 1
[16:21:16] [PASSED] Link rate 810000 lane count 4
[16:21:16] [PASSED] Link rate 810000 lane count 2
[16:21:16] [PASSED] Link rate 810000 lane count 1
[16:21:16] [PASSED] Link rate 540000 lane count 4
[16:21:16] [PASSED] Link rate 540000 lane count 2
[16:21:16] [PASSED] Link rate 540000 lane count 1
[16:21:16] [PASSED] Link rate 270000 lane count 4
[16:21:16] [PASSED] Link rate 270000 lane count 2
[16:21:16] [PASSED] Link rate 270000 lane count 1
[16:21:16] [PASSED] Link rate 162000 lane count 4
[16:21:16] [PASSED] Link rate 162000 lane count 2
[16:21:16] [PASSED] Link rate 162000 lane count 1
[16:21:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[16:21:16] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[16:21:16] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[16:21:16] [PASSED] DP_POWER_UP_PHY with port number
[16:21:16] [PASSED] DP_POWER_DOWN_PHY with port number
[16:21:16] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[16:21:16] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[16:21:16] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[16:21:16] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[16:21:16] [PASSED] DP_QUERY_PAYLOAD with port number
[16:21:16] [PASSED] DP_QUERY_PAYLOAD with VCPI
[16:21:16] [PASSED] DP_REMOTE_DPCD_READ with port number
[16:21:16] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[16:21:16] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[16:21:16] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[16:21:16] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[16:21:16] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[16:21:16] [PASSED] DP_REMOTE_I2C_READ with port number
[16:21:16] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[16:21:16] [PASSED] DP_REMOTE_I2C_READ with transactions array
[16:21:16] [PASSED] DP_REMOTE_I2C_WRITE with port number
[16:21:16] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[16:21:16] [PASSED] DP_REMOTE_I2C_WRITE with data array
[16:21:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[16:21:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[16:21:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[16:21:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[16:21:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[16:21:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[16:21:16] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[16:21:16] ================ [PASSED] drm_dp_mst_helper ================
[16:21:16] ================== drm_exec (7 subtests) ===================
[16:21:16] [PASSED] sanitycheck
[16:21:16] [PASSED] test_lock
[16:21:16] [PASSED] test_lock_unlock
[16:21:16] [PASSED] test_duplicates
[16:21:16] [PASSED] test_prepare
[16:21:16] [PASSED] test_prepare_array
[16:21:16] [PASSED] test_multiple_loops
[16:21:16] ==================== [PASSED] drm_exec =====================
[16:21:16] =========== drm_format_helper_test (17 subtests) ===========
[16:21:16] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[16:21:16] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[16:21:16] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[16:21:16] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[16:21:16] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[16:21:16] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[16:21:16] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[16:21:16] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[16:21:16] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[16:21:16] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[16:21:16] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[16:21:16] ============== drm_test_fb_xrgb8888_to_mono  ===============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[16:21:16] ==================== drm_test_fb_swab  =====================
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ================ [PASSED] drm_test_fb_swab =================
[16:21:16] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[16:21:16] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[16:21:16] [PASSED] single_pixel_source_buffer
[16:21:16] [PASSED] single_pixel_clip_rectangle
[16:21:16] [PASSED] well_known_colors
[16:21:16] [PASSED] destination_pitch
[16:21:16] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[16:21:16] ================= drm_test_fb_clip_offset  =================
[16:21:16] [PASSED] pass through
[16:21:16] [PASSED] horizontal offset
[16:21:16] [PASSED] vertical offset
[16:21:16] [PASSED] horizontal and vertical offset
[16:21:16] [PASSED] horizontal offset (custom pitch)
[16:21:16] [PASSED] vertical offset (custom pitch)
[16:21:16] [PASSED] horizontal and vertical offset (custom pitch)
[16:21:16] ============= [PASSED] drm_test_fb_clip_offset =============
[16:21:16] =================== drm_test_fb_memcpy  ====================
[16:21:16] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[16:21:16] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[16:21:16] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[16:21:16] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[16:21:16] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[16:21:16] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[16:21:16] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[16:21:16] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[16:21:16] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[16:21:16] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[16:21:16] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[16:21:16] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[16:21:16] =============== [PASSED] drm_test_fb_memcpy ================
[16:21:16] ============= [PASSED] drm_format_helper_test ==============
[16:21:16] ================= drm_format (18 subtests) =================
[16:21:16] [PASSED] drm_test_format_block_width_invalid
[16:21:16] [PASSED] drm_test_format_block_width_one_plane
[16:21:16] [PASSED] drm_test_format_block_width_two_plane
[16:21:16] [PASSED] drm_test_format_block_width_three_plane
[16:21:16] [PASSED] drm_test_format_block_width_tiled
[16:21:16] [PASSED] drm_test_format_block_height_invalid
[16:21:16] [PASSED] drm_test_format_block_height_one_plane
[16:21:16] [PASSED] drm_test_format_block_height_two_plane
[16:21:16] [PASSED] drm_test_format_block_height_three_plane
[16:21:16] [PASSED] drm_test_format_block_height_tiled
[16:21:16] [PASSED] drm_test_format_min_pitch_invalid
[16:21:16] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[16:21:16] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[16:21:16] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[16:21:16] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[16:21:16] [PASSED] drm_test_format_min_pitch_two_plane
[16:21:16] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[16:21:16] [PASSED] drm_test_format_min_pitch_tiled
[16:21:16] =================== [PASSED] drm_format ====================
[16:21:16] ============== drm_framebuffer (10 subtests) ===============
[16:21:16] ========== drm_test_framebuffer_check_src_coords  ==========
[16:21:16] [PASSED] Success: source fits into fb
[16:21:16] [PASSED] Fail: overflowing fb with x-axis coordinate
[16:21:16] [PASSED] Fail: overflowing fb with y-axis coordinate
[16:21:16] [PASSED] Fail: overflowing fb with source width
[16:21:16] [PASSED] Fail: overflowing fb with source height
[16:21:16] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[16:21:16] [PASSED] drm_test_framebuffer_cleanup
[16:21:16] =============== drm_test_framebuffer_create  ===============
[16:21:16] [PASSED] ABGR8888 normal sizes
[16:21:16] [PASSED] ABGR8888 max sizes
[16:21:16] [PASSED] ABGR8888 pitch greater than min required
[16:21:16] [PASSED] ABGR8888 pitch less than min required
[16:21:16] [PASSED] ABGR8888 Invalid width
[16:21:16] [PASSED] ABGR8888 Invalid buffer handle
[16:21:16] [PASSED] No pixel format
[16:21:16] [PASSED] ABGR8888 Width 0
[16:21:16] [PASSED] ABGR8888 Height 0
[16:21:16] [PASSED] ABGR8888 Out of bound height * pitch combination
[16:21:16] [PASSED] ABGR8888 Large buffer offset
[16:21:16] [PASSED] ABGR8888 Buffer offset for inexistent plane
[16:21:16] [PASSED] ABGR8888 Invalid flag
[16:21:16] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[16:21:16] [PASSED] ABGR8888 Valid buffer modifier
[16:21:16] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[16:21:16] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[16:21:16] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[16:21:16] [PASSED] NV12 Normal sizes
[16:21:16] [PASSED] NV12 Max sizes
[16:21:16] [PASSED] NV12 Invalid pitch
[16:21:16] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[16:21:16] [PASSED] NV12 different  modifier per-plane
[16:21:16] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[16:21:16] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[16:21:16] [PASSED] NV12 Modifier for inexistent plane
[16:21:16] [PASSED] NV12 Handle for inexistent plane
[16:21:16] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[16:21:16] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[16:21:16] [PASSED] YVU420 Normal sizes
[16:21:16] [PASSED] YVU420 Max sizes
[16:21:16] [PASSED] YVU420 Invalid pitch
[16:21:16] [PASSED] YVU420 Different pitches
[16:21:16] [PASSED] YVU420 Different buffer offsets/pitches
[16:21:16] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[16:21:16] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[16:21:16] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[16:21:16] [PASSED] YVU420 Valid modifier
[16:21:16] [PASSED] YVU420 Different modifiers per plane
[16:21:16] [PASSED] YVU420 Modifier for inexistent plane
[16:21:16] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[16:21:16] [PASSED] X0L2 Normal sizes
[16:21:16] [PASSED] X0L2 Max sizes
[16:21:16] [PASSED] X0L2 Invalid pitch
[16:21:16] [PASSED] X0L2 Pitch greater than minimum required
[16:21:16] [PASSED] X0L2 Handle for inexistent plane
[16:21:16] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[16:21:16] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[16:21:16] [PASSED] X0L2 Valid modifier
[16:21:16] [PASSED] X0L2 Modifier for inexistent plane
[16:21:16] =========== [PASSED] drm_test_framebuffer_create ===========
[16:21:16] [PASSED] drm_test_framebuffer_free
[16:21:16] [PASSED] drm_test_framebuffer_init
[16:21:16] [PASSED] drm_test_framebuffer_init_bad_format
[16:21:16] [PASSED] drm_test_framebuffer_init_dev_mismatch
[16:21:16] [PASSED] drm_test_framebuffer_lookup
[16:21:16] [PASSED] drm_test_framebuffer_lookup_inexistent
[16:21:16] [PASSED] drm_test_framebuffer_modifiers_not_supported
[16:21:16] ================= [PASSED] drm_framebuffer =================
[16:21:16] ================ drm_gem_shmem (8 subtests) ================
[16:21:16] [PASSED] drm_gem_shmem_test_obj_create
[16:21:16] [PASSED] drm_gem_shmem_test_obj_create_private
[16:21:16] [PASSED] drm_gem_shmem_test_pin_pages
[16:21:16] [PASSED] drm_gem_shmem_test_vmap
[16:21:16] [PASSED] drm_gem_shmem_test_get_sg_table
[16:21:16] [PASSED] drm_gem_shmem_test_get_pages_sgt
[16:21:16] [PASSED] drm_gem_shmem_test_madvise
[16:21:16] [PASSED] drm_gem_shmem_test_purge
[16:21:16] ================== [PASSED] drm_gem_shmem ==================
[16:21:16] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[16:21:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[16:21:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[16:21:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[16:21:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[16:21:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[16:21:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[16:21:16] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[16:21:16] [PASSED] Automatic
[16:21:16] [PASSED] Full
[16:21:16] [PASSED] Limited 16:235
[16:21:16] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[16:21:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[16:21:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[16:21:16] [PASSED] drm_test_check_disable_connector
[16:21:16] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[16:21:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[16:21:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[16:21:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[16:21:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[16:21:16] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[16:21:16] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[16:21:16] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[16:21:16] [PASSED] drm_test_check_output_bpc_dvi
[16:21:16] [PASSED] drm_test_check_output_bpc_format_vic_1
[16:21:16] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[16:21:16] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[16:21:16] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[16:21:16] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[16:21:16] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[16:21:16] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[16:21:16] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[16:21:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[16:21:16] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[16:21:16] [PASSED] drm_test_check_broadcast_rgb_value
[16:21:16] [PASSED] drm_test_check_bpc_8_value
[16:21:16] [PASSED] drm_test_check_bpc_10_value
[16:21:16] [PASSED] drm_test_check_bpc_12_value
[16:21:16] [PASSED] drm_test_check_format_value
[16:21:16] [PASSED] drm_test_check_tmds_char_value
[16:21:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[16:21:16] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[16:21:16] [PASSED] drm_test_check_mode_valid
[16:21:16] [PASSED] drm_test_check_mode_valid_reject
[16:21:16] [PASSED] drm_test_check_mode_valid_reject_rate
[16:21:16] [PASSED] drm_test_check_mode_valid_reject_max_clock
[16:21:16] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[16:21:16] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[16:21:16] [PASSED] drm_test_check_infoframes
[16:21:16] [PASSED] drm_test_check_reject_avi_infoframe
[16:21:16] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[16:21:16] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[16:21:16] [PASSED] drm_test_check_reject_audio_infoframe
[16:21:16] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[16:21:16] ================= drm_managed (2 subtests) =================
[16:21:16] [PASSED] drm_test_managed_release_action
[16:21:16] [PASSED] drm_test_managed_run_action
[16:21:16] =================== [PASSED] drm_managed ===================
[16:21:16] =================== drm_mm (6 subtests) ====================
[16:21:16] [PASSED] drm_test_mm_init
[16:21:16] [PASSED] drm_test_mm_debug
[16:21:16] [PASSED] drm_test_mm_align32
[16:21:16] [PASSED] drm_test_mm_align64
[16:21:16] [PASSED] drm_test_mm_lowest
[16:21:16] [PASSED] drm_test_mm_highest
[16:21:16] ===================== [PASSED] drm_mm ======================
[16:21:16] ============= drm_modes_analog_tv (5 subtests) =============
[16:21:16] [PASSED] drm_test_modes_analog_tv_mono_576i
[16:21:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[16:21:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[16:21:16] [PASSED] drm_test_modes_analog_tv_pal_576i
[16:21:16] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[16:21:16] =============== [PASSED] drm_modes_analog_tv ===============
[16:21:16] ============== drm_plane_helper (2 subtests) ===============
[16:21:16] =============== drm_test_check_plane_state  ================
[16:21:16] [PASSED] clipping_simple
[16:21:16] [PASSED] clipping_rotate_reflect
[16:21:16] [PASSED] positioning_simple
[16:21:16] [PASSED] upscaling
[16:21:16] [PASSED] downscaling
[16:21:16] [PASSED] rounding1
[16:21:16] [PASSED] rounding2
[16:21:16] [PASSED] rounding3
[16:21:16] [PASSED] rounding4
[16:21:16] =========== [PASSED] drm_test_check_plane_state ============
[16:21:16] =========== drm_test_check_invalid_plane_state  ============
[16:21:16] [PASSED] positioning_invalid
[16:21:16] [PASSED] upscaling_invalid
[16:21:16] [PASSED] downscaling_invalid
[16:21:16] ======= [PASSED] drm_test_check_invalid_plane_state ========
[16:21:16] ================ [PASSED] drm_plane_helper =================
[16:21:16] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[16:21:16] ====== drm_test_connector_helper_tv_get_modes_check  =======
[16:21:16] [PASSED] None
[16:21:16] [PASSED] PAL
[16:21:16] [PASSED] NTSC
[16:21:16] [PASSED] Both, NTSC Default
[16:21:16] [PASSED] Both, PAL Default
[16:21:16] [PASSED] Both, NTSC Default, with PAL on command-line
[16:21:16] [PASSED] Both, PAL Default, with NTSC on command-line
[16:21:16] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[16:21:16] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[16:21:16] ================== drm_rect (9 subtests) ===================
[16:21:16] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[16:21:16] [PASSED] drm_test_rect_clip_scaled_not_clipped
[16:21:16] [PASSED] drm_test_rect_clip_scaled_clipped
[16:21:16] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[16:21:16] ================= drm_test_rect_intersect  =================
[16:21:16] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[16:21:16] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[16:21:16] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[16:21:16] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[16:21:16] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[16:21:16] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[16:21:16] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[16:21:16] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[16:21:16] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[16:21:16] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[16:21:16] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[16:21:16] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[16:21:16] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[16:21:16] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[16:21:16] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[16:21:16] ============= [PASSED] drm_test_rect_intersect =============
[16:21:16] ================ drm_test_rect_calc_hscale  ================
[16:21:16] [PASSED] normal use
[16:21:16] [PASSED] out of max range
[16:21:16] [PASSED] out of min range
[16:21:16] [PASSED] zero dst
[16:21:16] [PASSED] negative src
[16:21:16] [PASSED] negative dst
[16:21:16] ============ [PASSED] drm_test_rect_calc_hscale ============
[16:21:16] ================ drm_test_rect_calc_vscale  ================
[16:21:16] [PASSED] normal use
[16:21:16] [PASSED] out of max range
[16:21:16] [PASSED] out of min range
[16:21:16] [PASSED] zero dst
[16:21:16] [PASSED] negative src
[16:21:16] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[16:21:16] ============ [PASSED] drm_test_rect_calc_vscale ============
[16:21:16] ================== drm_test_rect_rotate  ===================
[16:21:16] [PASSED] reflect-x
[16:21:16] [PASSED] reflect-y
[16:21:16] [PASSED] rotate-0
[16:21:16] [PASSED] rotate-90
[16:21:16] [PASSED] rotate-180
[16:21:16] [PASSED] rotate-270
[16:21:16] ============== [PASSED] drm_test_rect_rotate ===============
[16:21:16] ================ drm_test_rect_rotate_inv  =================
[16:21:16] [PASSED] reflect-x
[16:21:16] [PASSED] reflect-y
[16:21:16] [PASSED] rotate-0
[16:21:16] [PASSED] rotate-90
[16:21:16] [PASSED] rotate-180
[16:21:16] [PASSED] rotate-270
[16:21:16] ============ [PASSED] drm_test_rect_rotate_inv =============
[16:21:16] ==================== [PASSED] drm_rect =====================
[16:21:16] ============ drm_sysfb_modeset_test (1 subtest) ============
[16:21:16] ============ drm_test_sysfb_build_fourcc_list  =============
[16:21:16] [PASSED] no native formats
[16:21:16] [PASSED] XRGB8888 as native format
[16:21:16] [PASSED] remove duplicates
[16:21:16] [PASSED] convert alpha formats
[16:21:16] [PASSED] random formats
[16:21:16] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[16:21:16] ============= [PASSED] drm_sysfb_modeset_test ==============
[16:21:16] ================== drm_fixp (2 subtests) ===================
[16:21:16] [PASSED] drm_test_int2fixp
[16:21:16] [PASSED] drm_test_sm2fixp
[16:21:16] ==================== [PASSED] drm_fixp =====================
[16:21:16] ============================================================
[16:21:16] Testing complete. Ran 621 tests: passed: 621
[16:21:16] Elapsed time: 26.627s total, 1.737s configuring, 24.725s building, 0.120s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[16:21:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:21:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:21:27] Starting KUnit Kernel (1/1)...
[16:21:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:21:27] ================= ttm_device (5 subtests) ==================
[16:21:27] [PASSED] ttm_device_init_basic
[16:21:27] [PASSED] ttm_device_init_multiple
[16:21:27] [PASSED] ttm_device_fini_basic
[16:21:27] [PASSED] ttm_device_init_no_vma_man
[16:21:27] ================== ttm_device_init_pools  ==================
[16:21:27] [PASSED] No DMA allocations, no DMA32 required
[16:21:27] [PASSED] DMA allocations, DMA32 required
[16:21:27] [PASSED] No DMA allocations, DMA32 required
[16:21:27] [PASSED] DMA allocations, no DMA32 required
[16:21:27] ============== [PASSED] ttm_device_init_pools ==============
[16:21:27] =================== [PASSED] ttm_device ====================
[16:21:27] ================== ttm_pool (8 subtests) ===================
[16:21:27] ================== ttm_pool_alloc_basic  ===================
[16:21:27] [PASSED] One page
[16:21:27] [PASSED] More than one page
[16:21:27] [PASSED] Above the allocation limit
[16:21:27] [PASSED] One page, with coherent DMA mappings enabled
[16:21:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:21:27] ============== [PASSED] ttm_pool_alloc_basic ===============
[16:21:27] ============== ttm_pool_alloc_basic_dma_addr  ==============
[16:21:27] [PASSED] One page
[16:21:27] [PASSED] More than one page
[16:21:27] [PASSED] Above the allocation limit
[16:21:27] [PASSED] One page, with coherent DMA mappings enabled
[16:21:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:21:27] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[16:21:27] [PASSED] ttm_pool_alloc_order_caching_match
[16:21:27] [PASSED] ttm_pool_alloc_caching_mismatch
[16:21:27] [PASSED] ttm_pool_alloc_order_mismatch
[16:21:27] [PASSED] ttm_pool_free_dma_alloc
[16:21:27] [PASSED] ttm_pool_free_no_dma_alloc
[16:21:27] [PASSED] ttm_pool_fini_basic
[16:21:27] ==================== [PASSED] ttm_pool =====================
[16:21:27] ================ ttm_resource (8 subtests) =================
[16:21:27] ================= ttm_resource_init_basic  =================
[16:21:27] [PASSED] Init resource in TTM_PL_SYSTEM
[16:21:27] [PASSED] Init resource in TTM_PL_VRAM
[16:21:27] [PASSED] Init resource in a private placement
[16:21:27] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[16:21:27] ============= [PASSED] ttm_resource_init_basic =============
[16:21:27] [PASSED] ttm_resource_init_pinned
[16:21:27] [PASSED] ttm_resource_fini_basic
[16:21:27] [PASSED] ttm_resource_manager_init_basic
[16:21:27] [PASSED] ttm_resource_manager_usage_basic
[16:21:27] [PASSED] ttm_resource_manager_set_used_basic
[16:21:27] [PASSED] ttm_sys_man_alloc_basic
[16:21:27] [PASSED] ttm_sys_man_free_basic
[16:21:27] ================== [PASSED] ttm_resource ===================
[16:21:27] =================== ttm_tt (15 subtests) ===================
[16:21:27] ==================== ttm_tt_init_basic  ====================
[16:21:27] [PASSED] Page-aligned size
[16:21:27] [PASSED] Extra pages requested
[16:21:27] ================ [PASSED] ttm_tt_init_basic ================
[16:21:27] [PASSED] ttm_tt_init_misaligned
[16:21:27] [PASSED] ttm_tt_fini_basic
[16:21:27] [PASSED] ttm_tt_fini_sg
[16:21:27] [PASSED] ttm_tt_fini_shmem
[16:21:27] [PASSED] ttm_tt_create_basic
[16:21:27] [PASSED] ttm_tt_create_invalid_bo_type
[16:21:27] [PASSED] ttm_tt_create_ttm_exists
[16:21:27] [PASSED] ttm_tt_create_failed
[16:21:27] [PASSED] ttm_tt_destroy_basic
[16:21:27] [PASSED] ttm_tt_populate_null_ttm
[16:21:27] [PASSED] ttm_tt_populate_populated_ttm
[16:21:27] [PASSED] ttm_tt_unpopulate_basic
[16:21:27] [PASSED] ttm_tt_unpopulate_empty_ttm
[16:21:27] [PASSED] ttm_tt_swapin_basic
[16:21:27] ===================== [PASSED] ttm_tt ======================
[16:21:27] =================== ttm_bo (14 subtests) ===================
[16:21:27] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[16:21:27] [PASSED] Cannot be interrupted and sleeps
[16:21:27] [PASSED] Cannot be interrupted, locks straight away
[16:21:27] [PASSED] Can be interrupted, sleeps
[16:21:27] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[16:21:27] [PASSED] ttm_bo_reserve_locked_no_sleep
[16:21:27] [PASSED] ttm_bo_reserve_no_wait_ticket
[16:21:27] [PASSED] ttm_bo_reserve_double_resv
[16:21:27] [PASSED] ttm_bo_reserve_interrupted
[16:21:27] [PASSED] ttm_bo_reserve_deadlock
[16:21:27] [PASSED] ttm_bo_unreserve_basic
[16:21:27] [PASSED] ttm_bo_unreserve_pinned
[16:21:27] [PASSED] ttm_bo_unreserve_bulk
[16:21:27] [PASSED] ttm_bo_fini_basic
[16:21:27] [PASSED] ttm_bo_fini_shared_resv
[16:21:27] [PASSED] ttm_bo_pin_basic
[16:21:27] [PASSED] ttm_bo_pin_unpin_resource
[16:21:27] [PASSED] ttm_bo_multiple_pin_one_unpin
[16:21:27] ===================== [PASSED] ttm_bo ======================
[16:21:27] ============== ttm_bo_validate (22 subtests) ===============
[16:21:27] ============== ttm_bo_init_reserved_sys_man  ===============
[16:21:27] [PASSED] Buffer object for userspace
[16:21:27] [PASSED] Kernel buffer object
[16:21:27] [PASSED] Shared buffer object
[16:21:27] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[16:21:27] ============== ttm_bo_init_reserved_mock_man  ==============
[16:21:27] [PASSED] Buffer object for userspace
[16:21:27] [PASSED] Kernel buffer object
[16:21:27] [PASSED] Shared buffer object
[16:21:27] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[16:21:27] [PASSED] ttm_bo_init_reserved_resv
[16:21:27] ================== ttm_bo_validate_basic  ==================
[16:21:27] [PASSED] Buffer object for userspace
[16:21:27] [PASSED] Kernel buffer object
[16:21:27] [PASSED] Shared buffer object
[16:21:27] ============== [PASSED] ttm_bo_validate_basic ==============
[16:21:27] [PASSED] ttm_bo_validate_invalid_placement
[16:21:27] ============= ttm_bo_validate_same_placement  ==============
[16:21:27] [PASSED] System manager
[16:21:27] [PASSED] VRAM manager
[16:21:27] ========= [PASSED] ttm_bo_validate_same_placement ==========
[16:21:27] [PASSED] ttm_bo_validate_failed_alloc
[16:21:27] [PASSED] ttm_bo_validate_pinned
[16:21:27] [PASSED] ttm_bo_validate_busy_placement
[16:21:27] ================ ttm_bo_validate_multihop  =================
[16:21:27] [PASSED] Buffer object for userspace
[16:21:27] [PASSED] Kernel buffer object
[16:21:27] [PASSED] Shared buffer object
[16:21:27] ============ [PASSED] ttm_bo_validate_multihop =============
[16:21:27] ========== ttm_bo_validate_no_placement_signaled  ==========
[16:21:27] [PASSED] Buffer object in system domain, no page vector
[16:21:27] [PASSED] Buffer object in system domain with an existing page vector
[16:21:27] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[16:21:27] ======== ttm_bo_validate_no_placement_not_signaled  ========
[16:21:27] [PASSED] Buffer object for userspace
[16:21:27] [PASSED] Kernel buffer object
[16:21:27] [PASSED] Shared buffer object
[16:21:27] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[16:21:27] [PASSED] ttm_bo_validate_move_fence_signaled
[16:21:27] ========= ttm_bo_validate_move_fence_not_signaled  =========
[16:21:27] [PASSED] Waits for GPU
[16:21:27] [PASSED] Tries to lock straight away
[16:21:27] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[16:21:27] [PASSED] ttm_bo_validate_swapout
[16:21:27] [PASSED] ttm_bo_validate_happy_evict
[16:21:27] [PASSED] ttm_bo_validate_all_pinned_evict
[16:21:27] [PASSED] ttm_bo_validate_allowed_only_evict
[16:21:27] [PASSED] ttm_bo_validate_deleted_evict
[16:21:27] [PASSED] ttm_bo_validate_busy_domain_evict
[16:21:27] [PASSED] ttm_bo_validate_evict_gutting
[16:21:27] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[16:21:27] ================= [PASSED] ttm_bo_validate =================
[16:21:27] ============================================================
[16:21:27] Testing complete. Ran 102 tests: passed: 102
[16:21:27] Elapsed time: 11.630s total, 1.715s configuring, 9.699s building, 0.181s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for USE drm mm instead of drm SA for CCS read/write (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3262 bytes --]

== Series Details ==

Series: USE drm mm instead of drm SA for CCS read/write (rev3)
URL   : https://patchwork.freedesktop.org/series/163588/
State : failure

== Summary ==

CI Bug Log - changes from xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2_BAT -> xe-pw-163588v3_BAT
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-163588v3_BAT absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-163588v3_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-163588v3_BAT:

### IGT changes ###

#### Possible regressions ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-ptl-vm:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/bat-ptl-vm/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/bat-ptl-vm/igt@core_hotunplug@unbind-rebind.html

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - bat-ptl-1:          [PASS][3] -> [ABORT][4] +1 other test abort
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/bat-ptl-1/igt@sriov_basic@enable-vfs-autoprobe-on.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/bat-ptl-1/igt@sriov_basic@enable-vfs-autoprobe-on.html
    - bat-wcl-1:          [PASS][5] -> [ABORT][6] +1 other test abort
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/bat-wcl-1/igt@sriov_basic@enable-vfs-autoprobe-on.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/bat-wcl-1/igt@sriov_basic@enable-vfs-autoprobe-on.html
    - bat-wcl-2:          [PASS][7] -> [ABORT][8] +1 other test abort
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/bat-wcl-2/igt@sriov_basic@enable-vfs-autoprobe-on.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/bat-wcl-2/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1:
    - bat-ptl-2:          [PASS][9] -> [ABORT][10] +1 other test abort
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/bat-ptl-2/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/bat-ptl-2/igt@sriov_basic@enable-vfs-autoprobe-on@numvfs-1.html

  


Build changes
-------------

  * IGT: IGT_8839 -> IGT_8840
  * Linux: xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2 -> xe-pw-163588v3

  IGT_8839: 8839
  IGT_8840: 8840
  xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2: 5d36e6d54e963f0c1137aaf2249d2baa781f08c2
  xe-pw-163588v3: 163588v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/index.html

[-- Attachment #2: Type: text/html, Size: 3948 bytes --]

✗ Xe.CI.FULL: failure for USE drm mm instead of drm SA for CCS read/write (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4670 bytes --]

== Series Details ==

Series: USE drm mm instead of drm SA for CCS read/write (rev3)
URL   : https://patchwork.freedesktop.org/series/163588/
State : failure

== Summary ==

CI Bug Log - changes from xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2_FULL -> xe-pw-163588v3_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-163588v3_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-163588v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-163588v3_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_sriov_vfio@region-info:
    - shard-lnl:          NOTRUN -> [SKIP][1] +2 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/shard-lnl-1/igt@xe_sriov_vfio@region-info.html

  
Known issues
------------

  Here are the changes found in xe-pw-163588v3_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][2] -> [FAIL][3] ([Intel XE#301]) +4 other tests fail
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [PASS][4] -> [FAIL][5] ([Intel XE#7340] / [Intel XE#7504])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/shard-lnl-1/igt@kms_pm_dc@dc5-dpms.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/shard-lnl-6/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [PASS][6] -> [FAIL][7] ([Intel XE#7340])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/shard-lnl-2/igt@kms_pm_dc@dc5-psr.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/shard-lnl-1/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-lnl:          [PASS][8] -> [FAIL][9] ([Intel XE#2029] / [Intel XE#7395])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/shard-lnl-3/igt@kms_pm_dc@deep-pkgc.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/shard-lnl-5/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_setmode@basic@pipe-a-edp-1:
    - shard-lnl:          [PASS][10] -> [FAIL][11] ([Intel XE#6361]) +1 other test fail
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/shard-lnl-1/igt@kms_setmode@basic@pipe-a-edp-1.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/shard-lnl-2/igt@kms_setmode@basic@pipe-a-edp-1.html

  
#### Possible fixes ####

  * igt@kms_vrr@flipline:
    - shard-lnl:          [FAIL][12] ([Intel XE#4227] / [Intel XE#7397]) -> [PASS][13] +1 other test pass
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2/shard-lnl-7/igt@kms_vrr@flipline.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/shard-lnl-1/igt@kms_vrr@flipline.html

  
  [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#6361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6361
  [Intel XE#7340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7340
  [Intel XE#7395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7395
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7504


Build changes
-------------

  * IGT: IGT_8839 -> IGT_8840
  * Linux: xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2 -> xe-pw-163588v3

  IGT_8839: 8839
  IGT_8840: 8840
  xe-4833-5d36e6d54e963f0c1137aaf2249d2baa781f08c2: 5d36e6d54e963f0c1137aaf2249d2baa781f08c2
  xe-pw-163588v3: 163588v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163588v3/index.html

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