From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
<intel-gfx@lists.freedesktop.org>
Cc: <intel-xe@lists.freedesktop.org>,
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Subject: Re: [PATCH v2 4/9] drm/i915/dp: Restructure the sink/output format selection
Date: Thu, 9 Apr 2026 16:21:37 +0530 [thread overview]
Message-ID: <58ecede7-5cf9-4000-9635-2d4bbeb269c2@intel.com> (raw)
In-Reply-To: <20260409101539.22032-5-ville.syrjala@linux.intel.com>
On 4/9/2026 3:45 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Restructure intel_dp_compute_output_format() to resemble the new
> intel_hdmi_compute_output_formats().
>
> Again, we basically have two main code paths:
> - YCbCr 4:2:0 only modes
> - everything else including YCbCr 4:2:0 also modes
>
> Take the exact same approach with the DP code, making the
> format selection much less convoluted.
>
> Cc: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 98 +++++++++++++++++--------
> 1 file changed, 69 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index b8b6d62fb275..ed5841f224ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1379,6 +1379,28 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
> return MODE_OK;
> }
>
> +static enum drm_mode_status
> +intel_dp_sink_format_valid(struct intel_connector *connector,
> + const struct drm_display_mode *mode,
> + enum intel_output_format sink_format)
> +{
> + const struct drm_display_info *info = &connector->base.display_info;
> +
> + switch (sink_format) {
> + case INTEL_OUTPUT_FORMAT_YCBCR420:
> + if (!connector->base.ycbcr_420_allowed ||
> + !drm_mode_is_420(info, mode))
> + return MODE_NO_420;
> +
> + return MODE_OK;
> + case INTEL_OUTPUT_FORMAT_RGB:
> + return MODE_OK;
> + default:
> + MISSING_CASE(sink_format);
> + return MODE_BAD;
> + }
> +}
> +
> int intel_dp_max_hdisplay_per_pipe(struct intel_display *display)
> {
> return DISPLAY_VER(display) >= 30 ? 6144 : 5120;
> @@ -3338,41 +3360,59 @@ static int
> intel_dp_compute_output_format(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state,
> - bool respect_downstream_limits)
> + bool respect_downstream_limits,
> + enum intel_output_format sink_format)
> {
> - struct intel_display *display = to_intel_display(encoder);
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> struct intel_connector *connector = intel_dp->attached_connector;
> - const struct drm_display_info *info = &connector->base.display_info;
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> - bool ycbcr_420_only;
> - int ret;
>
> - ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
> -
> - if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
> - drm_dbg_kms(display->drm,
> - "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
> - crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> - } else {
> - crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
> - }
> + if (intel_dp_sink_format_valid(connector, adjusted_mode,
> + sink_format) != MODE_OK)
> + return -EINVAL;
>
> + crtc_state->sink_format = sink_format;
> crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
>
> - ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
> - respect_downstream_limits);
> - if (ret) {
> - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> - !connector->base.ycbcr_420_allowed ||
> - !drm_mode_is_420_also(info, adjusted_mode))
> - return ret;
> -
> - crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> - crtc_state->output_format = intel_dp_output_format(connector,
> - crtc_state->sink_format);
> - ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
> - respect_downstream_limits);
> + return intel_dp_compute_link_config(encoder, crtc_state, conn_state,
> + respect_downstream_limits);
> +}
> +
> +static int
> +intel_dp_compute_formats(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
> + bool respect_downstream_limits)
> +{
> + struct intel_display *display = to_intel_display(encoder);
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + struct intel_connector *connector = intel_dp->attached_connector;
> + const struct drm_display_info *info = &connector->base.display_info;
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> + int ret;
> +
> + if (drm_mode_is_420_only(info, adjusted_mode)) {
> + ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state,
> + respect_downstream_limits,
> + INTEL_OUTPUT_FORMAT_YCBCR420);
> +
> + if (ret) {
> + drm_dbg_kms(display->drm,
> + "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
> +
> + ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state,
> + respect_downstream_limits,
> + INTEL_OUTPUT_FORMAT_RGB);
> + }
> + } else {
> + ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state,
> + respect_downstream_limits,
> + INTEL_OUTPUT_FORMAT_RGB);
> +
> + if (ret && drm_mode_is_420_also(info, adjusted_mode))
> + ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state,
> + respect_downstream_limits,
> + INTEL_OUTPUT_FORMAT_YCBCR420);
> }
>
> return ret;
> @@ -3547,9 +3587,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> * Try to respect downstream TMDS clock limits first, if
> * that fails assume the user might know something we don't.
> */
> - ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
> + ret = intel_dp_compute_formats(encoder, pipe_config, conn_state, true);
> if (ret)
> - ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
> + ret = intel_dp_compute_formats(encoder, pipe_config, conn_state, false);
> if (ret)
> return ret;
>
next prev parent reply other threads:[~2026-04-09 10:51 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-09 10:15 [PATCH v2 0/9] drm/i915/{dp, hdmi}: Restructure DP/HDMI sink format handling Ville Syrjala
2026-04-09 10:15 ` [PATCH v2 1/9] drm/i915/hdmi: Add missing intel_pfit_mode_valid() for 4:2:0 also modes Ville Syrjala
2026-04-09 10:15 ` [PATCH v2 2/9] drm/i915/hdmi: Restructure the sink/output format selection Ville Syrjala
2026-04-09 10:15 ` [PATCH v2 3/9] drm/i915/hdmi: Restructure 4:2:0 vs. 4:4:4 mode validation Ville Syrjala
2026-04-09 10:15 ` [PATCH v2 4/9] drm/i915/dp: Restructure the sink/output format selection Ville Syrjala
2026-04-09 10:51 ` Nautiyal, Ankit K [this message]
2026-04-09 10:15 ` [PATCH v2 5/9] drm/i915/dp: Validate "4:2:0 also" modes twice Ville Syrjala
2026-04-09 10:58 ` Nautiyal, Ankit K
2026-04-09 10:15 ` [PATCH v2 6/9] drm/i915/dp: Require a HDMI sink for YCbCr output via PCON Ville Syrjala
2026-04-09 10:15 ` [PATCH v2 7/9] drm/i915/dp: Validate sink format in .mode_valid() Ville Syrjala
2026-04-09 10:15 ` [PATCH v2 8/9] drm/i915/hdmi: Make the RGB fallback for "4:2:0 only" modes the last resort Ville Syrjala
2026-04-09 10:15 ` [PATCH v2 9/9] drm/i915/dp: " Ville Syrjala
2026-04-09 10:23 ` ✗ CI.KUnit: failure for drm/i915/{dp, hdmi}: Restructure DP/HDMI sink format handling (rev2) Patchwork
2026-04-09 15:40 ` [PATCH v2 0/9] drm/i915/{dp, hdmi}: Restructure DP/HDMI sink format handling Nicolas Frattaroli
2026-04-10 10:07 ` ✗ CI.checkpatch: warning for drm/i915/{dp, hdmi}: Restructure DP/HDMI sink format handling (rev3) Patchwork
2026-04-10 10:08 ` ✓ CI.KUnit: success " Patchwork
2026-04-10 10:53 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-10 17:42 ` ✗ Xe.CI.FULL: failure " Patchwork
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