Re: [PATCH v2] drm/xe/mmio: Avoid double-adjust in 64-bit reads

[Jani Nikula <jani.nikula@linux.intel.com>]

On Fri, 30 Jan 2026, Shuicheng Lin <shuicheng.lin@intel.com> wrote:
> xe_mmio_read64_2x32() was adjusting register addresses and then
> calling xe_mmio_read32(), which applies the adjustment again.
> This may shift accesses twice if adj_offset < adj_limit. There is
> no issue currently, as for media gt, adj_offset > adj_limit, so
> the 2nd adjust will be a no-op. But it may not work in future.
>
> To fix it, replace the adjusted-address comparison with a direct
> sanity check that ensures the MMIO address adjustment cutoff never
> falls within the 8-byte range of a 64-bit register. And let
> xe_mmio_read32() handle address translation.
>
> v2: rewrite the sanity check in a more natural way. (Matt)
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com>

Fixes: ?

> ---
>  drivers/gpu/drm/xe/xe_mmio.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index bcb6674b7dac..a1a05c68dc7d 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -256,11 +256,11 @@ u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg)
>  	struct xe_reg reg_udw = { .addr = reg.addr + 0x4 };
>  	u32 ldw, udw, oldudw, retries;
>  
> -	reg.addr = xe_mmio_adjusted_addr(mmio, reg.addr);
> -	reg_udw.addr = xe_mmio_adjusted_addr(mmio, reg_udw.addr);
> -
> -	/* we shouldn't adjust just one register address */
> -	xe_tile_assert(mmio->tile, reg_udw.addr == reg.addr + 0x4);
> +	/*
> +	 * The two dwords of a 64-bit register can never straddle the offset
> +	 * adjustment cutoff.
> +	 */
> +	xe_tile_assert(mmio->tile, !in_range(mmio->adj_limit, reg.addr + 1, 7));
>  
>  	oldudw = xe_mmio_read32(mmio, reg_udw);
>  	for (retries = 5; retries; --retries) {

-- 
Jani Nikula, Intel