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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by PH8PR11MB6755.namprd11.prod.outlook.com (2603:10b6:510:1ca::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.22; Wed, 4 Mar 2026 08:37:02 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::68b9:ea3c:8166:3cc4]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::68b9:ea3c:8166:3cc4%4]) with mapi id 15.20.9678.016; Wed, 4 Mar 2026 08:37:01 +0000 Message-ID: <5bb046c8-b154-4fc3-a119-e7c2a41b4c6b@intel.com> Date: Wed, 4 Mar 2026 14:06:54 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/4] drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters To: =?UTF-8?Q?Jouni_H=C3=B6gander?= , , References: <20260303125409.503148-1-jouni.hogander@intel.com> <20260303125409.503148-4-jouni.hogander@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20260303125409.503148-4-jouni.hogander@intel.com> Content-Type: text/plain; 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Add helper for configuring these. > > Bspec: 71709 > Signed-off-by: Jouni Högander > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 22 ++++++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_vdsc.h | 3 +++ > 2 files changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 7e53201b3cb1..ae3af3c2e41a 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -820,6 +820,28 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder, > sizeof(dp_dsc_pps_sdp)); > } > > +void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, int su_lines) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > + enum pipe pipe = crtc->pipe; > + int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); > + int slice_row_per_frame = su_lines / vdsc_cfg->slice_height; > + u32 val; > + > + drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height); > + > + val = DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame); > + val |= DSC_SUPS0_SU_PIC_HEIGHT(su_lines); > + > + intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val); > + > + if (vdsc_instances_per_pipe > 1) > + intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val); Currently 3 DSC engines per pipe is only supported on BMG, which doesn't have eDP, so vdsc_instances_per_pipe would never be 3 for now. Furthermore we do not support these registers for BMG AFAICS. However later some platform may have 3 VDSC engines and who knows may need the Selective Update ET configuration for DSC. Since we do not have those registers defined, lets make this condition specifically check for `vdsc_instances_per_pipe == 1` We can have perhaps have WARN_ON if vdsc_instances_per_pipe > 2, at the start, as we do not expect the SU ET configuration for 3rd VDSC engine yet. Regards, Ankit > +} > + > static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) > { > return is_pipe_dsc(crtc, cpu_transcoder) ? > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h > index f4d5b37293cf..3372f8694054 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.h > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h > @@ -14,6 +14,7 @@ enum transcoder; > struct intel_crtc; > struct intel_crtc_state; > struct intel_display; > +struct intel_dsb; > struct intel_dsc_slice_config; > struct intel_encoder; > > @@ -37,6 +38,8 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); > void intel_dsc_dp_pps_write(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); > +void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, int su_lines); > void intel_vdsc_state_dump(struct drm_printer *p, int indent, > const struct intel_crtc_state *crtc_state); > int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);