Re: [PATCH 3/4] drm/xe/xe2: Limit ccs framebuffers to tile4 only

[Matthew Auld <matthew.auld@intel.com>]

On 18/01/2024 15:27, Juha-Pekka Heikkila wrote:
> Display engine support ccs only with tile4, prevent other modifiers
> from using compressed memory.
> 
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
>   drivers/gpu/drm/xe/display/xe_fb_pin.c | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index 722c84a56607..579badb8c69e 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -13,6 +13,16 @@
>   
>   #include <drm/ttm/ttm_bo.h>
>   
> +static bool is_compressed(const struct drm_framebuffer *fb)
> +{
> +	struct xe_bo *bo = intel_fb_obj(fb);
> +	struct xe_device *xe = to_xe_device(to_intel_framebuffer(fb)->base.dev);
> +	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
> +	u16 pat_index_compressed = tile_to_xe(ggtt->tile)->pat.idx[XE_CACHE_WT];

Why just this index? There seems to be various indexes that turn on 
compression. How about annotating the pat index table and then have a 
helper like xe_pat_index_has_compression(xe, pat_index)?

@@ -104,7 +104,8 @@ static const struct xe_pat_table_entry 
xelpg_pat_table[] = {
                         REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \
                         REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \
                         REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \
-               .coh_mode = __coh_mode ? XE_COH_AT_LEAST_1WAY : 
XE_COH_NONE \
+               .coh_mode = __coh_mode ? XE_COH_AT_LEAST_1WAY : 
XE_COH_NONE, \
+               .compressed = comp_en \
         }

  static const struct xe_pat_table_entry xe2_pat_table[] = {
@@ -148,6 +149,12 @@ u16 xe_pat_index_get_coh_mode(struct xe_device *xe, 
u16 pat_index)
         return xe->pat.table[pat_index].coh_mode;
  }

+bool xe_pat_index_has_compression(struct xe_device *xe, u16 pat_index)
+{
+       WARN_ON(pat_index >= xe->pat.n_entries);
+       return xe->pat.table[pat_index].compressed;
+}
+
  static void program_pat(struct xe_gt *gt, const struct 
xe_pat_table_entry table[],
                         int n_entries)
  {
diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
index fa0dfbe525cd..37666ba1aec4 100644
--- a/drivers/gpu/drm/xe/xe_pat.h
+++ b/drivers/gpu/drm/xe/xe_pat.h
@@ -29,6 +29,7 @@ struct xe_pat_table_entry {
  #define XE_COH_NONE          1
  #define XE_COH_AT_LEAST_1WAY 2
         u16 coh_mode;
+       bool compressed;
  };

  /**
@@ -58,4 +59,6 @@ void xe_pat_dump(struct xe_gt *gt, struct drm_printer *p);
   */
  u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index);

+bool xe_pat_index_has_compression(struct xe_device *xe, u16 pat_index);

> +
> +	return (bo->pat_index == pat_index_compressed);
> +}
> +
>   static void
>   write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_ofs,
>   		  u32 width, u32 height, u32 src_stride, u32 dst_stride)
> @@ -349,12 +359,19 @@ void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
>   int intel_plane_pin_fb(struct intel_plane_state *plane_state)
>   {
>   	struct drm_framebuffer *fb = plane_state->hw.fb;
> +	struct xe_device *xe = to_xe_device(to_intel_framebuffer(fb)->base.dev);
>   	struct xe_bo *bo = intel_fb_obj(fb);
>   	struct i915_vma *vma;
>   
>   	/* We reject creating !SCANOUT fb's, so this is weird.. */
>   	drm_WARN_ON(bo->ttm.base.dev, !(bo->flags & XE_BO_SCANOUT_BIT));
>   
> +	if (GRAPHICS_VER(xe) >= 20 && fb->modifier != I915_FORMAT_MOD_4_TILED &&
> +	    is_compressed(fb)) {
> +		drm_warn(&xe->drm, "Cannot create ccs framebuffer with other than tile4 mofifier\n");
> +		return -EINVAL;
> +	}
> +
>   	vma = __xe_pin_fb_vma(to_intel_framebuffer(fb), &plane_state->view.gtt);
>   	if (IS_ERR(vma))
>   		return PTR_ERR(vma);