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Downgrade all the errors to non-fatal to prevent PCIe >> bus driver from triggering a Secondary Bus Reset (SBR). This allows error >> detection, containment and recovery in the driver. >> >> The Uncorrectable Error Severity Register has the 'Uncorrectable >> Internal Error Severity' set to fatal by default. Set this to >> non-fatal and unmask the error. >> >> Signed-off-by: Riana Tauro >> --- >> v2: clear stale uncorrectable internal status in status register >> (Aravind) >> >> v3: Abbrevate TLA's (Raag) >> Add a info message if USP does not support AER >> --- >> drivers/gpu/drm/xe/Makefile | 1 + >> drivers/gpu/drm/xe/xe_device.c | 3 ++ >> drivers/gpu/drm/xe/xe_ras.c | 84 ++++++++++++++++++++++++++++++++++ >> drivers/gpu/drm/xe/xe_ras.h | 13 ++++++ >> 4 files changed, 101 insertions(+) >> create mode 100644 drivers/gpu/drm/xe/xe_ras.c >> create mode 100644 drivers/gpu/drm/xe/xe_ras.h >> >> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile >> index 69c233d9a488..e29a4ae99ac6 100644 >> --- a/drivers/gpu/drm/xe/Makefile >> +++ b/drivers/gpu/drm/xe/Makefile >> @@ -113,6 +113,7 @@ xe-y += xe_bb.o \ >> xe_pxp_debugfs.o \ >> xe_pxp_submit.o \ >> xe_query.o \ >> + xe_ras.o \ >> xe_range_fence.o \ >> xe_reg_sr.o \ >> xe_reg_whitelist.o \ >> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c >> index cbdf7426e09c..c1c54836ac73 100644 >> --- a/drivers/gpu/drm/xe/xe_device.c >> +++ b/drivers/gpu/drm/xe/xe_device.c >> @@ -62,6 +62,7 @@ >> #include "xe_psmi.h" >> #include "xe_pxp.h" >> #include "xe_query.h" >> +#include "xe_ras.h" >> #include "xe_shrinker.h" >> #include "xe_soc_remapper.h" >> #include "xe_survivability_mode.h" >> @@ -1074,6 +1075,8 @@ int xe_device_probe(struct xe_device *xe) >> >> xe_vsec_init(xe); >> >> + xe_ras_init(xe); >> + >> err = xe_sriov_init_late(xe); >> if (err) >> goto err_unregister_display; >> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c >> new file mode 100644 >> index 000000000000..4f705deaeefa >> --- /dev/null >> +++ b/drivers/gpu/drm/xe/xe_ras.c >> @@ -0,0 +1,84 @@ >> +// SPDX-License-Identifier: MIT >> +/* >> + * Copyright © 2026 Intel Corporation >> + */ >> + >> +#include "xe_device_types.h" >> +#include "xe_ras.h" >> + >> +#ifdef CONFIG_PCIEAER >> +static void aer_unmask_and_downgrade_internal_error(struct xe_device *xe) >> +{ >> + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); >> + struct pci_dev *vsp, *usp; >> + u32 aer_uncorr_mask, aer_uncorr_sev, aer_uncorr_status; >> + u16 aer_cap; >> + >> + /* >> + * Device Hierarchy: >> + * >> + * Upstream Switch Port (USP)--> Virtual Switch Port (VSP)--> SGunit (GPU endpoint) >> + */ >> + vsp = pci_upstream_bridge(pdev); >> + if (!vsp) >> + return; >> + >> + usp = pci_upstream_bridge(vsp); >> + if (!usp) >> + return; >> + >> + aer_cap = usp->aer_cap; >> + >> + if (!aer_cap) { >> + dev_info(&usp->dev, "USP doesn't support AER capability\n"); >> + return; >> + } >> + >> + /* >> + * Clear any stale Uncorrectable Internal Error Status event in Uncorrectable Error >> + * Status Register. >> + */ >> + pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_STATUS, &aer_uncorr_status); >> + if (aer_uncorr_status & PCI_ERR_UNC_INTN) >> + pci_write_config_dword(usp, aer_cap + PCI_ERR_UNCOR_STATUS, PCI_ERR_UNC_INTN); >> + >> + /* >> + * All errors are steered to USP which is a PCIe AER Compliant device. >> + * Downgrade all the errors to non-fatal to prevent PCIe bus driver >> + * from triggering a Secondary Bus Reset (SBR). This allows error >> + * detection, containment and recovery in the driver. >> + * >> + * The Uncorrectable Error Severity Register has the 'Uncorrectable >> + * Internal Error Severity' set to fatal by default. Set this to >> + * non-fatal and unmask the error. >> + */ >> + >> + /* Initialize Uncorrectable Error Severity Register */ >> + pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_SEVER, &aer_uncorr_sev); >> + aer_uncorr_sev &= ~PCI_ERR_UNC_INTN; >> + pci_write_config_dword(usp, aer_cap + PCI_ERR_UNCOR_SEVER, aer_uncorr_sev); >> + >> + /* Initialize Uncorrectable Error Mask Register */ >> + pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_MASK, &aer_uncorr_mask); >> + aer_uncorr_mask &= ~PCI_ERR_UNC_INTN; >> + pci_write_config_dword(usp, aer_cap + PCI_ERR_UNCOR_MASK, aer_uncorr_mask); >> + >> + pci_save_state(usp); >> +} >> +#endif >> + >> +/** >> + * xe_ras_init - Initialize Xe RAS >> + * @xe: xe device instance >> + * >> + * Initialize Xe RAS >> + */ >> +void xe_ras_init(struct xe_device *xe) >> +{ >> + if (!xe->info.has_sysctrl) >> + return; >> + >> +#ifdef CONFIG_PCIEAER >> + aer_unmask_and_downgrade_internal_error(xe); > If we fail silently we'd most likely be clueless why RAS isn't working. > So either add error log here or have an explicit success log inside > downgrade function. We already have a log if AER is not supported.  Handling ret for pci_write/read is unnecessary. This fails only when device is disconnected or there is something wrong with the device. yeah i can add a debug success log. Thanks Riana > > Raag > >> +#endif >> +} >> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h >> new file mode 100644 >> index 000000000000..14cb973603e7 >> --- /dev/null >> +++ b/drivers/gpu/drm/xe/xe_ras.h >> @@ -0,0 +1,13 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * Copyright © 2026 Intel Corporation >> + */ >> + >> +#ifndef _XE_RAS_H_ >> +#define _XE_RAS_H_ >> + >> +struct xe_device; >> + >> +void xe_ras_init(struct xe_device *xe); >> + >> +#endif >> -- >> 2.47.1 >>