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d="scan'208";a="200679055" Received: from mwiniars-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.154]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2025 03:00:52 -0800 From: Jani Nikula To: Ville Syrjala , intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: Re: [PATCH 18/19] drm/i915: Clean up PCI config space reg defines In-Reply-To: <20251208182637.334-19-ville.syrjala@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251208182637.334-1-ville.syrjala@linux.intel.com> <20251208182637.334-19-ville.syrjala@linux.intel.com> Date: Tue, 09 Dec 2025 13:00:49 +0200 Message-ID: <648563e277208801e5ca4b700aea4329483ad3dd@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Mon, 08 Dec 2025, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > The PCI config space register defines in i915_drm.h are > a bit of a mess; Whitespace is all over the place, register > masks and values are defined in inconsitent ways. > > Clean it up a bit. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > include/drm/intel/i915_drm.h | 70 ++++++++++++++++++------------------ > 1 file changed, 34 insertions(+), 36 deletions(-) > > diff --git a/include/drm/intel/i915_drm.h b/include/drm/intel/i915_drm.h > index 91f628367f1f..c633ce62f2bf 100644 > --- a/include/drm/intel/i915_drm.h > +++ b/include/drm/intel/i915_drm.h > @@ -45,38 +45,36 @@ extern struct resource intel_graphics_stolen_res; > * cares about the vga bit for the vga arbiter. > */ > #define SNB_GMCH_CTRL 0x50 > -#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ > -#define SNB_GMCH_GGMS_MASK 0x3 > -#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ > -#define SNB_GMCH_GMS_MASK 0x1f > -#define BDW_GMCH_GGMS_SHIFT 6 > -#define BDW_GMCH_GGMS_MASK 0x3 > -#define BDW_GMCH_GMS_SHIFT 8 > -#define BDW_GMCH_GMS_MASK 0xff > +#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ > +#define SNB_GMCH_GGMS_MASK 0x3 > +#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ > +#define SNB_GMCH_GMS_MASK 0x1f > +#define BDW_GMCH_GGMS_SHIFT 6 > +#define BDW_GMCH_GGMS_MASK 0x3 > +#define BDW_GMCH_GMS_SHIFT 8 > +#define BDW_GMCH_GMS_MASK 0xff >=20=20 > #define I830_GMCH_CTRL 0x52 > - > -#define I830_GMCH_GMS_MASK 0x70 > -#define I830_GMCH_GMS_LOCAL 0x10 > -#define I830_GMCH_GMS_STOLEN_512 0x20 > -#define I830_GMCH_GMS_STOLEN_1024 0x30 > -#define I830_GMCH_GMS_STOLEN_8192 0x40 > - > -#define I855_GMCH_GMS_MASK 0xF0 > -#define I855_GMCH_GMS_STOLEN_0M 0x0 > -#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) > -#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) > -#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) > -#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) > -#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) > -#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) > -#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) > -#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) > -#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) > -#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) > -#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) > -#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) > -#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) > +#define I830_GMCH_GMS_MASK (0x7 << 4) > +#define I830_GMCH_GMS_LOCAL (0x1 << 4) > +#define I830_GMCH_GMS_STOLEN_512 (0x2 << 4) > +#define I830_GMCH_GMS_STOLEN_1024 (0x3 << 4) > +#define I830_GMCH_GMS_STOLEN_8192 (0x4 << 4) > +#define I855_GMCH_GMS_MASK (0xF << 4) > +#define I855_GMCH_GMS_STOLEN_0M (0x0 << 4) > +#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) > +#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) > +#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) > +#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) > +#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) > +#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) > +#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) > +#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) > +#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) > +#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) > +#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) > +#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) > +#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) >=20=20 > /* valid for both I830_GMCH_CTRL and SNB_GMCH_CTRL */ > #define INTEL_GMCH_VGA_DISABLE (1 << 1) > @@ -88,12 +86,12 @@ extern struct resource intel_graphics_stolen_res; > #define I830_ESMRAMC 0x91 > #define I845_ESMRAMC 0x9e > #define I85X_ESMRAMC 0x61 > -#define TSEG_ENABLE (1 << 0) > -#define I830_TSEG_SIZE_512K (0 << 1) > -#define I830_TSEG_SIZE_1M (1 << 1) > -#define I845_TSEG_SIZE_MASK (3 << 1) > -#define I845_TSEG_SIZE_512K (2 << 1) > -#define I845_TSEG_SIZE_1M (3 << 1) > +#define TSEG_ENABLE (1 << 0) > +#define I830_TSEG_SIZE_512K (0 << 1) > +#define I830_TSEG_SIZE_1M (1 << 1) > +#define I845_TSEG_SIZE_MASK (3 << 1) > +#define I845_TSEG_SIZE_512K (2 << 1) > +#define I845_TSEG_SIZE_1M (3 << 1) >=20=20 > #define INTEL_BSM 0x5c > #define INTEL_GEN11_BSM_DW0 0xc0 --=20 Jani Nikula, Intel