Re: [PATCH 3/3] drm/xe/xe2: Add performance tuning for L3 cache flushing

["Pottumuttu, Sai Teja" <sai.teja.pottumuttu@intel.com>]

On 19-09-2024 02:17, Gustavo Sousa wrote:
> A recommended performance tuning for LNL related to L3 cache flushing
> was recently introduced in Bspec. Implement it.
>
> Bspec: 70821

The correct BSpec should be 72161 I guess.

> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>   drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++++
>   drivers/gpu/drm/xe/xe_tuning.c       | 8 ++++++++
>   2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 6ec2d2c11d77..ccd18cdd5b50 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -389,6 +389,9 @@
>   #define L3SQCREG3				XE_REG_MCR(0xb108)
>   #define   COMPPWOVERFETCHEN			REG_BIT(28)
>   
> +#define SCRATCH3LBCF				XE_REG_MCR(0xb154)
> +#define   RWFLUSHALLEN				REG_BIT(17)
> +
>   #define XEHP_L3SQCREG5				XE_REG_MCR(0xb158)
>   #define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)
>   
> @@ -406,6 +409,8 @@
>   
>   #define XE2LPM_L3SQCREG3			XE_REG_MCR(0xb608)
>   
> +#define XE2LPM_SCRATCH3LBCF			XE_REG_MCR(0xb654)

Just a general question, the register might exist on other platforms as 
well right, so,

would it be a good idea to call it SCRATCH3LBCF_MEDIA instead?

> +
>   #define XE2LPM_L3SQCREG5			XE_REG_MCR(0xb658)
>   
>   #define XE2_TDF_CTRL				XE_REG(0xb418)
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index f62622f0be85..4dd77b44ac82 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -80,6 +80,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>   	  XE_RTP_ACTIONS(FIELD_SET(XELPMP_STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
>   				   REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
>   	},
> +	{ XE_RTP_NAME("Tuning: L3 RW flush all Cache"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2004, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_ACTIONS(SET(SCRATCH3, RWFLUSHALLEN))

The register should be SCRATCH3LBCF

Thank You

- Sai Teja

> +	},
> +	{ XE_RTP_NAME("Tuning: L3 RW flush all cache - media"),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3LBCF, RWFLUSHALLEN))
> +	},
>   	{}
>   };
>