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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from MN0PR11MB6011.namprd11.prod.outlook.com (2603:10b6:208:372::6) by SJ5PPFD56E32CC2.namprd11.prod.outlook.com (2603:10b6:a0f:fc02::859) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9412.10; Thu, 11 Dec 2025 18:20:37 +0000 Received: from MN0PR11MB6011.namprd11.prod.outlook.com ([fe80::bbbc:5368:4433:4267]) by MN0PR11MB6011.namprd11.prod.outlook.com ([fe80::bbbc:5368:4433:4267%5]) with mapi id 15.20.9388.013; Thu, 11 Dec 2025 18:20:36 +0000 Message-ID: <677fa545-802c-4e49-8334-d2138bd185fb@intel.com> Date: Thu, 11 Dec 2025 19:20:32 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 02/12] drm/gt/guc: extract scheduler-related defines from guc_fwif.h To: Daniele Ceraolo Spurio , References: <20251211015700.34266-14-daniele.ceraolospurio@intel.com> <20251211015700.34266-16-daniele.ceraolospurio@intel.com> Content-Language: en-US From: Michal Wajdeczko In-Reply-To: <20251211015700.34266-16-daniele.ceraolospurio@intel.com> Content-Type: text/plain; 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Note that the legacy GuC defines have not been moved and have > instead been dropped because Xe doesn't support any GuC old enough to > still use them. > > While at it, struct guc_ctxt_registration_info has been moved to > guc_submit.c since it doesn't come from the GuC specs (we added it to > make things simpler in our code). > > Signed-off-by: Daniele Ceraolo Spurio > Cc: Michal Wajdeczko Reviewed-by: Michal Wajdeczko with 2 nits below to be fixed later > --- > drivers/gpu/drm/xe/abi/guc_scheduler_abi.h | 48 ++++++++++++++++++++ > drivers/gpu/drm/xe/xe_guc_capture.h | 2 +- > drivers/gpu/drm/xe/xe_guc_fwif.h | 52 +--------------------- > drivers/gpu/drm/xe/xe_guc_submit.c | 15 +++++++ > 4 files changed, 65 insertions(+), 52 deletions(-) > create mode 100644 drivers/gpu/drm/xe/abi/guc_scheduler_abi.h > > diff --git a/drivers/gpu/drm/xe/abi/guc_scheduler_abi.h b/drivers/gpu/drm/xe/abi/guc_scheduler_abi.h > new file mode 100644 > index 000000000000..db9c171f8b64 > --- /dev/null > +++ b/drivers/gpu/drm/xe/abi/guc_scheduler_abi.h > @@ -0,0 +1,48 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2025 Intel Corporation > + */ > + > +#ifndef _ABI_GUC_SCHEDULER_ABI_H > +#define _ABI_GUC_SCHEDULER_ABI_H > + > +/** > + * Generic defines required for registration with and submissions to the GuC > + * scheduler. Includes engine class/instance defines and context attributes > + * (id, priority, etc) > + */ > + > +/* Engine classes/instances */ > +#define GUC_RENDER_CLASS 0 > +#define GUC_VIDEO_CLASS 1 > +#define GUC_VIDEOENHANCE_CLASS 2 > +#define GUC_BLITTER_CLASS 3 > +#define GUC_COMPUTE_CLASS 4 > +#define GUC_GSC_OTHER_CLASS 5 > +#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS > +#define GUC_MAX_ENGINE_CLASSES 16 > +#define GUC_MAX_INSTANCES_PER_CLASS 32 > + > +/* context priority values */ > +#define GUC_CLIENT_PRIORITY_KMD_HIGH 0 > +#define GUC_CLIENT_PRIORITY_HIGH 1 > +#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 > +#define GUC_CLIENT_PRIORITY_NORMAL 3 > +#define GUC_CLIENT_PRIORITY_NUM 4 > + > +/* Context registration */ > +#define GUC_ID_MAX 65535 > +#define GUC_ID_UNKNOWN 0xffffffff > + > +#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0) > +#define CONTEXT_REGISTRATION_FLAG_TYPE GENMASK(2, 1) nit: we might want to rename it by adding GUC_ prefix like all other defs > +#define GUC_CONTEXT_NORMAL 0 > +#define GUC_CONTEXT_COMPRESSION_SAVE 1 > +#define GUC_CONTEXT_COMPRESSION_RESTORE 2 > +#define GUC_CONTEXT_COUNT (GUC_CONTEXT_COMPRESSION_RESTORE + 1) nit: candidate to drop, the only use of it can be replaced with FIELD_FIT > + > +/* context enable/disable */ > +#define GUC_CONTEXT_DISABLE 0 > +#define GUC_CONTEXT_ENABLE 1 > + > +#endif > diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h > index 20a078dc4b85..34d6fdc64f56 100644 > --- a/drivers/gpu/drm/xe/xe_guc_capture.h > +++ b/drivers/gpu/drm/xe/xe_guc_capture.h > @@ -8,8 +8,8 @@ > > #include > #include "abi/guc_capture_abi.h" > +#include "abi/guc_scheduler_abi.h" > #include "xe_guc.h" > -#include "xe_guc_fwif.h" > > struct xe_exec_queue; > struct xe_guc; > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h > index 7d93c2749485..08149c8159c5 100644 > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h > @@ -10,6 +10,7 @@ > > #include "abi/guc_capture_abi.h" > #include "abi/guc_klvs_abi.h" > +#include "abi/guc_scheduler_abi.h" > #include "xe_hw_engine_types.h" > > #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 4 > @@ -17,57 +18,6 @@ > #define G2H_LEN_DW_TLB_INVALIDATE 3 > #define G2H_LEN_DW_G2G_NOTIFY_MIN 3 > > -#define GUC_ID_MAX 65535 > -#define GUC_ID_UNKNOWN 0xffffffff > - > -#define GUC_CONTEXT_DISABLE 0 > -#define GUC_CONTEXT_ENABLE 1 > - > -#define GUC_CLIENT_PRIORITY_KMD_HIGH 0 > -#define GUC_CLIENT_PRIORITY_HIGH 1 > -#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 > -#define GUC_CLIENT_PRIORITY_NORMAL 3 > -#define GUC_CLIENT_PRIORITY_NUM 4 > - > -#define GUC_RENDER_ENGINE 0 > -#define GUC_VIDEO_ENGINE 1 > -#define GUC_BLITTER_ENGINE 2 > -#define GUC_VIDEOENHANCE_ENGINE 3 > -#define GUC_VIDEO_ENGINE2 4 > -#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) > - > -#define GUC_RENDER_CLASS 0 > -#define GUC_VIDEO_CLASS 1 > -#define GUC_VIDEOENHANCE_CLASS 2 > -#define GUC_BLITTER_CLASS 3 > -#define GUC_COMPUTE_CLASS 4 > -#define GUC_GSC_OTHER_CLASS 5 > -#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS > -#define GUC_MAX_ENGINE_CLASSES 16 > -#define GUC_MAX_INSTANCES_PER_CLASS 32 > - > -#define GUC_CONTEXT_NORMAL 0 > -#define GUC_CONTEXT_COMPRESSION_SAVE 1 > -#define GUC_CONTEXT_COMPRESSION_RESTORE 2 > -#define GUC_CONTEXT_COUNT (GUC_CONTEXT_COMPRESSION_RESTORE + 1) > - > -/* Helper for context registration H2G */ > -struct guc_ctxt_registration_info { > - u32 flags; > - u32 context_idx; > - u32 engine_class; > - u32 engine_submit_mask; > - u32 wq_desc_lo; > - u32 wq_desc_hi; > - u32 wq_base_lo; > - u32 wq_base_hi; > - u32 wq_size; > - u32 hwlrca_lo; > - u32 hwlrca_hi; > -}; > -#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0) > -#define CONTEXT_REGISTRATION_FLAG_TYPE GENMASK(2, 1) > - > /* 32-bit KLV structure as used by policy updates and others */ > struct guc_klv_generic_dw_t { > u32 kl; > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c > index bf289c480cd2..0fd08d59b644 100644 > --- a/drivers/gpu/drm/xe/xe_guc_submit.c > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c > @@ -568,6 +568,21 @@ static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue > __guc_exec_queue_policy_action_size(&policy), 0, 0); > } > > +/* Helper for context registration H2G */ > +struct guc_ctxt_registration_info { > + u32 flags; > + u32 context_idx; > + u32 engine_class; > + u32 engine_submit_mask; > + u32 wq_desc_lo; > + u32 wq_desc_hi; > + u32 wq_base_lo; > + u32 wq_base_hi; > + u32 wq_size; > + u32 hwlrca_lo; > + u32 hwlrca_hi; > +}; > + > #define parallel_read(xe_, map_, field_) \ > xe_map_rd_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \ > field_)