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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH7PR11MB7605.namprd11.prod.outlook.com (2603:10b6:510:277::5) by CH3PR11MB8154.namprd11.prod.outlook.com (2603:10b6:610:15f::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9870.25; Mon, 4 May 2026 23:59:46 +0000 Received: from PH7PR11MB7605.namprd11.prod.outlook.com ([fe80::48d7:f2a6:b18:1b87]) by PH7PR11MB7605.namprd11.prod.outlook.com ([fe80::48d7:f2a6:b18:1b87%5]) with mapi id 15.20.9870.023; Mon, 4 May 2026 23:59:46 +0000 Message-ID: <68c4aad8-851e-48af-9a38-59039a123482@intel.com> Date: Mon, 4 May 2026 16:59:44 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/1] drm/xe/guc: Exclude indirect ring state page from ADS engine state size To: Satyanarayana K V P , CC: Michal Wajdeczko , Matthew Brost References: <20260504094924.3760713-3-satyanarayana.k.v.p@intel.com> <20260504094924.3760713-4-satyanarayana.k.v.p@intel.com> Content-Language: en-US From: Daniele Ceraolo Spurio In-Reply-To: <20260504094924.3760713-4-satyanarayana.k.v.p@intel.com> Content-Type: text/plain; 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The GuC uses this size to > overwrite the engine state in the LRC on watchdog resets and we don't > want it to overwrite the indirect ring state as well. > > Fixes: d6219e1cd5e3 ("drm/xe: Add Indirect Ring State support") > Suggested-by: Daniele Ceraolo Spurio > Signed-off-by: Satyanarayana K V P > Cc: Michal Wajdeczko > Cc: Matthew Brost Reviewed-by: Daniele Ceraolo Spurio Daniele > --- > V1 -> V2: > - Replaced xe_lrc_skip_size() with xe_lrc_engine_state_size(). > - Updated commit message (Daniel). > --- > drivers/gpu/drm/xe/xe_guc_ads.c | 5 +---- > drivers/gpu/drm/xe/xe_lrc.c | 11 +++++++++-- > drivers/gpu/drm/xe/xe_lrc.h | 2 +- > 3 files changed, 11 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c > index ce651da6f318..b9bca6084a4f 100644 > --- a/drivers/gpu/drm/xe/xe_guc_ads.c > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c > @@ -515,12 +515,9 @@ static void guc_golden_lrc_init(struct xe_guc_ads *ads) > * that starts after the execlists LRC registers. This is > * required to allow the GuC to restore just the engine state > * when a watchdog reset occurs. > - * We calculate the engine state size by removing the size of > - * what comes before it in the context image (which is identical > - * on all engines). > */ > ads_blob_write(ads, ads.eng_state_size[guc_class], > - real_size - xe_lrc_skip_size(xe)); > + xe_lrc_engine_state_size(gt, class)); > ads_blob_write(ads, ads.golden_context_lrca[guc_class], > addr_ggtt); > > diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c > index 9db914584347..fdfe2ed5f683 100644 > --- a/drivers/gpu/drm/xe/xe_lrc.c > +++ b/drivers/gpu/drm/xe/xe_lrc.c > @@ -727,9 +727,16 @@ size_t xe_lrc_reg_size(struct xe_device *xe) > return 80 * sizeof(u32); > } > > -size_t xe_lrc_skip_size(struct xe_device *xe) > +/** > + * xe_lrc_engine_state_size() - Get size of the engine state within LRC > + * @gt: the &xe_gt struct instance > + * @class: Hardware engine class > + * > + * Returns: Size of the engine state > + */ > +size_t xe_lrc_engine_state_size(struct xe_gt *gt, enum xe_engine_class class) > { > - return LRC_PPHWSP_SIZE + xe_lrc_reg_size(xe); > + return xe_gt_lrc_hang_replay_size(gt, class) - xe_lrc_reg_size(gt_to_xe(gt)); > } > > static inline u32 __xe_lrc_seqno_offset(struct xe_lrc *lrc) > diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h > index e7c975f9e2d9..5440663183f6 100644 > --- a/drivers/gpu/drm/xe/xe_lrc.h > +++ b/drivers/gpu/drm/xe/xe_lrc.h > @@ -130,7 +130,7 @@ u32 xe_lrc_parallel_ggtt_addr(struct xe_lrc *lrc); > struct iosys_map xe_lrc_parallel_map(struct xe_lrc *lrc); > > size_t xe_lrc_reg_size(struct xe_device *xe); > -size_t xe_lrc_skip_size(struct xe_device *xe); > +size_t xe_lrc_engine_state_size(struct xe_gt *gt, enum xe_engine_class class); > > void xe_lrc_dump_default(struct drm_printer *p, > struct xe_gt *gt,