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Currently we only log the errors in > dmesg but this serves as a foundation for RAS infrastructure and will > be further extended to facilitate other RAS features. > > Signed-off-by: Raag Jadav > --- > drivers/gpu/drm/xe/Makefile | 1 + > drivers/gpu/drm/xe/xe_ras.c | 87 +++++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_ras.h | 14 +++++ > drivers/gpu/drm/xe/xe_ras_types.h | 79 ++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +- > 5 files changed, 183 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/xe/xe_ras.c > create mode 100644 drivers/gpu/drm/xe/xe_ras.h > create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile > index 59e083f90d7e..7fc67c320086 100644 > --- a/drivers/gpu/drm/xe/Makefile > +++ b/drivers/gpu/drm/xe/Makefile > @@ -111,6 +111,7 @@ xe-y += xe_bb.o \ > xe_pxp_submit.o \ > xe_query.o \ > xe_range_fence.o \ > + xe_ras.o \ > xe_reg_sr.o \ > xe_reg_whitelist.o \ > xe_ring_ops.o \ > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c > new file mode 100644 > index 000000000000..413c6e62cd50 > --- /dev/null > +++ b/drivers/gpu/drm/xe/xe_ras.c > @@ -0,0 +1,87 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2026 Intel Corporation > + */ > + > +#include "xe_assert.h" > +#include "xe_printk.h" > +#include "xe_ras.h" > +#include "xe_ras_types.h" > +#include "xe_sysctrl_event_types.h" > + > +/* Severity of detected errors */ > +enum xe_ras_severity { > + XE_RAS_SEV_NOT_SUPPORTED = 0x00, > + XE_RAS_SEV_CORRECTABLE = 0x01, > + XE_RAS_SEV_UNCORRECTABLE = 0x02, > + XE_RAS_SEV_INFORMATIONAL = 0x03, > + XE_RAS_SEV_MAX > +}; > + > +/* Major IP blocks/components where errors can originate */ > +enum xe_ras_component { > + XE_RAS_COMP_NOT_SUPPORTED = 0x00, > + XE_RAS_COMP_DEVICE_MEMORY = 0x01, > + XE_RAS_COMP_CORE_COMPUTE = 0x02, > + XE_RAS_COMP_RESERVED = 0x03, > + XE_RAS_COMP_PCIE = 0x04, > + XE_RAS_COMP_FABRIC = 0x05, > + XE_RAS_COMP_SOC_INTERNAL = 0x06, > + XE_RAS_COMP_MAX > +}; > + > +static const char *const xe_ras_severities[] = { > + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported", > + [XE_RAS_SEV_CORRECTABLE] = "Correctable", > + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable", > + [XE_RAS_SEV_INFORMATIONAL] = "Informational", > +}; > +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX); > + > +static const char *const xe_ras_components[] = { > + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported", > + [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory", > + [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute", > + [XE_RAS_COMP_RESERVED] = "Reserved", > + [XE_RAS_COMP_PCIE] = "PCIe", > + [XE_RAS_COMP_FABRIC] = "Fabric", > + [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal", > +}; > +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX); > + > +static inline const char *sev_to_str(struct xe_device *xe, u32 sev) > +{ > + xe_assert(xe, sev < XE_RAS_SEV_MAX); > + > + return xe_ras_severities[sev]; > +} > + > +static inline const char *comp_to_str(struct xe_device *xe, u32 comp) > +{ > + xe_assert(xe, comp < XE_RAS_COMP_MAX); > + > + return xe_ras_components[comp]; > +} > + > +void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response) > +{ > + struct xe_ras_event_threshold_crossed *pending = (void *)&response->data; > + struct xe_ras_error *errors = pending->counters; > + u32 cid, sev, comp, inst, cause; > + u8 tile; > + > + xe_warn(xe, "[RAS]: error counter threshold crossed\n"); > + xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS); > + > + for (cid = 0; cid < pending->ncounters; cid++) { > + sev = errors[cid].common.severity; > + comp = errors[cid].common.component; > + > + tile = errors[cid].product.unit.tile; > + inst = errors[cid].product.unit.instance; > + cause = errors[cid].product.cause.cause; > + Unaligned access of member cause penalty, we need to check. > + xe_warn(xe, "[RAS]: Error:%s Tile:%u Component:%s Instance:%u Cause:%#x\n", > + sev_to_str(xe, sev), tile, comp_to_str(xe, comp), inst, cause); Spam kernel Log, we can use rate limit right? Thanks -/Mallesh > + } > +} > diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h > new file mode 100644 > index 000000000000..fdefe0e2fe98 > --- /dev/null > +++ b/drivers/gpu/drm/xe/xe_ras.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2026 Intel Corporation > + */ > + > +#ifndef _XE_RAS_H_ > +#define _XE_RAS_H_ > + > +struct xe_device; > +struct xe_sysctrl_event_response; > + > +void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response); > + > +#endif > diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h > new file mode 100644 > index 000000000000..0afcf8bf982d > --- /dev/null > +++ b/drivers/gpu/drm/xe/xe_ras_types.h > @@ -0,0 +1,79 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2026 Intel Corporation > + */ > + > +#ifndef _XE_RAS_TYPES_H_ > +#define _XE_RAS_TYPES_H_ > + > +#include > + > +#define XE_RAS_NUM_COUNTERS 21 > + > +/** > + * struct xe_ras_error_common - Error fields that are common across all products > + */ > +struct xe_ras_error_common { > + /** @severity: Error severity */ > + u8 severity; > + /** @component: IP block where error originated */ > + u8 component; > +} __packed; > + > +/** > + * struct xe_ras_error_unit - Error unit information > + */ > +struct xe_ras_error_unit { > + /** @tile: Tile identifier */ > + u8 tile; > + /** @instance: Instance identifier specific to IP */ > + u32 instance; > +} __packed; > + > +/** > + * struct xe_ras_error_cause - Error cause information > + */ > +struct xe_ras_error_cause { > + /** @cause: Cause/checker */ > + u32 cause; > + /** @reserved: For future use */ > + u8 reserved; > +} __packed; > + > +/** > + * struct xe_ras_error_product - Error fields that are specific to the product > + */ > +struct xe_ras_error_product { > + /** @unit: Unit within IP block */ > + struct xe_ras_error_unit unit; > + /** @cause: Cause/checker */ > + struct xe_ras_error_cause cause; > +} __packed; > + > +/** > + * struct xe_ras_error - Combines common and product-specific parts > + */ > +struct xe_ras_error { > + /** @common: Common error type and component */ > + struct xe_ras_error_common common; > + /** @product: Product-specific unit and cause */ > + struct xe_ras_error_product product; > +} __packed; > + > +/** > + * struct xe_ras_event_threshold_crossed - Event data for counter threshold crossed event > + */ > +struct xe_ras_event_threshold_crossed { > + /** @ncounters: Number of counters that crossed thresholds */ > + u32 ncounters; > + /** @ts_high: Higher 32 bits of event timestamp */ > + u32 ts_high; > + /** @ts_low: Lower 32 bits of event timestamp */ > + u32 ts_low; > + /** @reason: Threshold cross reason */ > + u32 reason; > + /** @counters: Array of error counters that crossed threshold */ > + struct xe_ras_error counters[XE_RAS_NUM_COUNTERS]; > +} __packed; > + > +#endif > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c > index 7c3041f4196a..876754f9fe35 100644 > --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c > @@ -7,6 +7,7 @@ > #include "xe_device.h" > #include "xe_irq.h" > #include "xe_printk.h" > +#include "xe_ras.h" > #include "xe_sysctrl.h" > #include "xe_sysctrl_event_types.h" > #include "xe_sysctrl_mailbox.h" > @@ -37,7 +38,7 @@ static void xe_sysctrl_get_pending_event(struct xe_device *xe, > } > > if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) { > - xe_warn(xe, "[RAS]: error counter threshold crossed\n"); > + xe_ras_event_log(xe, &response); > } else { > xe_err(xe, "sysctrl: unexpected event %#x\n", response.event); > return;