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d="scan'208";a="228346258" Received: from krybak-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.32]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2026 01:48:02 -0700 From: Jani Nikula To: Ville Syrjala , intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: Re: [PATCH 06/12] drm/xe/fb: Extract xe_dpt_size() In-Reply-To: <20260407155053.32156-7-ville.syrjala@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland References: <20260407155053.32156-1-ville.syrjala@linux.intel.com> <20260407155053.32156-7-ville.syrjala@linux.intel.com> Date: Wed, 08 Apr 2026 11:47:59 +0300 Message-ID: <6c2020b26cb953ee922a15710112a5afe7ef5927@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Tue, 07 Apr 2026, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Declutter the xe fb pinning code by extracting the DPT size > calculation into its own function. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/xe/display/xe_fb_pin.c | 30 +++++++++++++++----------- > 1 file changed, 18 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/= display/xe_fb_pin.c > index 72efafb189f7..9873904a950d 100644 > --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c > +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c > @@ -139,6 +139,22 @@ write_dpt_remapped(struct xe_bo *bo, > } > } >=20=20 > +static unsigned int xe_dpt_size(struct drm_gem_object *obj, > + const struct i915_gtt_view *view) > +{ > + unsigned int pages; > + int pte_size =3D 8; > + > + if (view->type =3D=3D I915_GTT_VIEW_NORMAL) > + pages =3D obj->size / XE_PAGE_SIZE; > + else if (view->type =3D=3D I915_GTT_VIEW_REMAPPED) > + pages =3D intel_remapped_info_size(&view->remapped); > + else > + pages =3D intel_rotation_info_size(&view->rotated); > + > + return ALIGN(pages * pte_size, XE_PAGE_SIZE); > +} > + > static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb, > const struct i915_gtt_view *view, > struct i915_vma *vma, > @@ -149,17 +165,7 @@ static int __xe_pin_fb_vma_dpt(const struct intel_fr= amebuffer *fb, > struct xe_ggtt *ggtt =3D tile0->mem.ggtt; > struct drm_gem_object *obj =3D intel_fb_bo(&fb->base); > struct xe_bo *bo =3D gem_to_xe_bo(obj), *dpt; > - u32 dpt_size, size =3D bo->ttm.base.size; > - > - if (view->type =3D=3D I915_GTT_VIEW_NORMAL) > - dpt_size =3D ALIGN(size / XE_PAGE_SIZE * 8, XE_PAGE_SIZE); > - else if (view->type =3D=3D I915_GTT_VIEW_REMAPPED) > - dpt_size =3D ALIGN(intel_remapped_info_size(&view->remapped) * 8, > - XE_PAGE_SIZE); > - else > - /* display uses 4K tiles instead of bytes here, convert to entries.. */ > - dpt_size =3D ALIGN(intel_rotation_info_size(&view->rotated) * 8, > - XE_PAGE_SIZE); > + u32 dpt_size =3D xe_dpt_size(obj, view); >=20=20 > if (IS_DGFX(xe)) > dpt =3D xe_bo_create_pin_map_at_novm(xe, tile0, > @@ -193,7 +199,7 @@ static int __xe_pin_fb_vma_dpt(const struct intel_fra= mebuffer *fb, > u64 pte =3D xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NO= NE]); > u32 x; >=20=20 > - for (x =3D 0; x < size / XE_PAGE_SIZE; x++) { > + for (x =3D 0; x < obj->size / XE_PAGE_SIZE; x++) { > u64 addr =3D xe_bo_addr(bo, x * XE_PAGE_SIZE, XE_PAGE_SIZE); >=20=20 > iosys_map_wr(&dpt->vmap, x * 8, u64, pte | addr); --=20 Jani Nikula, Intel