Re: [PATCH] drm/i915/dp: Don't use DP link min bpp for the FRL link bandwidth check

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 4/8/2026 12:00 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_dp_mode_min_link_bpp_x16() gives us the min bpp for the
> DP link before the PCON, however intel_dp_mode_valid_downstream()
> is trying to check for sufficient bandwidth on the HDMI FRL link
> after the PCON. So the use of intel_dp_mode_min_link_bpp_x16() here
> is incorrect.
>
> Presumably even with FRL HDMI still can't go below 8bpc, so we should

Thats right, even with HDMI2.1 FRL the minimum uncompressed bpc is 8.

Thanks for catching this issue.

Patch LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>



> just use that to give us the minimum required FRL bandwidth. And this
> needs to account for the sink format (for 4:2:0 sub-sampling) since
> that is what will be flowing over the HDMI link.
>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c | 20 ++++++++++++++------
>   1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4955bd8b11d7..31e9b2758499 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1317,6 +1317,15 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
>   	return MODE_OK;
>   }
>   
> +static int frl_required_bw(int clock, int bpc,
> +			   enum intel_output_format sink_format)
> +{
> +	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +		clock /= 2;
> +
> +	return clock * bpc * 3;
> +}
> +
>   static enum drm_mode_status
>   intel_dp_mode_valid_downstream(struct intel_connector *connector,
>   			       const struct drm_display_mode *mode,
> @@ -1327,13 +1336,14 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
>   	enum drm_mode_status status;
>   	enum intel_output_format sink_format;
>   
> +	sink_format = intel_dp_sink_format(connector, mode);
> +
>   	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
>   	if (intel_dp->dfp.pcon_max_frl_bw) {
> -		int link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode);
> -		int target_bw;
> -		int max_frl_bw;
> +		int target_bw, max_frl_bw;
>   
> -		target_bw = fxp_q4_to_int_roundup(link_bpp_x16) * target_clock;
> +		/* Assume 8bpc for the FRL bandwidth check */
> +		target_bw = frl_required_bw(target_clock, 8, sink_format);
>   
>   		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
>   
> @@ -1350,8 +1360,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
>   	    target_clock > intel_dp->dfp.max_dotclock)
>   		return MODE_CLOCK_HIGH;
>   
> -	sink_format = intel_dp_sink_format(connector, mode);
> -
>   	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
>   	status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
>   					   8, sink_format, true);