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SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On 11/4/2026 8:54 AM, Arun R Murthy wrote: > Add the definitions of the registers of the DP link layer (LL) symbol > based timing generator. > > v3: change MMIO -> MMIO_TRANS2 (Suraj) > > Bspec: 68849, 68922, 69961 nit: The registers this patch defines are on 74606 (TRANS_LLSYM_HTOTAL), 74607 (TRANS_LLSYM_CHUNK_SIZE), 74609 (TRANS_LLSYM_HACT), 74747/74748 (DP_LLSYM_DATAM/N) and 76160/76161 (_EXT). Add those; keep 69961 for TRANSCONF. > Signed-off-by: Arun R Murthy > Reviewed-by: Suraj Kandpal > --- > drivers/gpu/drm/i915/display/intel_display_regs.h | 38 +++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h > index bbdbc27629d7104c1f80baad44e710872214d42b..1a7badeb327977916c85ce88327ec496623d787b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -879,6 +879,7 @@ > #define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ > #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ > #define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ > +#define TRANSCONF_DP_SYMBOL_TG_ENABLE REG_BIT(28) /* xe3p+ */ > #define TRANSCONF_PIPE_LOCKED REG_BIT(25) > #define TRANSCONF_FORCE_BORDER REG_BIT(25) > #define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ > @@ -930,6 +931,7 @@ > #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3) > #define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0) > #define TRANSCONF_PIXEL_COUNT_SCALING_X4 1 > +#define TRANSCONF_PIXEL_COUNT_SCALING_X1 3 /* xe3p+ */ > > #define _PIPEASTAT 0x70024 > #define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) > @@ -2332,6 +2334,42 @@ > #define _DP_MIN_HBLANK_CTL_B 0x610ac > #define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans, _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B) > > +/* DP link layer (LL) symbol based timing generator, display version 35+ */ > +#define _TRANS_LLSYM_HACT_A 0x600dc > +#define TRANS_LLSYM_HACT(display, trans) \ > + _MMIO_TRANS2(display, trans, _TRANS_LLSYM_HACT_A) > +#define TRANS_LLSYM_HACT_MASK REG_GENMASK(14, 0) > +#define TRANS_LLSYM_HACT_VAL(x) REG_FIELD_PREP(TRANS_LLSYM_HACT_MASK, (x)) > + > +#define _TRANS_LLSYM_HTOTAL_A 0x600e0 > +#define TRANS_LLSYM_HTOTAL(display, trans) \ > + _MMIO_TRANS2(display, trans, _TRANS_LLSYM_HTOTAL_A) > +#define TRANS_LLSYM_HTOTAL_MASK REG_GENMASK(14, 0) > +#define TRANS_LLSYM_HTOTAL_VAL(x) REG_FIELD_PREP(TRANS_LLSYM_HTOTAL_MASK, (x)) > + > +#define _TRANS_LLSYM_CHUNK_SIZE_A 0x600e4 > +#define TRANS_LLSYM_CHUNK_SIZE(display, trans) \ > + _MMIO_TRANS2(display, trans, _TRANS_LLSYM_CHUNK_SIZE_A) > +#define TRANS_LLSYM_CHUNK_SIZE_MASK REG_GENMASK(11, 0) > +#define TRANS_LLSYM_CHUNK_SIZE_VAL(x) REG_FIELD_PREP(TRANS_LLSYM_CHUNK_SIZE_MASK, (x)) > + > +/* Data M/N value DW0/DW1 at the base offset, DW2/DW3 in the _EXT register */ > +#define _DP_LLSYM_DATAM_A 0x60024 > +#define DP_LLSYM_DATAM(display, trans, dw) \ > + _MMIO_TRANS2(display, trans, _DP_LLSYM_DATAM_A + (dw) * 4) > + > +#define _DP_LLSYM_DATAN_A 0x60038 > +#define DP_LLSYM_DATAN(display, trans, dw) \ > + _MMIO_TRANS2(display, trans, _DP_LLSYM_DATAN_A + (dw) * 4) > + > +#define _DP_LLSYM_DATAM_EXT_A 0x60470 > +#define DP_LLSYM_DATAM_EXT(display, trans, dw) \ > + _MMIO_TRANS2(display, trans, _DP_LLSYM_DATAM_EXT_A + (dw) * 4) > + > +#define _DP_LLSYM_DATAN_EXT_A 0x60478 > +#define DP_LLSYM_DATAN_EXT(display, trans, dw) \ > + _MMIO_TRANS2(display, trans, _DP_LLSYM_DATAN_EXT_A + (dw) * 4) > + > /* SNB eDP training params */ > /* SNB A-stepping */ > #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) >