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These values are normalized by taking the > sum of all values and then dividing each value with a sum. > > v2: Fix ifndef header naming issue reported by kernel test robot > v3: Rename file name[Arun] > Replace array size number with macro[Arun] > v4: Correct the register format[Jani] > Add brief comment and expalin about file[Jani] > Remove coefficient value from crtc_state[Jani] > v5: Fix build issue > v6: Add new function for writing coefficients[Ankit] > > Signed-off-by: Nemesa Garg > Reviewed-by: Naga Venkata Srikanth V > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/display/intel_casf.c | 142 ++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_casf.h | 16 ++ > .../gpu/drm/i915/display/intel_casf_regs.h | 19 +++ > drivers/gpu/drm/i915/display/intel_display.c | 3 + > .../drm/i915/display/intel_display_types.h | 13 ++ > drivers/gpu/drm/xe/Makefile | 1 + > 7 files changed, 195 insertions(+) > create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c > create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h > create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 3dda9f0eda82..6f7f47af894e 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -286,6 +286,7 @@ i915-y += \ > display/intel_pmdemand.o \ > display/intel_psr.o \ > display/intel_quirks.o \ > + display/intel_casf.o \ > display/intel_sprite.o \ > display/intel_sprite_uapi.o \ > display/intel_tc.o \ > diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c > new file mode 100644 > index 000000000000..b507401457bf > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_casf.c > @@ -0,0 +1,142 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2024 Intel Corporation Update to 2025 > + * > + */ > +#include "i915_reg.h" > +#include "intel_de.h" > +#include "intel_display_types.h" > +#include "intel_casf.h" > +#include "intel_casf_regs.h" > +#include "skl_scaler.h" > + > +#define FILTER_COEFF_0_125 125 > +#define FILTER_COEFF_0_25 250 > +#define FILTER_COEFF_0_5 500 > +#define FILTER_COEFF_1_0 1000 > +#define FILTER_COEFF_0_0 0 > +#define SET_POSITIVE_SIGN(x) ((x) & (~SIGN)) > + > +/** > + * DOC: Content Adaptive Sharpness Filter (CASF) > + * > + * From LNL onwards the display engine based adaptive > + * sharpening filter is supported. This helps in > + * improving the image quality. The display hardware > + * uses one of the pipe scaler for implementing casf. > + * It works on a region of pixels depending on the > + * tap size. The coefficients are used to generate an > + * alpha value which is used to blend the sharpened image > + * to original image. > + */ > + > +const u16 filtercoeff_1[] = { > + FILTER_COEFF_0_0, FILTER_COEFF_0_0, FILTER_COEFF_0_5, Indentation seems to off. Use just one tab. > + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0, > + FILTER_COEFF_0_0, > + }; Align the closing braces with the start of the line. > + > +const u16 filtercoeff_2[] = { > + FILTER_COEFF_0_0, FILTER_COEFF_0_25, FILTER_COEFF_0_5, > + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, > + FILTER_COEFF_0_0, > + }; > + > +const u16 filtercoeff_3[] = { > + FILTER_COEFF_0_125, FILTER_COEFF_0_25, FILTER_COEFF_0_5, > + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, > + FILTER_COEFF_0_125, > + }; > + > +static int casf_coef_tap(int i) > +{ > + return i % 7; Should this be SCALER_FILTER_NUM_TAPS? > +} > + > +static u16 casf_coef(struct intel_crtc_state *crtc_state, int t) IMO consistently using coeff would be better. Currently coef and coeff are mixed. > +{ > + struct scaler_filter_coeff value; > + u16 coeff; > + > + value = crtc_state->hw.casf_params.coeff[t]; > + coeff = SET_POSITIVE_SIGN(0) | EXPONENT(value.exp) | MANTISSA(value.mantissa); > + > + return coeff; > +} > + > +static void intel_casf_write_coeff(struct intel_crtc_state *crtc_state) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + int id = crtc_state->scaler_state.scaler_id; I think we should have a check that id is 1 (for second scaler) if not flag error and return. > + int i; > + > + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0), > + PS_COEF_INDEX_AUTO_INC); > + > + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 1), > + PS_COEF_INDEX_AUTO_INC); > + > + for (i = 0; i < 17 * 7; i += 2) { I think we should add comment about the reasoning. If I understand correctly there are total 17 phase of 7 taps that require 119 coefficients in 60 Dwords per set. Which filter coefficients to be used, depends on window size, that itself depends on the resolution. > + u32 tmp; > + int t; > + > + t = casf_coef_tap(i); > + tmp = casf_coef(crtc_state, t); > + > + t = casf_coef_tap(i + 1); > + tmp |= casf_coef(crtc_state, t) << 16; > + > + intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0), > + tmp); > + intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 1), > + tmp); > + } > +} > + > +void intel_casf_enable(struct intel_crtc_state *crtc_state) > +{ > + intel_casf_write_coeff(crtc_state); > +} > + > +static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, > + u16 coefficient) > +{ > + if (coefficient < 25) { > + coeff->mantissa = (coefficient * 2048) / 100; > + coeff->exp = 3; > + } else if (coefficient < 50) { > + coeff->mantissa = (coefficient * 1024) / 100; > + coeff->exp = 2; > + } else if (coefficient < 100) { > + coeff->mantissa = (coefficient * 512) / 100; > + coeff->exp = 1; > + } else { > + coeff->mantissa = (coefficient * 256) / 100; > + coeff->exp = 0; > + } > +} > + > +void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state) > +{ > + const u16 *filtercoeff; > + u16 filter_coeff[SCALER_FILTER_NUM_TAPS]; > + u16 sumcoeff = 0; > + u8 i; > + > + if (crtc_state->hw.casf_params.win_size == 0) > + filtercoeff = filtercoeff_1; > + else if (crtc_state->hw.casf_params.win_size == 1) > + filtercoeff = filtercoeff_2; > + else > + filtercoeff = filtercoeff_3; > + > + for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) > + sumcoeff += *(filtercoeff + i); > + > + for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) { > + filter_coeff[i] = (*(filtercoeff + i) * 100 / sumcoeff); > + convert_sharpness_coef_binary(&crtc_state->hw.casf_params.coeff[i], > + filter_coeff[i]); > + } > +} > diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h > new file mode 100644 > index 000000000000..8e0b67a2fd99 > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_casf.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2024 Intel Corporation > + */ > + > +#ifndef __INTEL_CASF_H__ > +#define __INTEL_CASF_H__ > + > +#include > + > +struct intel_crtc_state; > + > +void intel_casf_enable(struct intel_crtc_state *crtc_state); > +void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); > + > +#endif /* __INTEL_CASF_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h > new file mode 100644 > index 000000000000..0b3fcdb22c0c > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2024 Intel Corporation > + */ > + > +#ifndef __INTEL_CASF_REGS_H__ > +#define __INTEL_CASF_REGS_H__ > + > +#include "intel_display_reg_defs.h" > + > +/* Scaler Coefficient structure */ > +#define SIGN REG_BIT(15) > +#define EXPONENT_MASK REG_GENMASK(13, 12) > +#define EXPONENT(x) REG_FIELD_PREP(EXPONENT_MASK, (x)) > +#define MANTISSA_MASK REG_GENMASK(11, 3) > +#define MANTISSA(x) REG_FIELD_PREP(MANTISSA_MASK, (x)) > + > +#endif /* __INTEL_CASF_REGS__ */ > + > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 4271da219b41..413b7fd7e287 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -111,6 +111,7 @@ > #include "intel_psr.h" > #include "intel_psr_regs.h" > #include "intel_sdvo.h" > +#include "intel_casf.h" > #include "intel_snps_phy.h" > #include "intel_tc.h" > #include "intel_tdf.h" > @@ -6176,6 +6177,8 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) > if (ret) > return ret; > > + intel_casf_scaler_compute_config(new_crtc_state); > + This is added here and then removed later. What you perhaps want to do is have intel_casf_compute_config() here and call this inside. > /* > * On some platforms the number of active planes affects > * the planes' minimum cdclk calculation. Add such planes > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 8271e50e3644..7cb58bf56907 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -929,6 +929,18 @@ struct intel_csc_matrix { > u16 postoff[3]; > }; > > +struct scaler_filter_coeff { > + u16 sign; > + u16 exp; > + u16 mantissa; > +}; > + > +struct intel_casf { > +#define SCALER_FILTER_NUM_TAPS 7 > + struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS]; > + u8 win_size; > +}; > + > void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); > > typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val); > @@ -969,6 +981,7 @@ struct intel_crtc_state { > struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; > struct drm_display_mode mode, pipe_mode, adjusted_mode; > enum drm_scaling_filter scaling_filter; > + struct intel_casf casf_params; > } hw; > > /* actual state of LUTs */ > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile > index 5c97ad6ed738..fca8cdb70ce6 100644 > --- a/drivers/gpu/drm/xe/Makefile > +++ b/drivers/gpu/drm/xe/Makefile > @@ -262,6 +262,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ > i915-display/intel_psr.o \ > i915-display/intel_qp_tables.o \ > i915-display/intel_quirks.o \ > + i915-display/intel_casf.o \ Maintain alphabetical order Regards, Ankit > i915-display/intel_snps_phy.o \ > i915-display/intel_tc.o \ > i915-display/intel_vblank.o \