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From: "Poosa, Karthik" <karthik.poosa@intel.com>
To: <sashiko-reviews@lists.linux.dev>
Cc: <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v2 3/5] drm/xe/hwmon: Correct group selection for memory controller temperature
Date: Thu, 10 Sep 2026 22:30:22 +0530	[thread overview]
Message-ID: <835e584f-11a1-4411-8768-e6d530af89b5@intel.com> (raw)
In-Reply-To: <20260902181800.169391F00A3E@smtp.kernel.org>


On 02-09-2026 23:47, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>
> Pre-existing issues:
> - [High] Unaligned memory access due to misaligned pointer cast.
> --
>
> commit bce6aebc01fe7736c7ce377f855345b461ab89e3
> Author: Karthik Poosa <karthik.poosa@intel.com>
>
> drm/xe/hwmon: Correct group selection for memory controller temperature
>      
> Read all the necessary groups when reading memory controller
> temperature in get_mc_temp().
>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index 51a6664eec485..3a675d7b6758b 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> [ ... ]
>> @@ -883,7 +883,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>>   	int ret, i, count = 0;
>>   	s32 average = 0;
>>   
>> -	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
>> +	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
>>   		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
>>   				    (dword + i), NULL);
> [Severity: High]
> This is a pre-existing issue, but does this code create an unaligned memory
> access?
>
> In get_mc_temp(), the variable dword is initialized as:
>
>      u32 *dword = (u32 *)hwmon->temp.value;
>
> Since the value array is located at offset 10 in struct
> xe_hwmon_thermal_info, this cast creates a misaligned 32-bit pointer.
>
> When (dword + i) is passed to xe_pcode_read(), an unaligned 32-bit store
> occurs. On strict-alignment architectures, this could cause an alignment
> fault and kernel panic.
>
> Because the temp1_input sysfs attribute is world-readable, could this allow
> an unprivileged local user to trigger a denial of service?
This shall be addressed in next revision
>>   		if (ret)

  reply	other threads:[~2026-09-10 17:00 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-02 17:55 [PATCH v2 0/5] drm/xe/hwmon: Update hwmon thermal mailbox handling Karthik Poosa
2026-09-02 17:55 ` [PATCH v2 1/5] drm/xe/hwmon: Detect unavailable temperature sensors Karthik Poosa
2026-09-02 17:55 ` [PATCH v2 2/5] drm/xe/hwmon: Use VRAM temperature sensor count from thermal config on CRI Karthik Poosa
2026-09-02 18:10   ` sashiko-bot
2026-09-10 10:42     ` Poosa, Karthik
2026-09-02 18:43   ` Rodrigo Vivi
2026-09-10 11:33     ` Poosa, Karthik
2026-09-02 17:55 ` [PATCH v2 3/5] drm/xe/hwmon: Correct group selection for memory controller temperature Karthik Poosa
2026-09-02 18:17   ` sashiko-bot
2026-09-10 17:00     ` Poosa, Karthik [this message]
2026-09-02 17:55 ` [PATCH v2 4/5] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754 Karthik Poosa
2026-09-02 18:08   ` sashiko-bot
2026-09-10 17:05     ` Poosa, Karthik
2026-09-02 17:55 ` [PATCH v2 5/5] drm/xe/hwmon: Disable memory controller and PCIe temperatures on CRI Karthik Poosa
2026-09-02 18:07   ` sashiko-bot
2026-09-03  6:11     ` Poosa, Karthik
2026-09-02 18:28 ` ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox handling (rev2) Patchwork
2026-09-02 19:22 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-09-03  9:37 ` ✗ Xe.CI.FULL: " Patchwork

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