From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1FA4D5B154 for ; Mon, 28 Oct 2024 20:48:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E84310E576; Mon, 28 Oct 2024 20:48:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="BKxNs4Nr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 850F210E576 for ; Mon, 28 Oct 2024 20:48:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730148498; x=1761684498; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=CkIRX3wmYSaNoKY/yhPAoKoNW1IhYZDETk6DjnorKVs=; b=BKxNs4NrjuF94nEnJY4Fot5F3of0XdGRIq3XNFsh+DNMyK7utL++CRNE /ec0R9Lbsfw5vfVqb810DxkH+lvM81tDL4KM2LFFjqg9Up3xiEMYkFTtL 24SpqO1QTitzlLUPt9m12u6q5HhfkBE86OmW26T8oZZT6L7mlyqpNcP8F QJ555Gw2aCUWUHuKwlBF/z5aGvm5aCSZNVLuy0jKkxeQ4t+8KECVTtnVQ 06Un4DMXbMzOeVNX5gHVK2U1D0iVi6TG4iG1vh3Q3/rYXK4bBG/xOJ8Ru mh4wpOTbf2mpQMPiThIuO2rXxNmcHPjF06IurnIJ86ZaO/00Yq+e03SaB A==; X-CSE-ConnectionGUID: bzoEd91WRf+GS11XEOGXdw== X-CSE-MsgGUID: PCQoZDvVQfKAqaQlRnW99A== X-IronPort-AV: E=McAfee;i="6700,10204,11239"; a="29222454" X-IronPort-AV: E=Sophos;i="6.11,240,1725346800"; d="scan'208";a="29222454" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2024 13:48:18 -0700 X-CSE-ConnectionGUID: FT/atqNETa+72c5574nalA== X-CSE-MsgGUID: saMWh9kfTb23Ez4mk3MFcw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,240,1725346800"; d="scan'208";a="85687039" Received: from orsosgc001.jf.intel.com (HELO orsosgc001.intel.com) ([10.165.21.142]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Oct 2024 13:48:17 -0700 Date: Mon, 28 Oct 2024 13:48:17 -0700 Message-ID: <857c9symwe.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa Cc: Jonathan Cavitt , intel-xe@lists.freedesktop.org, saurabhg.gupta@intel.com, alex.zuo@intel.com, john.c.harrison@intel.com, stable@vger.kernel.org Subject: Re: [PATCH v3] drm/xe/xe_guc_ads: save/restore OA registers In-Reply-To: References: <20241023200716.82624-1-jonathan.cavitt@intel.com> <854j4wtca7.wl-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-redhat-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Mon, 28 Oct 2024 13:38:29 -0700, Umesh Nerlige Ramappa wrote: > > On Mon, Oct 28, 2024 at 09:36:32AM -0700, Dixit, Ashutosh wrote: > > On Wed, 23 Oct 2024 13:07:15 -0700, Jonathan Cavitt wrote: > >> > > > > Hi Umesh, > > > >> @@ -748,6 +754,14 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads, > >> } > >> } > >> > >> + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL0, count++); > >> + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL1, count++); > >> + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL2, count++); > >> + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL3, count++); > >> + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL4, count++); > >> + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL5, count++); > >> + guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL6, count++); > > > > I am trying to understand how this works. So these registers are > > saved/restored by GuC because they are not part of HW context image > > correct. > > > and that is why GuC needs to do the save/restore? > > yes, only if GuC performs an engine reset > > > Bspec 46458/56839 do seem to > > be saying that these registers are context saved/restored? If that is > > indeed true (though not sure), do they need to be here? > > For pre-gen12 they were part of the engine context image, but not from > gen12 onwards. From gen12, they are in the power context image. > > These were added because users were seeing the EuStall and EuActive > counters zeroed out during OA use case. GuC was doing an engine reset for > some reason and that was resetting these registers. Once we added it here > (so GuC would save restore these), the counters had correct values. Hi Umesh, thanks for the explanation, yes let's just leave these here. Reviewed-by: Ashutosh Dixit