i915 has a configurable fence wait timeout, defaulting to 10 seconds,
and xe uses MAX_SCHEDULE_TIMEOUT i.e. it has no timeout.
Use a fixed 10 second timeout for both drivers instead of having them do
different things. Ditch the now unused compat header from xe.
i915 actually needs the timeout to deal with CI reset tests, but there
shouldn't be any harm in having a 10 second timeout in xe either.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
There have been a number of stabs at this in the past (see links below),
and all of them have been rejected with one reason or another.
My primary goal here is just to remove the annoying i915_fence_timeout()
usage and i915 vs. xe difference. Further cleanup can come later (or
never, as it usually is).
https://lore.kernel.org/r/20251112155612.8320-1-jani.nikula@intel.com
https://lore.kernel.org/r/20251113155332.789554-1-jani.nikula@intel.com
https://lore.kernel.org/r/8cde57236982fc3ca1a5608332943d3b9274a45a.1775661609.git.jani.nikula@intel.com
https://lore.kernel.org/r/20260408233458.22666-6-ville.syrjala@linux.intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +---
.../gpu/drm/xe/compat-i915-headers/i915_config.h | 16 ----------------
2 files changed, 1 insertion(+), 19 deletions(-)
delete mode 100644 drivers/gpu/drm/xe/compat-i915-headers/i915_config.h
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index aa5d41dac8a9..c3a11e9e69e2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -50,7 +50,6 @@
#include "g4x_dp.h"
#include "g4x_hdmi.h"
#include "hsw_ips.h"
-#include "i915_config.h"
#include "i9xx_plane.h"
#include "i9xx_plane_regs.h"
#include "i9xx_wm.h"
@@ -7284,8 +7283,7 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *state)
if (!new_plane_state->fence)
continue;
- ret = dma_fence_wait_timeout(new_plane_state->fence, false,
- i915_fence_timeout());
+ ret = dma_fence_wait_timeout(new_plane_state->fence, false, 10 * HZ);
if (!ret)
ret = -ETIMEDOUT;
if (ret < 0) {
Not waiting on fences until they're signaled is an existing issue in
i915, and was added as a workaround for a deadlock when GPU reset
has to reset display as well on old platforms. This requires a
modeset to disable everything, which may hang since it could wait on
a fence that may only be signaled after gpu reset completes.