From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C0EAE69E90 for ; Mon, 2 Dec 2024 20:33:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D328C10E1DE; Mon, 2 Dec 2024 20:33:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="X9EfJhxw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6E26D10E1DE for ; Mon, 2 Dec 2024 20:33:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733171605; x=1764707605; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=QC3K1wi8LGuYzXRzAqE0jvZzdsEBwsXF2KJUaIjQDvU=; b=X9EfJhxwsIuwnCmXq9n68SBJyLC7I1xRbIM/lK4a60npcfxjjjLl3hPI 6siuh0SNHEkC9kwnW531dZWG/HLOT7n9S9S/mAYTV97JWZDmXu2AMy6BZ HzaS5Ek3OwtpyC1hKRccVOyqumXM4l5tGnno0aKJLnPlXJ1ou91kZMBx0 YIB5w4g0ajML7JD3j+S/QmXRkusArL4/bimvmTSDLG6/5j34gEHdEO1lX GiTrgXxcx8+VBALqiQb0Hl8wENXAKxFcF5tN8juCb5jszSqoV03azXKRw Wm2PfML1Vd8b2wuanx0WOuVEOQYXnsp7qhMrqhUQ0lc5SWLKdIdhtumol Q==; X-CSE-ConnectionGUID: XpwBaTG/S1uvek6zoCzeSg== X-CSE-MsgGUID: 1btIlJWpQzyiBLzOYL9m/g== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="50777837" X-IronPort-AV: E=Sophos;i="6.12,203,1728975600"; d="scan'208";a="50777837" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 12:33:25 -0800 X-CSE-ConnectionGUID: Lspb+sBzSpmDOy33KVs2DA== X-CSE-MsgGUID: PfK+WtpITO+MuwsWAfmbOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,203,1728975600"; d="scan'208";a="97288282" Received: from orsosgc001.jf.intel.com (HELO orsosgc001.intel.com) ([10.165.21.142]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 12:33:24 -0800 Date: Mon, 02 Dec 2024 12:33:24 -0800 Message-ID: <85ttbl3jvv.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Jonathan Cavitt Cc: , , , , , , Subject: Re: [PATCH v3] drm/xe/xe_guc_ads: Add nonpriv registers to write list In-Reply-To: <20241122180826.7075-1-jonathan.cavitt@intel.com> References: <20241122180826.7075-1-jonathan.cavitt@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-redhat-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Fri, 22 Nov 2024 10:08:26 -0800, Jonathan Cavitt wrote: > > When performing a guc_mmio_regset_write, we add all the registers in the > reg_sr list to the save/restore list, but do not do the same for the > nonpriv registers. Add them in. > > v2: > - Add all NONPRIV registers to avoid undefined behavior (Harrison) > - s/whitelist/nonpriv > > v3: > - Rebase > > Closes: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2249 > Signed-off-by: Jonathan Cavitt > CC: Lucas de Marchi > CC: Matt Roper > CC: John Harrison > CC: Umesh Nerlige Ramappa > CC: Ashutosh Dixit > Reviewed-by: Lucas De Marchi > --- > drivers/gpu/drm/xe/xe_guc_ads.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c > index 943146e5b460..b0afb89d9d90 100644 > --- a/drivers/gpu/drm/xe/xe_guc_ads.c > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c > @@ -243,6 +243,8 @@ static size_t calculate_regset_size(struct xe_gt *gt) > xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry) > count++; > > + count += RING_MAX_NONPRIV_SLOTS * XE_NUM_HW_ENGINES; > + > count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES; > > if (XE_WA(gt, 1607983814)) > @@ -727,6 +729,11 @@ static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads, > xa_for_each(&hwe->reg_sr.xa, idx, entry) > guc_mmio_regset_write_one(ads, regset_map, entry->reg, count++); > > + for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) > + guc_mmio_regset_write_one(ads, regset_map, > + RING_FORCE_TO_NONPRIV(hwe->mmio_base, i), > + count++); > + What about the EU_PERF_CNTL registers which were there in the original patch? Those are not needed? > for (e = extra_regs; e < extra_regs + ARRAY_SIZE(extra_regs); e++) { > if (e->skip) > continue; > -- > 2.43.0 >