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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from IA0PR11MB7307.namprd11.prod.outlook.com (2603:10b6:208:437::10) by SA3PR11MB9487.namprd11.prod.outlook.com (2603:10b6:806:47e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9253.13; Thu, 23 Oct 2025 09:32:44 +0000 Received: from IA0PR11MB7307.namprd11.prod.outlook.com ([fe80::dafa:d38d:8ac1:e843]) by IA0PR11MB7307.namprd11.prod.outlook.com ([fe80::dafa:d38d:8ac1:e843%6]) with mapi id 15.20.9253.011; Thu, 23 Oct 2025 09:32:44 +0000 Message-ID: <86bf906a-db11-4ab5-8d6d-4eae25bd1599@intel.com> Date: Thu, 23 Oct 2025 15:02:36 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 12/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy To: "Kandpal, Suraj" , "intel-xe@lists.freedesktop.org" , "intel-gfx@lists.freedesktop.org" CC: "Nautiyal, Ankit K" , "Shankar, Uma" , "Sousa, Gustavo" , "De Marchi, Lucas" References: <20251015040817.3431297-1-suraj.kandpal@intel.com> <20251015040817.3431297-13-suraj.kandpal@intel.com> <9f7466b5-e5e7-4603-b564-0ef7f073d2c7@intel.com> Content-Language: en-US From: "Murthy, Arun R" In-Reply-To: Content-Type: text/plain; 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>> How was this delay value derived? > While doing power on we came up with this empirical value after a lot of trial and error. Might be the settling time required for the PHY. Please add a Re-visit/TODO Thanks and Regards, Arun R Murthy ------------------- > Regards, > Suraj Kandpal > >> Thanks and Regards, >> Arun R Murthy >> ------------------- >> >>> + intel_clear_response_ready_flag(encoder, lane); >>> + intel_lt_phy_clear_status_p2p(encoder, lane); >>> + >>> + return 0; >>> +} >>> + >>> +static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder, >>> + int lane, u16 addr, u8 data, >>> + i915_reg_t mac_reg_addr, >>> + u8 expected_mac_val) >>> +{ >>> + struct intel_display *display = to_intel_display(encoder); >>> + enum phy phy = intel_encoder_to_phy(encoder); >>> + int i, status; >>> + >>> + assert_dc_off(display); >>> + >>> + /* 3 tries is assumed to be enough to write successfully */ >>> + for (i = 0; i < 3; i++) { >>> + status = __intel_lt_phy_p2p_write_once(encoder, lane, addr, >> data, mac_reg_addr, >>> + expected_mac_val); >>> + >>> + if (status == 0) >>> + return; >>> + } >>> + >>> + drm_err_once(display->drm, >>> + "PHY %c P2P Write %04x failed after %d retries.\n", >>> +phy_name(phy), addr, i); } >>> + >>> +static void intel_lt_phy_p2p_write(struct intel_encoder *encoder, >>> + u8 lane_mask, u16 addr, u8 data, >>> + i915_reg_t mac_reg_addr, >>> + u8 expected_mac_val) >>> +{ >>> + int lane; >>> + >>> + for_each_lt_phy_lane_in_mask(lane_mask, lane) >>> + __intel_lt_phy_p2p_write(encoder, lane, addr, data, >> mac_reg_addr, >>> +expected_mac_val); } >>> + >>> static void >>> intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 >> lane_count) >>> { >>> @@ -1417,6 +1528,10 @@ void intel_lt_phy_pll_enable(struct >> intel_encoder *encoder, >>> * register at offset 0xC00 for Owned PHY Lanes*. >>> */ >>> /* 6.3. Clear P2P transaction Ready bit. */ >>> + intel_lt_phy_p2p_write(encoder, owned_lane_mask, >> LT_PHY_RATE_UPDATE, >>> + LT_PHY_RATE_CONTROL_VDR_UPDATE, >> LT_PHY_MAC_VDR, >>> + LT_PHY_PCLKIN_GATE); >>> + >>> /* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. >> */ >>> /* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */ >>> /* >>> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h >>> b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h >>> index a4aa2a3e0425..5fb4331c387f 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h >>> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h >>> @@ -9,12 +9,17 @@ >>> #include "i915_reg_defs.h" >>> #include "intel_display_limits.h" >>> >>> +#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500 >>> #define XE3PLPD_MACCLK_TURNON_LATENCY_MS 1 >>> #define XE3PLPD_MACCLK_TURNON_LATENCY_US 21 >>> #define XE3PLPD_RATE_CALIB_DONE_LATENCY_US 50 >>> #define XE3PLPD_RESET_START_LATENCY_US 10 >>> #define XE3PLPD_RESET_END_LATENCY_US 200 >>> >>> +/* LT Phy MAC Register */ >>> +#define LT_PHY_MAC_VDR _MMIO(0xC00) >>> +#define LT_PHY_PCLKIN_GATE REG_BIT8(0) >>> + >>> /* LT Phy Vendor Register */ >>> #define LT_PHY_VDR_0_CONFIG 0xC02 >>> #define LT_PHY_VDR_DP_PLL_ENABLE REG_BIT(7) >>> @@ -29,6 +34,7 @@ >>> #define LT_PHY_VDR_X_DATAY(idx, y) ((0xC06 + (3 - (y))) + 0x6 * >> (idx)) >>> #define LT_PHY_RATE_UPDATE 0xCC4 >>> +#define LT_PHY_RATE_CONTROL_VDR_UPDATE REG_BIT8(0) >>> >>> #define _XE3PLPD_PORT_BUF_CTL5(idx) >> _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ >> _XELPDP_PORT_BUF_CTL1_LN0_A, \ @@ -41,4 +47,13 @@ >>> #define XE3PLPD_MACCLK_RATE_MASK REG_GENMASK(4, 0) >>> #define XE3PLPD_MACCLK_RATE_DEF >> REG_FIELD_PREP(XE3PLPD_MACCLK_RATE_MASK, 0x1F) >>> +#define _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(idx, lane) >> _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ >>> + >> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ >>> + >> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ >>> + >> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ >>> + >> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) \ >>> + >> + 0x60 + (lane) * 0x4) >>> +#define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane) >> _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \ >>> + >> lane) >>> +#define XE3LPD_PORT_P2M_ADDR_MASK >> REG_GENMASK(11, 0) >>> #endif /* __INTEL_LT_PHY_REGS_H__ */