Re: [PATCH v2 05/11] drm/i915/psr: Write PIPEDMC_BLOCK_PKGC_SW when enabling PSR

[Jani Nikula <jani.nikula@linux.intel.com>]

On Mon, 17 Mar 2025, Jouni Högander <jouni.hogander@intel.com> wrote:
> Write PIPEDMC_BLOCK_PKGC_SW when enabling PSR as described in workaround
> for underrun on idle PSR HW issue (Wa_16025596647).
>
> Bspec: 74151
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1415e1e7aaf2c..a3946eef44f0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -37,6 +37,7 @@
>  #include "intel_de.h"
>  #include "intel_display_irq.h"
>  #include "intel_display_types.h"
> +#include "intel_dmc_regs.h"

Mildly annoying to poke at dmc registers from psr code.

BR,
Jani.

>  #include "intel_dp.h"
>  #include "intel_dp_aux.h"
>  #include "intel_frontbuffer.h"
> @@ -1961,6 +1962,13 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  			intel_de_rmw(display, CLKGATE_DIS_MISC, 0,
>  				     CLKGATE_DIS_MISC_DMASC_GATING_DIS);
>  	}
> +
> +	/* Wa_16025596647 */
> +	if ((DISPLAY_VER(display) == 20 ||
> +	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
> +	    !intel_dp->psr.panel_replay_enabled)
> +		intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(intel_dp->psr.pipe), 0,
> +			     PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS);
>  }
>  
>  static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
> @@ -2186,6 +2194,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  					   DP_RECEIVER_ALPM_CONFIG, 0);
>  	}
>  
> +	/* Wa_16025596647 */
> +	if ((DISPLAY_VER(display) == 20 ||
> +	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
> +	    !intel_dp->psr.panel_replay_enabled)
> +		intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(intel_dp->psr.pipe),
> +			     PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, 0);
> +
>  	intel_dp->psr.enabled = false;
>  	intel_dp->psr.panel_replay_enabled = false;
>  	intel_dp->psr.sel_update_enabled = false;

-- 
Jani Nikula, Intel