* [PATCH 01/18] drm/i915/dpll: Rename intel_dpll
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:04 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 02/18] drm/i915/dpll: Rename intel_dpll_funcs Suraj Kandpal
` (16 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename intel_dpll to intel_dpll_global so that intel_shared_dpll
can be renamed to intel_dpll in an effort to move away from the shared
naming convention.
Also intel_dpll according to it's comment tracks global dpll rather
than individual hence making more sense this gets changed.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_core.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index b4937e102360..6fc213f84e73 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -122,7 +122,7 @@ struct intel_audio {
* intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
* dpll, because on some platforms plls share registers.
*/
-struct intel_dpll {
+struct intel_dpll_global {
struct mutex lock;
int num_shared_dpll;
@@ -570,7 +570,7 @@ struct intel_display {
/* Grouping using named structs. Keep sorted. */
struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
struct intel_audio audio;
- struct intel_dpll dpll;
+ struct intel_dpll_global dpll;
struct intel_fbc *fbc[I915_MAX_FBCS];
struct intel_frontbuffer_tracking fb_tracking;
struct intel_hotplug hotplug;
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 01/18] drm/i915/dpll: Rename intel_dpll
2025-05-09 4:27 ` [PATCH 01/18] drm/i915/dpll: Rename intel_dpll Suraj Kandpal
@ 2025-05-09 10:04 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:04 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_dpll to intel_dpll_global so that intel_shared_dpll
> can be renamed to intel_dpll in an effort to move away from the shared
> naming convention.
> Also intel_dpll according to it's comment tracks global dpll rather
> than individual hence making more sense this gets changed.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_core.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index b4937e102360..6fc213f84e73 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -122,7 +122,7 @@ struct intel_audio {
> * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
> * dpll, because on some platforms plls share registers.
> */
> -struct intel_dpll {
> +struct intel_dpll_global {
> struct mutex lock;
>
> int num_shared_dpll;
> @@ -570,7 +570,7 @@ struct intel_display {
> /* Grouping using named structs. Keep sorted. */
> struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
> struct intel_audio audio;
> - struct intel_dpll dpll;
> + struct intel_dpll_global dpll;
> struct intel_fbc *fbc[I915_MAX_FBCS];
> struct intel_frontbuffer_tracking fb_tracking;
> struct intel_hotplug hotplug;
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 02/18] drm/i915/dpll: Rename intel_dpll_funcs
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
2025-05-09 4:27 ` [PATCH 01/18] drm/i915/dpll: Rename intel_dpll Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:05 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 03/18] drm/i915/dpll: Rename intel_shared_dpll_state Suraj Kandpal
` (15 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename intel_dpll_funcs to intel_dpll_global_funcs so that later
on intel_shared_dpll_funcs can be renamed to intel_dpll_funcs.
This is done to move away from the shared naming convention since
starting MTL dpll's are not shared among PHYs.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 4 ++--
drivers/gpu/drm/i915/display/intel_dpll.c | 22 +++++++++----------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 6fc213f84e73..e0221e514326 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -42,7 +42,7 @@ struct intel_color_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dmc;
-struct intel_dpll_funcs;
+struct intel_dpll_global_funcs;
struct intel_dpll_mgr;
struct intel_fbdev;
struct intel_fdi_funcs;
@@ -300,7 +300,7 @@ struct intel_display {
const struct intel_cdclk_funcs *cdclk;
/* Display pll funcs */
- const struct intel_dpll_funcs *dpll;
+ const struct intel_dpll_global_funcs *dpll;
/* irq display functions */
const struct intel_hotplug_funcs *hotplug;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index a9e9b98d0bf9..8db603d9c823 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -24,7 +24,7 @@
#include "vlv_dpio_phy_regs.h"
#include "vlv_sideband.h"
-struct intel_dpll_funcs {
+struct intel_dpll_global_funcs {
int (*crtc_compute_clock)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
@@ -1690,45 +1690,45 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
-static const struct intel_dpll_funcs mtl_dpll_funcs = {
+static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
.crtc_compute_clock = mtl_crtc_compute_clock,
};
-static const struct intel_dpll_funcs dg2_dpll_funcs = {
+static const struct intel_dpll_global_funcs dg2_dpll_funcs = {
.crtc_compute_clock = dg2_crtc_compute_clock,
};
-static const struct intel_dpll_funcs hsw_dpll_funcs = {
+static const struct intel_dpll_global_funcs hsw_dpll_funcs = {
.crtc_compute_clock = hsw_crtc_compute_clock,
.crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
};
-static const struct intel_dpll_funcs ilk_dpll_funcs = {
+static const struct intel_dpll_global_funcs ilk_dpll_funcs = {
.crtc_compute_clock = ilk_crtc_compute_clock,
.crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
};
-static const struct intel_dpll_funcs chv_dpll_funcs = {
+static const struct intel_dpll_global_funcs chv_dpll_funcs = {
.crtc_compute_clock = chv_crtc_compute_clock,
};
-static const struct intel_dpll_funcs vlv_dpll_funcs = {
+static const struct intel_dpll_global_funcs vlv_dpll_funcs = {
.crtc_compute_clock = vlv_crtc_compute_clock,
};
-static const struct intel_dpll_funcs g4x_dpll_funcs = {
+static const struct intel_dpll_global_funcs g4x_dpll_funcs = {
.crtc_compute_clock = g4x_crtc_compute_clock,
};
-static const struct intel_dpll_funcs pnv_dpll_funcs = {
+static const struct intel_dpll_global_funcs pnv_dpll_funcs = {
.crtc_compute_clock = pnv_crtc_compute_clock,
};
-static const struct intel_dpll_funcs i9xx_dpll_funcs = {
+static const struct intel_dpll_global_funcs i9xx_dpll_funcs = {
.crtc_compute_clock = i9xx_crtc_compute_clock,
};
-static const struct intel_dpll_funcs i8xx_dpll_funcs = {
+static const struct intel_dpll_global_funcs i8xx_dpll_funcs = {
.crtc_compute_clock = i8xx_crtc_compute_clock,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 02/18] drm/i915/dpll: Rename intel_dpll_funcs
2025-05-09 4:27 ` [PATCH 02/18] drm/i915/dpll: Rename intel_dpll_funcs Suraj Kandpal
@ 2025-05-09 10:05 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:05 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_dpll_funcs to intel_dpll_global_funcs so that later
> on intel_shared_dpll_funcs can be renamed to intel_dpll_funcs.
> This is done to move away from the shared naming convention since
> starting MTL dpll's are not shared among PHYs.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
My gut feeling is that the whole dpll and shared dpll distinction was a
mistake, and we should just have one dpll framework. But let's see where
this goes.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 4 ++--
> drivers/gpu/drm/i915/display/intel_dpll.c | 22 +++++++++----------
> 2 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 6fc213f84e73..e0221e514326 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -42,7 +42,7 @@ struct intel_color_funcs;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_dmc;
> -struct intel_dpll_funcs;
> +struct intel_dpll_global_funcs;
> struct intel_dpll_mgr;
> struct intel_fbdev;
> struct intel_fdi_funcs;
> @@ -300,7 +300,7 @@ struct intel_display {
> const struct intel_cdclk_funcs *cdclk;
>
> /* Display pll funcs */
> - const struct intel_dpll_funcs *dpll;
> + const struct intel_dpll_global_funcs *dpll;
>
> /* irq display functions */
> const struct intel_hotplug_funcs *hotplug;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index a9e9b98d0bf9..8db603d9c823 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -24,7 +24,7 @@
> #include "vlv_dpio_phy_regs.h"
> #include "vlv_sideband.h"
>
> -struct intel_dpll_funcs {
> +struct intel_dpll_global_funcs {
> int (*crtc_compute_clock)(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
> @@ -1690,45 +1690,45 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
> return 0;
> }
>
> -static const struct intel_dpll_funcs mtl_dpll_funcs = {
> +static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
> .crtc_compute_clock = mtl_crtc_compute_clock,
> };
>
> -static const struct intel_dpll_funcs dg2_dpll_funcs = {
> +static const struct intel_dpll_global_funcs dg2_dpll_funcs = {
> .crtc_compute_clock = dg2_crtc_compute_clock,
> };
>
> -static const struct intel_dpll_funcs hsw_dpll_funcs = {
> +static const struct intel_dpll_global_funcs hsw_dpll_funcs = {
> .crtc_compute_clock = hsw_crtc_compute_clock,
> .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
> };
>
> -static const struct intel_dpll_funcs ilk_dpll_funcs = {
> +static const struct intel_dpll_global_funcs ilk_dpll_funcs = {
> .crtc_compute_clock = ilk_crtc_compute_clock,
> .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
> };
>
> -static const struct intel_dpll_funcs chv_dpll_funcs = {
> +static const struct intel_dpll_global_funcs chv_dpll_funcs = {
> .crtc_compute_clock = chv_crtc_compute_clock,
> };
>
> -static const struct intel_dpll_funcs vlv_dpll_funcs = {
> +static const struct intel_dpll_global_funcs vlv_dpll_funcs = {
> .crtc_compute_clock = vlv_crtc_compute_clock,
> };
>
> -static const struct intel_dpll_funcs g4x_dpll_funcs = {
> +static const struct intel_dpll_global_funcs g4x_dpll_funcs = {
> .crtc_compute_clock = g4x_crtc_compute_clock,
> };
>
> -static const struct intel_dpll_funcs pnv_dpll_funcs = {
> +static const struct intel_dpll_global_funcs pnv_dpll_funcs = {
> .crtc_compute_clock = pnv_crtc_compute_clock,
> };
>
> -static const struct intel_dpll_funcs i9xx_dpll_funcs = {
> +static const struct intel_dpll_global_funcs i9xx_dpll_funcs = {
> .crtc_compute_clock = i9xx_crtc_compute_clock,
> };
>
> -static const struct intel_dpll_funcs i8xx_dpll_funcs = {
> +static const struct intel_dpll_global_funcs i8xx_dpll_funcs = {
> .crtc_compute_clock = i8xx_crtc_compute_clock,
> };
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 03/18] drm/i915/dpll: Rename intel_shared_dpll_state
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
2025-05-09 4:27 ` [PATCH 01/18] drm/i915/dpll: Rename intel_dpll Suraj Kandpal
2025-05-09 4:27 ` [PATCH 02/18] drm/i915/dpll: Rename intel_dpll_funcs Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:07 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 04/18] drm/i915/dpll: Rename macro for_each_shared_dpll Suraj Kandpal
` (14 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename intel_shared_dpll_state to just intel_dpll_state since it may
not necessarily store share dpll state info specially since
DISPLAY_VER >= 14 PLL's are not shared.
Also change the name of variables which may have been assoiciated as
a shared_dpll.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 +--
3 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d6d0440dcee9..1bdffaca153a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -591,7 +591,7 @@ struct intel_atomic_state {
bool dpll_set, modeset;
- struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
+ struct intel_dpll_state dpll_state[I915_NUM_PLLS];
struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9da051a3f455..6b4eb230f4b3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -122,17 +122,17 @@ struct intel_dpll_mgr {
static void
intel_atomic_duplicate_dpll_state(struct intel_display *display,
- struct intel_shared_dpll_state *shared_dpll)
+ struct intel_dpll_state *dpll_state)
{
struct intel_shared_dpll *pll;
int i;
/* Copy shared dpll state */
for_each_shared_dpll(display, pll, i)
- shared_dpll[pll->index] = pll->state;
+ dpll_state[pll->index] = pll->state;
}
-static struct intel_shared_dpll_state *
+static struct intel_dpll_state *
intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
@@ -144,10 +144,10 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
state->dpll_set = true;
intel_atomic_duplicate_dpll_state(display,
- state->shared_dpll);
+ state->dpll_state);
}
- return state->shared_dpll;
+ return state->dpll_state;
}
/**
@@ -365,11 +365,11 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
{
struct intel_display *display = to_intel_display(crtc);
unsigned long dpll_mask_all = intel_dpll_mask_all(display);
- struct intel_shared_dpll_state *shared_dpll;
+ struct intel_dpll_state *dpll_state;
struct intel_shared_dpll *unused_pll = NULL;
enum intel_dpll_id id;
- shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
@@ -381,20 +381,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
continue;
/* Only want to check enabled timings first */
- if (shared_dpll[pll->index].pipe_mask == 0) {
+ if (dpll_state[pll->index].pipe_mask == 0) {
if (!unused_pll)
unused_pll = pll;
continue;
}
if (memcmp(dpll_hw_state,
- &shared_dpll[pll->index].hw_state,
+ &dpll_state[pll->index].hw_state,
sizeof(*dpll_hw_state)) == 0) {
drm_dbg_kms(display->drm,
"[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
crtc->base.base.id, crtc->base.name,
pll->info->name,
- shared_dpll[pll->index].pipe_mask,
+ dpll_state[pll->index].pipe_mask,
pll->active_mask);
return pll;
}
@@ -415,20 +415,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
* intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is taken
* @pll: DPLL for which the reference is taken
- * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
+ * @dpll_state: the DPLL atomic state in which the reference is tracked
*
* Take a reference for @pll tracking the use of it by @crtc.
*/
static void
intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
- struct intel_shared_dpll_state *shared_dpll_state)
+ struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
- drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
+ drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
- shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
+ dpll_state->pipe_mask |= BIT(crtc->pipe);
drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
@@ -440,34 +440,34 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
- struct intel_shared_dpll_state *shared_dpll;
+ struct intel_dpll_state *dpll_state;
- shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
- if (shared_dpll[pll->index].pipe_mask == 0)
- shared_dpll[pll->index].hw_state = *dpll_hw_state;
+ if (dpll_state[pll->index].pipe_mask == 0)
+ dpll_state[pll->index].hw_state = *dpll_hw_state;
- intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
+ intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
}
/**
* intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is dropped
* @pll: DPLL for which the reference is dropped
- * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
+ * @dpll_state: the DPLL atomic state in which the reference is tracked
*
* Drop a reference for @pll tracking the end of use of it by @crtc.
*/
void
intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
- struct intel_shared_dpll_state *shared_dpll_state)
+ struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
- drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
+ drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
- shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
+ dpll_state->pipe_mask &= ~BIT(crtc->pipe);
drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
@@ -477,11 +477,11 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll)
{
- struct intel_shared_dpll_state *shared_dpll;
+ struct intel_dpll_state *dpll_state;
- shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
- intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
+ intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
}
static void intel_put_dpll(struct intel_atomic_state *state,
@@ -514,7 +514,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
+ struct intel_dpll_state *dpll_state = state->dpll_state;
struct intel_shared_dpll *pll;
int i;
@@ -522,7 +522,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
return;
for_each_shared_dpll(display, pll, i)
- swap(pll->state, shared_dpll[pll->index]);
+ swap(pll->state, dpll_state[pll->index]);
}
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index caffb084830c..fe6c676737bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -280,7 +280,7 @@ struct intel_dpll_hw_state {
};
/**
- * struct intel_shared_dpll_state - hold the DPLL atomic state
+ * struct intel_dpll_state - hold the DPLL atomic state
*
* This structure holds an atomic state for the DPLL, that can represent
* either its current state (in struct &intel_shared_dpll) or a desired
@@ -289,7 +289,7 @@ struct intel_dpll_hw_state {
*
* See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
*/
-struct intel_shared_dpll_state {
+struct intel_dpll_state {
/**
* @pipe_mask: mask of pipes using this DPLL, active or not
*/
@@ -353,7 +353,7 @@ struct intel_shared_dpll {
* Store the state for the pll, including its hw state
* and CRTCs using it.
*/
- struct intel_shared_dpll_state state;
+ struct intel_dpll_state state;
/**
* @index: index for atomic state
@@ -406,7 +406,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
const struct intel_shared_dpll *pll,
- struct intel_shared_dpll_state *shared_dpll_state);
+ struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
enum icl_port_dpll_id port_dpll_id);
void intel_update_active_dpll(struct intel_atomic_state *state,
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 03/18] drm/i915/dpll: Rename intel_shared_dpll_state
2025-05-09 4:27 ` [PATCH 03/18] drm/i915/dpll: Rename intel_shared_dpll_state Suraj Kandpal
@ 2025-05-09 10:07 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:07 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_shared_dpll_state to just intel_dpll_state since it may
> not necessarily store share dpll state info specially since
> DISPLAY_VER >= 14 PLL's are not shared.
> Also change the name of variables which may have been assoiciated as
> a shared_dpll.
*associated
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++----------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 +--
> 3 files changed, 33 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d6d0440dcee9..1bdffaca153a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -591,7 +591,7 @@ struct intel_atomic_state {
>
> bool dpll_set, modeset;
>
> - struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
> + struct intel_dpll_state dpll_state[I915_NUM_PLLS];
>
> struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 9da051a3f455..6b4eb230f4b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -122,17 +122,17 @@ struct intel_dpll_mgr {
>
> static void
> intel_atomic_duplicate_dpll_state(struct intel_display *display,
> - struct intel_shared_dpll_state *shared_dpll)
> + struct intel_dpll_state *dpll_state)
> {
> struct intel_shared_dpll *pll;
> int i;
>
> /* Copy shared dpll state */
> for_each_shared_dpll(display, pll, i)
> - shared_dpll[pll->index] = pll->state;
> + dpll_state[pll->index] = pll->state;
> }
>
> -static struct intel_shared_dpll_state *
> +static struct intel_dpll_state *
> intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> {
> struct intel_atomic_state *state = to_intel_atomic_state(s);
> @@ -144,10 +144,10 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> state->dpll_set = true;
>
> intel_atomic_duplicate_dpll_state(display,
> - state->shared_dpll);
> + state->dpll_state);
> }
>
> - return state->shared_dpll;
> + return state->dpll_state;
> }
>
> /**
> @@ -365,11 +365,11 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> {
> struct intel_display *display = to_intel_display(crtc);
> unsigned long dpll_mask_all = intel_dpll_mask_all(display);
> - struct intel_shared_dpll_state *shared_dpll;
> + struct intel_dpll_state *dpll_state;
> struct intel_shared_dpll *unused_pll = NULL;
> enum intel_dpll_id id;
>
> - shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> + dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
>
> drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
>
> @@ -381,20 +381,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> continue;
>
> /* Only want to check enabled timings first */
> - if (shared_dpll[pll->index].pipe_mask == 0) {
> + if (dpll_state[pll->index].pipe_mask == 0) {
> if (!unused_pll)
> unused_pll = pll;
> continue;
> }
>
> if (memcmp(dpll_hw_state,
> - &shared_dpll[pll->index].hw_state,
> + &dpll_state[pll->index].hw_state,
> sizeof(*dpll_hw_state)) == 0) {
> drm_dbg_kms(display->drm,
> "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
> crtc->base.base.id, crtc->base.name,
> pll->info->name,
> - shared_dpll[pll->index].pipe_mask,
> + dpll_state[pll->index].pipe_mask,
> pll->active_mask);
> return pll;
> }
> @@ -415,20 +415,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
> * @crtc: CRTC on which behalf the reference is taken
> * @pll: DPLL for which the reference is taken
> - * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
> + * @dpll_state: the DPLL atomic state in which the reference is tracked
> *
> * Take a reference for @pll tracking the use of it by @crtc.
> */
> static void
> intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> const struct intel_shared_dpll *pll,
> - struct intel_shared_dpll_state *shared_dpll_state)
> + struct intel_dpll_state *dpll_state)
> {
> struct intel_display *display = to_intel_display(crtc);
>
> - drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
> + drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
>
> - shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
> + dpll_state->pipe_mask |= BIT(crtc->pipe);
>
> drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",
> crtc->base.base.id, crtc->base.name, pll->info->name);
> @@ -440,34 +440,34 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
> const struct intel_shared_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> - struct intel_shared_dpll_state *shared_dpll;
> + struct intel_dpll_state *dpll_state;
>
> - shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> + dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
>
> - if (shared_dpll[pll->index].pipe_mask == 0)
> - shared_dpll[pll->index].hw_state = *dpll_hw_state;
> + if (dpll_state[pll->index].pipe_mask == 0)
> + dpll_state[pll->index].hw_state = *dpll_hw_state;
>
> - intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
> + intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> }
>
> /**
> * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
> * @crtc: CRTC on which behalf the reference is dropped
> * @pll: DPLL for which the reference is dropped
> - * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
> + * @dpll_state: the DPLL atomic state in which the reference is tracked
> *
> * Drop a reference for @pll tracking the end of use of it by @crtc.
> */
> void
> intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> const struct intel_shared_dpll *pll,
> - struct intel_shared_dpll_state *shared_dpll_state)
> + struct intel_dpll_state *dpll_state)
> {
> struct intel_display *display = to_intel_display(crtc);
>
> - drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
> + drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
>
> - shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
> + dpll_state->pipe_mask &= ~BIT(crtc->pipe);
>
> drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",
> crtc->base.base.id, crtc->base.name, pll->info->name);
> @@ -477,11 +477,11 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> const struct intel_shared_dpll *pll)
> {
> - struct intel_shared_dpll_state *shared_dpll;
> + struct intel_dpll_state *dpll_state;
>
> - shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> + dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
>
> - intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
> + intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> }
>
> static void intel_put_dpll(struct intel_atomic_state *state,
> @@ -514,7 +514,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
> void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> {
> struct intel_display *display = to_intel_display(state);
> - struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
> + struct intel_dpll_state *dpll_state = state->dpll_state;
> struct intel_shared_dpll *pll;
> int i;
>
> @@ -522,7 +522,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> return;
>
> for_each_shared_dpll(display, pll, i)
> - swap(pll->state, shared_dpll[pll->index]);
> + swap(pll->state, dpll_state[pll->index]);
> }
>
> static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index caffb084830c..fe6c676737bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -280,7 +280,7 @@ struct intel_dpll_hw_state {
> };
>
> /**
> - * struct intel_shared_dpll_state - hold the DPLL atomic state
> + * struct intel_dpll_state - hold the DPLL atomic state
> *
> * This structure holds an atomic state for the DPLL, that can represent
> * either its current state (in struct &intel_shared_dpll) or a desired
> @@ -289,7 +289,7 @@ struct intel_dpll_hw_state {
> *
> * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
> */
> -struct intel_shared_dpll_state {
> +struct intel_dpll_state {
> /**
> * @pipe_mask: mask of pipes using this DPLL, active or not
> */
> @@ -353,7 +353,7 @@ struct intel_shared_dpll {
> * Store the state for the pll, including its hw state
> * and CRTCs using it.
> */
> - struct intel_shared_dpll_state state;
> + struct intel_dpll_state state;
>
> /**
> * @index: index for atomic state
> @@ -406,7 +406,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> const struct intel_shared_dpll *pll,
> - struct intel_shared_dpll_state *shared_dpll_state);
> + struct intel_dpll_state *shared_dpll_state);
> void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> enum icl_port_dpll_id port_dpll_id);
> void intel_update_active_dpll(struct intel_atomic_state *state,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 04/18] drm/i915/dpll: Rename macro for_each_shared_dpll
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (2 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 03/18] drm/i915/dpll: Rename intel_shared_dpll_state Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:07 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 05/18] drm/i915/dpll: Rename intel_shared_dpll_funcs Suraj Kandpal
` (13 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename the macro for_each_shared_dpll to for_each_dpll since
this loop will not necessarily be used for only shared
dpll in future.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++++++++--------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
drivers/gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 8d0a1779dd19..3770ce9469d1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -627,7 +627,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
display->dpll.ref_clks.nssc,
display->dpll.ref_clks.ssc);
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
pll->info->name, pll->info->id);
drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6b4eb230f4b3..9974fdb6eaeb 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -127,8 +127,8 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display,
struct intel_shared_dpll *pll;
int i;
- /* Copy shared dpll state */
- for_each_shared_dpll(display, pll, i)
+ /* Copy dpll state */
+ for_each_dpll(display, pll, i)
dpll_state[pll->index] = pll->state;
}
@@ -165,7 +165,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
if (pll->info->id == id)
return pll;
}
@@ -348,7 +348,7 @@ intel_dpll_mask_all(struct intel_display *display)
unsigned long dpll_mask = 0;
int i;
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
dpll_mask |= BIT(pll->info->id);
@@ -521,7 +521,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
if (!state->dpll_set)
return;
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
swap(pll->state, dpll_state[pll->index]);
}
@@ -4542,7 +4542,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display)
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
readout_dpll_hw_state(display, pll);
}
@@ -4571,7 +4571,7 @@ void intel_dpll_sanitize_state(struct intel_display *display)
intel_cx0_pll_power_save_wa(display);
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
sanitize_dpll_state(display, pll);
}
@@ -4720,6 +4720,6 @@ void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
struct intel_shared_dpll *pll;
int i;
- for_each_shared_dpll(display, pll, i)
+ for_each_dpll(display, pll, i)
verify_single_dpll_state(display, pll, NULL, NULL);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index fe6c676737bb..d93072486831 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -30,7 +30,7 @@
#include "intel_display_power.h"
#include "intel_wakeref.h"
-#define for_each_shared_dpll(__display, __pll, __i) \
+#define for_each_dpll(__display, __pll, __i) \
for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 693b90e3dfc3..8bec55deff9f 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -535,7 +535,7 @@ static void ilk_init_pch_refclk(struct intel_display *display)
}
/* Check if any DPLLs are using the SSC source */
- for_each_shared_dpll(display, pll, i) {
+ for_each_dpll(display, pll, i) {
u32 temp;
temp = intel_de_read(display, PCH_DPLL(pll->info->id));
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 04/18] drm/i915/dpll: Rename macro for_each_shared_dpll
2025-05-09 4:27 ` [PATCH 04/18] drm/i915/dpll: Rename macro for_each_shared_dpll Suraj Kandpal
@ 2025-05-09 10:07 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:07 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename the macro for_each_shared_dpll to for_each_dpll since
> this loop will not necessarily be used for only shared
> dpll in future.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++++++++--------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
> drivers/gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
> 4 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 8d0a1779dd19..3770ce9469d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -627,7 +627,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> display->dpll.ref_clks.nssc,
> display->dpll.ref_clks.ssc);
>
> - for_each_shared_dpll(display, pll, i) {
> + for_each_dpll(display, pll, i) {
> drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
> pll->info->name, pll->info->id);
> drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 6b4eb230f4b3..9974fdb6eaeb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -127,8 +127,8 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display,
> struct intel_shared_dpll *pll;
> int i;
>
> - /* Copy shared dpll state */
> - for_each_shared_dpll(display, pll, i)
> + /* Copy dpll state */
> + for_each_dpll(display, pll, i)
> dpll_state[pll->index] = pll->state;
> }
>
> @@ -165,7 +165,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
> struct intel_shared_dpll *pll;
> int i;
>
> - for_each_shared_dpll(display, pll, i) {
> + for_each_dpll(display, pll, i) {
> if (pll->info->id == id)
> return pll;
> }
> @@ -348,7 +348,7 @@ intel_dpll_mask_all(struct intel_display *display)
> unsigned long dpll_mask = 0;
> int i;
>
> - for_each_shared_dpll(display, pll, i) {
> + for_each_dpll(display, pll, i) {
> drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
>
> dpll_mask |= BIT(pll->info->id);
> @@ -521,7 +521,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> if (!state->dpll_set)
> return;
>
> - for_each_shared_dpll(display, pll, i)
> + for_each_dpll(display, pll, i)
> swap(pll->state, dpll_state[pll->index]);
> }
>
> @@ -4542,7 +4542,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display)
> struct intel_shared_dpll *pll;
> int i;
>
> - for_each_shared_dpll(display, pll, i)
> + for_each_dpll(display, pll, i)
> readout_dpll_hw_state(display, pll);
> }
>
> @@ -4571,7 +4571,7 @@ void intel_dpll_sanitize_state(struct intel_display *display)
>
> intel_cx0_pll_power_save_wa(display);
>
> - for_each_shared_dpll(display, pll, i)
> + for_each_dpll(display, pll, i)
> sanitize_dpll_state(display, pll);
> }
>
> @@ -4720,6 +4720,6 @@ void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
> struct intel_shared_dpll *pll;
> int i;
>
> - for_each_shared_dpll(display, pll, i)
> + for_each_dpll(display, pll, i)
> verify_single_dpll_state(display, pll, NULL, NULL);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index fe6c676737bb..d93072486831 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -30,7 +30,7 @@
> #include "intel_display_power.h"
> #include "intel_wakeref.h"
>
> -#define for_each_shared_dpll(__display, __pll, __i) \
> +#define for_each_dpll(__display, __pll, __i) \
> for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
> ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 693b90e3dfc3..8bec55deff9f 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -535,7 +535,7 @@ static void ilk_init_pch_refclk(struct intel_display *display)
> }
>
> /* Check if any DPLLs are using the SSC source */
> - for_each_shared_dpll(display, pll, i) {
> + for_each_dpll(display, pll, i) {
> u32 temp;
>
> temp = intel_de_read(display, PCH_DPLL(pll->info->id));
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 05/18] drm/i915/dpll: Rename intel_shared_dpll_funcs
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (3 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 04/18] drm/i915/dpll: Rename macro for_each_shared_dpll Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:08 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 06/18] drm/i915/dpll: Rename intel_shared_dpll Suraj Kandpal
` (12 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename intel_shared_dpll_funcs to intel_dpll_funcs
since it needs to represent both shared and individual
dplls.
--v2
-Change intel_global_dpll to intel_dpll_global to be more
in line with the naming standard where the name should
start with the file name [Jani]
--v3
-Drop shared and global altogether [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9974fdb6eaeb..bdad4d72cc01 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -64,7 +64,7 @@
*/
/* platform specific hooks for managing DPLLs */
-struct intel_shared_dpll_funcs {
+struct intel_dpll_funcs {
/*
* Hook for enabling the pll, called from intel_enable_shared_dpll() if
* the pll is not already enabled.
@@ -670,7 +670,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->fp1 == b->fp1;
}
-static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
+static const struct intel_dpll_funcs ibx_pch_dpll_funcs = {
.enable = ibx_pch_dpll_enable,
.disable = ibx_pch_dpll_disable,
.get_hw_state = ibx_pch_dpll_get_hw_state,
@@ -1270,14 +1270,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->spll == b->spll;
}
-static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
+static const struct intel_dpll_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
.disable = hsw_ddi_wrpll_disable,
.get_hw_state = hsw_ddi_wrpll_get_hw_state,
.get_freq = hsw_ddi_wrpll_get_freq,
};
-static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
+static const struct intel_dpll_funcs hsw_ddi_spll_funcs = {
.enable = hsw_ddi_spll_enable,
.disable = hsw_ddi_spll_disable,
.get_hw_state = hsw_ddi_spll_get_hw_state,
@@ -1302,7 +1302,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
return true;
}
-static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
+static const struct intel_dpll_funcs hsw_ddi_lcpll_funcs = {
.enable = hsw_ddi_lcpll_enable,
.disable = hsw_ddi_lcpll_disable,
.get_hw_state = hsw_ddi_lcpll_get_hw_state,
@@ -2004,14 +2004,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->cfgcr2 == b->cfgcr2;
}
-static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
+static const struct intel_dpll_funcs skl_ddi_pll_funcs = {
.enable = skl_ddi_pll_enable,
.disable = skl_ddi_pll_disable,
.get_hw_state = skl_ddi_pll_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
};
-static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
+static const struct intel_dpll_funcs skl_ddi_dpll0_funcs = {
.enable = skl_ddi_dpll0_enable,
.disable = skl_ddi_dpll0_disable,
.get_hw_state = skl_ddi_dpll0_get_hw_state,
@@ -2486,7 +2486,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->pcsdw12 == b->pcsdw12;
}
-static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
+static const struct intel_dpll_funcs bxt_ddi_pll_funcs = {
.enable = bxt_ddi_pll_enable,
.disable = bxt_ddi_pll_disable,
.get_hw_state = bxt_ddi_pll_get_hw_state,
@@ -4129,21 +4129,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias;
}
-static const struct intel_shared_dpll_funcs combo_pll_funcs = {
+static const struct intel_dpll_funcs combo_pll_funcs = {
.enable = combo_pll_enable,
.disable = combo_pll_disable,
.get_hw_state = combo_pll_get_hw_state,
.get_freq = icl_ddi_combo_pll_get_freq,
};
-static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
+static const struct intel_dpll_funcs tbt_pll_funcs = {
.enable = tbt_pll_enable,
.disable = tbt_pll_disable,
.get_hw_state = tbt_pll_get_hw_state,
.get_freq = icl_ddi_tbt_pll_get_freq,
};
-static const struct intel_shared_dpll_funcs mg_pll_funcs = {
+static const struct intel_dpll_funcs mg_pll_funcs = {
.enable = mg_pll_enable,
.disable = mg_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
@@ -4191,7 +4191,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.compare_hw_state = icl_compare_hw_state,
};
-static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
+static const struct intel_dpll_funcs dkl_pll_funcs = {
.enable = mg_pll_enable,
.disable = mg_pll_disable,
.get_hw_state = dkl_pll_get_hw_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index d93072486831..658174b99db3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -41,7 +41,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;
struct intel_shared_dpll;
-struct intel_shared_dpll_funcs;
+struct intel_dpll_funcs;
/**
* enum intel_dpll_id - possible DPLL ids
@@ -314,7 +314,7 @@ struct dpll_info {
/**
* @funcs: platform specific hooks
*/
- const struct intel_shared_dpll_funcs *funcs;
+ const struct intel_dpll_funcs *funcs;
/**
* @id: unique identifier for this DPLL
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 05/18] drm/i915/dpll: Rename intel_shared_dpll_funcs
2025-05-09 4:27 ` [PATCH 05/18] drm/i915/dpll: Rename intel_shared_dpll_funcs Suraj Kandpal
@ 2025-05-09 10:08 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:08 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_shared_dpll_funcs to intel_dpll_funcs
> since it needs to represent both shared and individual
> dplls.
>
> --v2
> -Change intel_global_dpll to intel_dpll_global to be more
> in line with the naming standard where the name should
> start with the file name [Jani]
>
> --v3
> -Drop shared and global altogether [Jani]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++----------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
> 2 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 9974fdb6eaeb..bdad4d72cc01 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -64,7 +64,7 @@
> */
>
> /* platform specific hooks for managing DPLLs */
> -struct intel_shared_dpll_funcs {
> +struct intel_dpll_funcs {
> /*
> * Hook for enabling the pll, called from intel_enable_shared_dpll() if
> * the pll is not already enabled.
> @@ -670,7 +670,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
> a->fp1 == b->fp1;
> }
>
> -static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
> +static const struct intel_dpll_funcs ibx_pch_dpll_funcs = {
> .enable = ibx_pch_dpll_enable,
> .disable = ibx_pch_dpll_disable,
> .get_hw_state = ibx_pch_dpll_get_hw_state,
> @@ -1270,14 +1270,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
> a->spll == b->spll;
> }
>
> -static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
> +static const struct intel_dpll_funcs hsw_ddi_wrpll_funcs = {
> .enable = hsw_ddi_wrpll_enable,
> .disable = hsw_ddi_wrpll_disable,
> .get_hw_state = hsw_ddi_wrpll_get_hw_state,
> .get_freq = hsw_ddi_wrpll_get_freq,
> };
>
> -static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
> +static const struct intel_dpll_funcs hsw_ddi_spll_funcs = {
> .enable = hsw_ddi_spll_enable,
> .disable = hsw_ddi_spll_disable,
> .get_hw_state = hsw_ddi_spll_get_hw_state,
> @@ -1302,7 +1302,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
> return true;
> }
>
> -static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
> +static const struct intel_dpll_funcs hsw_ddi_lcpll_funcs = {
> .enable = hsw_ddi_lcpll_enable,
> .disable = hsw_ddi_lcpll_disable,
> .get_hw_state = hsw_ddi_lcpll_get_hw_state,
> @@ -2004,14 +2004,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
> a->cfgcr2 == b->cfgcr2;
> }
>
> -static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
> +static const struct intel_dpll_funcs skl_ddi_pll_funcs = {
> .enable = skl_ddi_pll_enable,
> .disable = skl_ddi_pll_disable,
> .get_hw_state = skl_ddi_pll_get_hw_state,
> .get_freq = skl_ddi_pll_get_freq,
> };
>
> -static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
> +static const struct intel_dpll_funcs skl_ddi_dpll0_funcs = {
> .enable = skl_ddi_dpll0_enable,
> .disable = skl_ddi_dpll0_disable,
> .get_hw_state = skl_ddi_dpll0_get_hw_state,
> @@ -2486,7 +2486,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
> a->pcsdw12 == b->pcsdw12;
> }
>
> -static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
> +static const struct intel_dpll_funcs bxt_ddi_pll_funcs = {
> .enable = bxt_ddi_pll_enable,
> .disable = bxt_ddi_pll_disable,
> .get_hw_state = bxt_ddi_pll_get_hw_state,
> @@ -4129,21 +4129,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
> a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias;
> }
>
> -static const struct intel_shared_dpll_funcs combo_pll_funcs = {
> +static const struct intel_dpll_funcs combo_pll_funcs = {
> .enable = combo_pll_enable,
> .disable = combo_pll_disable,
> .get_hw_state = combo_pll_get_hw_state,
> .get_freq = icl_ddi_combo_pll_get_freq,
> };
>
> -static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
> +static const struct intel_dpll_funcs tbt_pll_funcs = {
> .enable = tbt_pll_enable,
> .disable = tbt_pll_disable,
> .get_hw_state = tbt_pll_get_hw_state,
> .get_freq = icl_ddi_tbt_pll_get_freq,
> };
>
> -static const struct intel_shared_dpll_funcs mg_pll_funcs = {
> +static const struct intel_dpll_funcs mg_pll_funcs = {
> .enable = mg_pll_enable,
> .disable = mg_pll_disable,
> .get_hw_state = mg_pll_get_hw_state,
> @@ -4191,7 +4191,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
> .compare_hw_state = icl_compare_hw_state,
> };
>
> -static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
> +static const struct intel_dpll_funcs dkl_pll_funcs = {
> .enable = mg_pll_enable,
> .disable = mg_pll_disable,
> .get_hw_state = dkl_pll_get_hw_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index d93072486831..658174b99db3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -41,7 +41,7 @@ struct intel_crtc;
> struct intel_crtc_state;
> struct intel_encoder;
> struct intel_shared_dpll;
> -struct intel_shared_dpll_funcs;
> +struct intel_dpll_funcs;
Nitpick, these should remain sorted.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> /**
> * enum intel_dpll_id - possible DPLL ids
> @@ -314,7 +314,7 @@ struct dpll_info {
> /**
> * @funcs: platform specific hooks
> */
> - const struct intel_shared_dpll_funcs *funcs;
> + const struct intel_dpll_funcs *funcs;
>
> /**
> * @id: unique identifier for this DPLL
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 06/18] drm/i915/dpll: Rename intel_shared_dpll
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (4 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 05/18] drm/i915/dpll: Rename intel_shared_dpll_funcs Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:13 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 07/18] drm/i915/dpll: Move away from using shared dpll Suraj Kandpal
` (11 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename intel_shared_dpll to intel_dpll to represent both
shared and individual dplls. Since from MTL each PHY has it's
own PLL making the shared PLL naming a little outdated. In an
effort to make this framework accepting of future changes this
needs to be done.
--v2
-Use intel_dpll_global to make sure names start with the filename
[Jani/Ville]
-Explain the need of this rename [Jani]
--v3
-Just keep it intel_dpll [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 52 ++--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 12 +-
.../gpu/drm/i915/display/intel_display_core.h | 4 +-
.../drm/i915/display/intel_display_debugfs.c | 2 +-
.../drm/i915/display/intel_display_types.h | 6 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 228 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 18 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c | 8 +-
.../gpu/drm/i915/display/intel_pch_display.c | 10 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
15 files changed, 179 insertions(+), 179 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ca7033251e91..55f0a20e0874 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -658,7 +658,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
{
struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ struct intel_dpll *pll = crtc_state->intel_dpll;
enum phy phy;
u32 val;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 74132c1d6385..4d631cbc81d2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -236,7 +236,7 @@ static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
port_name(port));
}
-static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
+static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll)
{
switch (pll->info->id) {
case DPLL_ID_WRPLL1:
@@ -260,7 +260,7 @@ static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll *pll = crtc_state->intel_dpll;
int clock = crtc_state->port_clock;
const enum intel_dpll_id id = pll->info->id;
@@ -1561,7 +1561,7 @@ static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t
return !(intel_de_read(display, reg) & clk_off);
}
-static struct intel_shared_dpll *
+static struct intel_dpll *
_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
u32 clk_sel_mask, u32 clk_sel_shift)
{
@@ -1576,7 +1576,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll *pll = crtc_state->intel_dpll;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(display->drm, !pll))
@@ -1606,7 +1606,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1620,7 +1620,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll *pll = crtc_state->intel_dpll;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(display->drm, !pll))
@@ -1650,7 +1650,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1664,7 +1664,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll *pll = crtc_state->intel_dpll;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(display->drm, !pll))
@@ -1703,7 +1703,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1730,7 +1730,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll *pll = crtc_state->intel_dpll;
enum phy phy = intel_encoder_to_phy(encoder);
if (drm_WARN_ON(display->drm, !pll))
@@ -1760,7 +1760,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
+struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
@@ -1774,7 +1774,7 @@ static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll *pll = crtc_state->intel_dpll;
enum port port = encoder->port;
if (drm_WARN_ON(display->drm, !pll))
@@ -1817,7 +1817,7 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll *pll = crtc_state->intel_dpll;
enum tc_port tc_port = intel_encoder_to_tc(encoder);
enum port port = encoder->port;
@@ -1868,7 +1868,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
}
-static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum tc_port tc_port = intel_encoder_to_tc(encoder);
@@ -1898,7 +1898,7 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
return intel_get_shared_dpll_by_id(display, id);
}
-static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder->base.dev);
enum intel_dpll_id id;
@@ -1925,7 +1925,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll *pll = crtc_state->intel_dpll;
enum port port = encoder->port;
if (drm_WARN_ON(display->drm, !pll))
@@ -1967,7 +1967,7 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
}
-static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
@@ -1993,7 +1993,7 @@ void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll *pll = crtc_state->intel_dpll;
enum port port = encoder->port;
if (drm_WARN_ON(display->drm, !pll))
@@ -2018,7 +2018,7 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
}
-static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
+static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
@@ -4187,7 +4187,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
void intel_ddi_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
struct intel_display *display = to_intel_display(encoder);
enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
@@ -4203,7 +4203,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
+ crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
&crtc_state->dpll_hw_state);
}
@@ -4257,7 +4257,7 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
intel_ddi_get_config(encoder, crtc_state);
}
-static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
+static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
{
return pll->info->id == DPLL_ID_ICL_TBTPLL;
}
@@ -4267,7 +4267,7 @@ icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(encoder);
- const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_dpll *pll = crtc_state->intel_dpll;
if (drm_WARN_ON(display->drm, !pll))
return ICL_PORT_DPLL_DEFAULT;
@@ -4290,7 +4290,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
struct intel_display *display = to_intel_display(encoder);
enum icl_port_dpll_id port_dpll_id;
@@ -4313,10 +4313,10 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
+ if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
else
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
+ crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
&crtc_state->dpll_hw_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 353eb04079e9..c18a69b2ae6d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -18,7 +18,7 @@ struct intel_display;
struct intel_dp;
struct intel_dpll_hw_state;
struct intel_encoder;
-struct intel_shared_dpll;
+struct intel_dpll;
enum pipe;
enum port;
enum transcoder;
@@ -40,7 +40,7 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder,
void intel_ddi_disable_clock(struct intel_encoder *encoder);
void intel_ddi_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
- struct intel_shared_dpll *pll);
+ struct intel_dpll *pll);
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void hsw_ddi_disable_clock(struct intel_encoder *encoder);
@@ -50,7 +50,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void hsw_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
-struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
+struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 287110e4e435..b765d5765b32 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1325,7 +1325,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
if (intel_crtc_needs_modeset(new_crtc_state))
continue;
- new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
+ new_crtc_state->intel_dpll = old_crtc_state->intel_dpll;
new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
}
}
@@ -1663,7 +1663,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_encoders_pre_pll_enable(state, crtc);
- if (new_crtc_state->shared_dpll)
+ if (new_crtc_state->intel_dpll)
intel_enable_shared_dpll(new_crtc_state);
intel_encoders_pre_enable(state, crtc);
@@ -1959,7 +1959,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
if (HAS_DDI(display) && crtc_state->has_audio)
set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
- if (crtc_state->shared_dpll)
+ if (crtc_state->intel_dpll)
set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
if (crtc_state->dsc.compression_enable)
@@ -4501,7 +4501,7 @@ copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
/* preserve some things from the slave's original crtc state */
saved_state->uapi = secondary_crtc_state->uapi;
saved_state->scaler_state = secondary_crtc_state->scaler_state;
- saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
+ saved_state->intel_dpll = secondary_crtc_state->intel_dpll;
saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
intel_crtc_free_hw_state(secondary_crtc_state);
@@ -4564,7 +4564,7 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
saved_state->uapi = crtc_state->uapi;
saved_state->inherited = crtc_state->inherited;
saved_state->scaler_state = crtc_state->scaler_state;
- saved_state->shared_dpll = crtc_state->shared_dpll;
+ saved_state->intel_dpll = crtc_state->intel_dpll;
saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
sizeof(saved_state->icl_port_dplls));
@@ -5318,7 +5318,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(double_wide);
if (display->dpll.mgr)
- PIPE_CONF_CHECK_P(shared_dpll);
+ PIPE_CONF_CHECK_P(intel_dpll);
/* FIXME convert everything over the dpll_mgr */
if (display->dpll.mgr || HAS_GMCH(display))
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index e0221e514326..3121a987d07b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -125,8 +125,8 @@ struct intel_audio {
struct intel_dpll_global {
struct mutex lock;
- int num_shared_dpll;
- struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
+ int num_intel_dpll;
+ struct intel_dpll intel_dplls[I915_NUM_PLLS];
const struct intel_dpll_mgr *mgr;
struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3770ce9469d1..ea9e271bc6ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -618,7 +618,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
{
struct intel_display *display = node_to_intel_display(m->private);
struct drm_printer p = drm_seq_file_printer(m);
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
int i;
drm_modeset_lock_all(display->drm);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1bdffaca153a..826af285e7fc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1075,8 +1075,8 @@ struct intel_crtc_state {
* haswell. */
struct dpll dpll;
- /* Selected dpll when shared or NULL. */
- struct intel_shared_dpll *shared_dpll;
+ /* Selected dpll. */
+ struct intel_dpll *intel_dpll;
/* Actual register state of the dpll, for shared dpll cross-checking. */
struct intel_dpll_hw_state dpll_hw_state;
@@ -1086,7 +1086,7 @@ struct intel_crtc_state {
* setting shared_dpll and dpll_hw_state to one of these reserved ones.
*/
struct icl_port_dpll {
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
struct intel_dpll_hw_state hw_state;
} icl_port_dplls[ICL_PORT_DPLL_COUNT];
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 8db603d9c823..4d1f7fccd28a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1767,9 +1767,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
int ret;
drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
- drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
+ drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->intel_dpll);
- if (!crtc_state->hw.enable || crtc_state->shared_dpll)
+ if (!crtc_state->hw.enable || crtc_state->intel_dpll)
return 0;
if (!display->funcs.dpll->crtc_get_shared_dpll)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index bdad4d72cc01..e63568be3150 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -70,7 +70,7 @@ struct intel_dpll_funcs {
* the pll is not already enabled.
*/
void (*enable)(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
/*
@@ -79,7 +79,7 @@ struct intel_dpll_funcs {
* tracked users for it.
*/
void (*disable)(struct intel_display *display,
- struct intel_shared_dpll *pll);
+ struct intel_dpll *pll);
/*
* Hook for reading the values currently programmed to the DPLL
@@ -87,7 +87,7 @@ struct intel_dpll_funcs {
* verification after a mode set.
*/
bool (*get_hw_state)(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
/*
@@ -95,7 +95,7 @@ struct intel_dpll_funcs {
* in state.
*/
int (*get_freq)(struct intel_display *i915,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
};
@@ -124,7 +124,7 @@ static void
intel_atomic_duplicate_dpll_state(struct intel_display *display,
struct intel_dpll_state *dpll_state)
{
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
int i;
/* Copy dpll state */
@@ -158,11 +158,11 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
* Returns:
* A pointer to the DPLL with @id
*/
-struct intel_shared_dpll *
+struct intel_dpll *
intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id)
{
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
int i;
for_each_dpll(display, pll, i) {
@@ -176,7 +176,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
/* For ILK+ */
void assert_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
bool state)
{
bool cur_state;
@@ -205,7 +205,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
static i915_reg_t
intel_combo_pll_enable_reg(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
if (display->platform.dg1)
return DG1_DPLL_ENABLE(pll->info->id);
@@ -218,7 +218,7 @@ intel_combo_pll_enable_reg(struct intel_display *display,
static i915_reg_t
intel_tc_pll_enable_reg(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -230,7 +230,7 @@ intel_tc_pll_enable_reg(struct intel_display *display,
}
static void _intel_enable_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
if (pll->info->power_domain)
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
@@ -240,7 +240,7 @@ static void _intel_enable_shared_dpll(struct intel_display *display,
}
static void _intel_disable_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
pll->info->funcs->disable(display, pll);
pll->on = false;
@@ -259,7 +259,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ struct intel_dpll *pll = crtc_state->intel_dpll;
unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
unsigned int old_mask;
@@ -305,7 +305,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ struct intel_dpll *pll = crtc_state->intel_dpll;
unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
/* PCH only available on ILK+ */
@@ -344,7 +344,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
static unsigned long
intel_dpll_mask_all(struct intel_display *display)
{
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
unsigned long dpll_mask = 0;
int i;
@@ -357,7 +357,7 @@ intel_dpll_mask_all(struct intel_display *display)
return dpll_mask;
}
-static struct intel_shared_dpll *
+static struct intel_dpll *
intel_find_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
const struct intel_dpll_hw_state *dpll_hw_state,
@@ -366,7 +366,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
struct intel_display *display = to_intel_display(crtc);
unsigned long dpll_mask_all = intel_dpll_mask_all(display);
struct intel_dpll_state *dpll_state;
- struct intel_shared_dpll *unused_pll = NULL;
+ struct intel_dpll *unused_pll = NULL;
enum intel_dpll_id id;
dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
@@ -374,7 +374,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
pll = intel_get_shared_dpll_by_id(display, id);
if (!pll)
@@ -421,7 +421,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
*/
static void
intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
@@ -437,7 +437,7 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
static void
intel_reference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_dpll_state *dpll_state;
@@ -460,7 +460,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
*/
void
intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
@@ -475,7 +475,7 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll)
+ const struct intel_dpll *pll)
{
struct intel_dpll_state *dpll_state;
@@ -492,12 +492,12 @@ static void intel_put_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- new_crtc_state->shared_dpll = NULL;
+ new_crtc_state->intel_dpll = NULL;
- if (!old_crtc_state->shared_dpll)
+ if (!old_crtc_state->intel_dpll)
return;
- intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
+ intel_unreference_shared_dpll(state, crtc, old_crtc_state->intel_dpll);
}
/**
@@ -515,7 +515,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct intel_dpll_state *dpll_state = state->dpll_state;
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
int i;
if (!state->dpll_set)
@@ -526,7 +526,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
}
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
@@ -562,7 +562,7 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
}
static void ibx_pch_dpll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
@@ -591,7 +591,7 @@ static void ibx_pch_dpll_enable(struct intel_display *display,
}
static void ibx_pch_dpll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
@@ -614,7 +614,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
enum intel_dpll_id id;
if (HAS_PCH_IBX(display)) {
@@ -640,7 +640,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->intel_dpll = pll;
return 0;
}
@@ -692,7 +692,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
};
static void hsw_ddi_wrpll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -704,7 +704,7 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display,
}
static void hsw_ddi_spll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -715,7 +715,7 @@ static void hsw_ddi_spll_enable(struct intel_display *display,
}
static void hsw_ddi_wrpll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
const enum intel_dpll_id id = pll->info->id;
@@ -731,7 +731,7 @@ static void hsw_ddi_wrpll_disable(struct intel_display *display,
}
static void hsw_ddi_spll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
enum intel_dpll_id id = pll->info->id;
@@ -747,7 +747,7 @@ static void hsw_ddi_spll_disable(struct intel_display *display,
}
static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -769,7 +769,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
}
static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -996,7 +996,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
}
static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -1059,7 +1059,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
return 0;
}
-static struct intel_shared_dpll *
+static struct intel_dpll *
hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1090,11 +1090,11 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
}
}
-static struct intel_shared_dpll *
+static struct intel_dpll *
hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
enum intel_dpll_id pll_id;
int clock = crtc_state->port_clock;
@@ -1122,7 +1122,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
}
static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
int link_clock = 0;
@@ -1162,7 +1162,7 @@ hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
return 0;
}
-static struct intel_shared_dpll *
+static struct intel_dpll *
hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1174,7 +1174,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
}
static int hsw_ddi_spll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
@@ -1221,7 +1221,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll = NULL;
+ struct intel_dpll *pll = NULL;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
pll = hsw_ddi_wrpll_get_dpll(state, crtc);
@@ -1236,7 +1236,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->intel_dpll = pll;
return 0;
}
@@ -1285,18 +1285,18 @@ static const struct intel_dpll_funcs hsw_ddi_spll_funcs = {
};
static void hsw_ddi_lcpll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *hw_state)
{
}
static void hsw_ddi_lcpll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
}
static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
return true;
@@ -1364,7 +1364,7 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
};
static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct skl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
@@ -1378,7 +1378,7 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
}
static void skl_ddi_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1400,7 +1400,7 @@ static void skl_ddi_pll_enable(struct intel_display *display,
}
static void skl_ddi_dpll0_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1409,7 +1409,7 @@ static void skl_ddi_dpll0_enable(struct intel_display *display,
}
static void skl_ddi_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1420,12 +1420,12 @@ static void skl_ddi_pll_disable(struct intel_display *display,
}
static void skl_ddi_dpll0_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
}
static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1463,7 +1463,7 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
}
static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1736,7 +1736,7 @@ skl_ddi_calculate_wrpll(int clock,
}
static int skl_ddi_wrpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1884,7 +1884,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
}
static int skl_ddi_lcpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -1939,7 +1939,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
pll = intel_find_shared_dpll(state, crtc,
@@ -1957,13 +1957,13 @@ static int skl_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->intel_dpll = pll;
return 0;
}
static int skl_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
@@ -2038,7 +2038,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
};
static void bxt_ddi_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
@@ -2141,7 +2141,7 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
}
static void bxt_ddi_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
@@ -2160,7 +2160,7 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
}
static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
@@ -2360,7 +2360,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
}
static int bxt_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
@@ -2429,7 +2429,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
enum intel_dpll_id id;
/* 1:1 mapping between ports and PLLs */
@@ -2442,7 +2442,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
intel_reference_shared_dpll(state, crtc,
pll, &crtc_state->dpll_hw_state);
- crtc_state->shared_dpll = pll;
+ crtc_state->intel_dpll = pll;
return 0;
}
@@ -2755,7 +2755,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
}
static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
/*
@@ -2826,7 +2826,7 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
}
static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3199,7 +3199,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
}
static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3285,7 +3285,7 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
struct icl_port_dpll *port_dpll =
&crtc_state->icl_port_dplls[port_dpll_id];
- crtc_state->shared_dpll = port_dpll->pll;
+ crtc_state->intel_dpll = port_dpll->pll;
crtc_state->dpll_hw_state = port_dpll->hw_state;
}
@@ -3428,8 +3428,8 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
return ret;
/* this is mainly for the fastset check */
- if (old_crtc_state->shared_dpll &&
- old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
+ if (old_crtc_state->intel_dpll &&
+ old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
else
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
@@ -3521,7 +3521,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
enum icl_port_dpll_id id;
- new_crtc_state->shared_dpll = NULL;
+ new_crtc_state->intel_dpll = NULL;
for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
const struct icl_port_dpll *old_port_dpll =
@@ -3539,7 +3539,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
}
static bool mg_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3606,7 +3606,7 @@ static bool mg_pll_get_hw_state(struct intel_display *display,
}
static bool dkl_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3678,7 +3678,7 @@ static bool dkl_pll_get_hw_state(struct intel_display *display,
}
static bool icl_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state,
i915_reg_t enable_reg)
{
@@ -3739,7 +3739,7 @@ static bool icl_pll_get_hw_state(struct intel_display *display,
}
static bool combo_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
@@ -3748,14 +3748,14 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
}
static bool tbt_pll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
}
static void icl_dpll_write(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
const enum intel_dpll_id id = pll->info->id;
@@ -3797,7 +3797,7 @@ static void icl_dpll_write(struct intel_display *display,
}
static void icl_mg_pll_write(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
@@ -3840,7 +3840,7 @@ static void icl_mg_pll_write(struct intel_display *display,
}
static void dkl_pll_write(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct icl_dpll_hw_state *hw_state)
{
enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
@@ -3905,7 +3905,7 @@ static void dkl_pll_write(struct intel_display *display,
}
static void icl_pll_power_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
i915_reg_t enable_reg)
{
intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
@@ -3920,7 +3920,7 @@ static void icl_pll_power_enable(struct intel_display *display,
}
static void icl_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
i915_reg_t enable_reg)
{
intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
@@ -3930,7 +3930,7 @@ static void icl_pll_enable(struct intel_display *display,
drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
}
-static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll)
+static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll *pll)
{
u32 val;
@@ -3955,7 +3955,7 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte
}
static void combo_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -3979,7 +3979,7 @@ static void combo_pll_enable(struct intel_display *display,
}
static void tbt_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -4000,7 +4000,7 @@ static void tbt_pll_enable(struct intel_display *display,
}
static void mg_pll_enable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
@@ -4025,7 +4025,7 @@ static void mg_pll_enable(struct intel_display *display,
}
static void icl_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
i915_reg_t enable_reg)
{
/* The first steps are done by intel_ddi_post_disable(). */
@@ -4056,7 +4056,7 @@ static void icl_pll_disable(struct intel_display *display,
}
static void combo_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
@@ -4064,13 +4064,13 @@ static void combo_pll_disable(struct intel_display *display,
}
static void tbt_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
icl_pll_disable(display, pll, TBT_PLL_ENABLE);
}
static void mg_pll_disable(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
@@ -4346,19 +4346,19 @@ void intel_shared_dpll_init(struct intel_display *display)
for (i = 0; dpll_info[i].name; i++) {
if (drm_WARN_ON(display->drm,
- i >= ARRAY_SIZE(display->dpll.shared_dplls)))
+ i >= ARRAY_SIZE(display->dpll.intel_dplls)))
break;
/* must fit into unsigned long bitmask on 32bit */
if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
break;
- display->dpll.shared_dplls[i].info = &dpll_info[i];
- display->dpll.shared_dplls[i].index = i;
+ display->dpll.intel_dplls[i].info = &dpll_info[i];
+ display->dpll.intel_dplls[i].index = i;
}
display->dpll.mgr = dpll_mgr;
- display->dpll.num_shared_dpll = i;
+ display->dpll.num_intel_dpll = i;
}
/**
@@ -4482,7 +4482,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
* Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
*/
int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
@@ -4500,14 +4500,14 @@ int intel_dpll_get_freq(struct intel_display *display,
* Read out @pll's hardware state into @dpll_hw_state.
*/
bool intel_dpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
}
static void readout_dpll_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
struct intel_crtc *crtc;
@@ -4521,7 +4521,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
- if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
+ if (crtc_state->hw.active && crtc_state->intel_dpll == pll)
intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
}
pll->active_mask = pll->state.pipe_mask;
@@ -4539,7 +4539,7 @@ void intel_dpll_update_ref_clks(struct intel_display *display)
void intel_dpll_readout_hw_state(struct intel_display *display)
{
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
int i;
for_each_dpll(display, pll, i)
@@ -4547,7 +4547,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display)
}
static void sanitize_dpll_state(struct intel_display *display,
- struct intel_shared_dpll *pll)
+ struct intel_dpll *pll)
{
if (!pll->on)
return;
@@ -4566,7 +4566,7 @@ static void sanitize_dpll_state(struct intel_display *display,
void intel_dpll_sanitize_state(struct intel_display *display)
{
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
int i;
intel_cx0_pll_power_save_wa(display);
@@ -4623,7 +4623,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
static void
verify_single_dpll_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_crtc *crtc,
const struct intel_crtc_state *new_crtc_state)
{
@@ -4676,8 +4676,8 @@ verify_single_dpll_state(struct intel_display *display,
pll->info->name);
}
-static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
- const struct intel_shared_dpll *new_pll)
+static bool has_alt_port_dpll(const struct intel_dpll *old_pll,
+ const struct intel_dpll *new_pll)
{
return old_pll && new_pll && old_pll != new_pll &&
(old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
@@ -4692,22 +4692,22 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- if (new_crtc_state->shared_dpll)
- verify_single_dpll_state(display, new_crtc_state->shared_dpll,
+ if (new_crtc_state->intel_dpll)
+ verify_single_dpll_state(display, new_crtc_state->intel_dpll,
crtc, new_crtc_state);
- if (old_crtc_state->shared_dpll &&
- old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
+ if (old_crtc_state->intel_dpll &&
+ old_crtc_state->intel_dpll != new_crtc_state->intel_dpll) {
u8 pipe_mask = BIT(crtc->pipe);
- struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
+ struct intel_dpll *pll = old_crtc_state->intel_dpll;
INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
"%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
/* TC ports have both MG/TC and TBT PLL referenced simultaneously */
- INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll,
- new_crtc_state->shared_dpll) &&
+ INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->intel_dpll,
+ new_crtc_state->intel_dpll) &&
pll->state.pipe_mask & pipe_mask,
"%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
@@ -4717,7 +4717,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
int i;
for_each_dpll(display, pll, i)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 658174b99db3..3604ebbc78b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -31,8 +31,8 @@
#include "intel_wakeref.h"
#define for_each_dpll(__display, __pll, __i) \
- for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
- ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
+ for ((__i) = 0; (__i) < (__display)->dpll.num_intel_dpll && \
+ ((__pll) = &(__display)->dpll.intel_dplls[(__i)]) ; (__i)++)
enum tc_port;
struct drm_printer;
@@ -344,9 +344,9 @@ struct dpll_info {
};
/**
- * struct intel_shared_dpll - display PLL with tracked state and users
+ * struct intel_dpll - display PLL with tracked state and users
*/
-struct intel_shared_dpll {
+struct intel_dpll {
/**
* @state:
*
@@ -388,11 +388,11 @@ struct intel_shared_dpll {
#define SKL_DPLL3 3
/* shared dpll functions */
-struct intel_shared_dpll *
+struct intel_dpll *
intel_get_shared_dpll_by_id(struct intel_display *display,
enum intel_dpll_id id);
void assert_shared_dpll(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
@@ -405,7 +405,7 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
enum icl_port_dpll_id port_dpll_id);
@@ -413,10 +413,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_shared_dpll *pll,
+ const struct intel_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state);
bool intel_dpll_get_hw_state(struct intel_display *display,
- struct intel_shared_dpll *pll,
+ struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 169bbe154b5c..b1d2ba9b7295 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -910,7 +910,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
/* Configure Port Clock Select */
- drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
+ drm_WARN_ON(display->drm, crtc_state->intel_dpll->info->id != DPLL_ID_SPLL);
intel_ddi_enable_clock(encoder, crtc_state);
/* Start the training iterating through available voltages and emphasis,
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 8ce7c630da52..ec8f38fba178 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -249,7 +249,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
if (HAS_PCH_SPLIT(display)) {
assert_fdi_rx_pll_disabled(display, pipe);
- assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
+ assert_shared_dpll_disabled(display, crtc_state->intel_dpll);
} else {
assert_pll_disabled(display, pipe);
}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 0325b0c9506d..46e0002a1358 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -92,10 +92,10 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
crtc->active = false;
crtc->base.enabled = false;
- if (crtc_state->shared_dpll)
+ if (crtc_state->intel_dpll)
intel_unreference_shared_dpll_crtc(crtc,
- crtc_state->shared_dpll,
- &crtc_state->shared_dpll->state);
+ crtc_state->intel_dpll,
+ &crtc_state->intel_dpll->state);
}
static void set_encoder_for_connector(struct intel_connector *connector,
@@ -565,7 +565,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
*/
return display->platform.sandybridge &&
crtc_state->hw.active &&
- crtc_state->shared_dpll &&
+ crtc_state->intel_dpll &&
crtc_state->port_clock == 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 1743ebf551cb..b38305c16e77 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -251,7 +251,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
u32 val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
- assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
+ assert_shared_dpll_enabled(display, crtc_state->intel_dpll);
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(display, pipe);
@@ -381,7 +381,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp = intel_de_read(display, PCH_DPLL_SEL);
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
- if (crtc_state->shared_dpll ==
+ if (crtc_state->intel_dpll ==
intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
temp |= sel;
else
@@ -496,7 +496,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
enum pipe pipe = crtc->pipe;
enum intel_dpll_id pll_id;
bool pll_active;
@@ -528,8 +528,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
pll_id = DPLL_ID_PCH_PLL_A;
}
- crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
- pll = crtc_state->shared_dpll;
+ crtc_state->intel_dpll = intel_get_shared_dpll_by_id(display, pll_id);
+ pll = crtc_state->intel_dpll;
pll_active = intel_dpll_get_hw_state(display, pll,
&crtc_state->dpll_hw_state);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 8bec55deff9f..9f6102d7c7be 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -499,7 +499,7 @@ static void lpt_init_pch_refclk(struct intel_display *display)
static void ilk_init_pch_refclk(struct intel_display *display)
{
struct intel_encoder *encoder;
- struct intel_shared_dpll *pll;
+ struct intel_dpll *pll;
int i;
u32 val, final;
bool has_lvds = false;
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 06/18] drm/i915/dpll: Rename intel_shared_dpll
2025-05-09 4:27 ` [PATCH 06/18] drm/i915/dpll: Rename intel_shared_dpll Suraj Kandpal
@ 2025-05-09 10:13 ` Jani Nikula
2025-05-12 4:00 ` Kandpal, Suraj
0 siblings, 1 reply; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:13 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_shared_dpll to intel_dpll to represent both
> shared and individual dplls. Since from MTL each PHY has it's
> own PLL making the shared PLL naming a little outdated. In an
> effort to make this framework accepting of future changes this
> needs to be done.
>
> --v2
> -Use intel_dpll_global to make sure names start with the filename
> [Jani/Ville]
> -Explain the need of this rename [Jani]
>
> --v3
> -Just keep it intel_dpll [Jani]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 52 ++--
> drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> drivers/gpu/drm/i915/display/intel_display.c | 12 +-
> .../gpu/drm/i915/display/intel_display_core.h | 4 +-
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> .../drm/i915/display/intel_display_types.h | 6 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 228 +++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 18 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> .../drm/i915/display/intel_modeset_setup.c | 8 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 10 +-
> .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
> 15 files changed, 179 insertions(+), 179 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ca7033251e91..55f0a20e0874 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -658,7 +658,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
> {
> struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> enum phy phy;
> u32 val;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 74132c1d6385..4d631cbc81d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -236,7 +236,7 @@ static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
> port_name(port));
> }
>
> -static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> +static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll)
> {
> switch (pll->info->id) {
> case DPLL_ID_WRPLL1:
> @@ -260,7 +260,7 @@ static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll *pll = crtc_state->intel_dpll;
> int clock = crtc_state->port_clock;
> const enum intel_dpll_id id = pll->info->id;
>
> @@ -1561,7 +1561,7 @@ static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t
> return !(intel_de_read(display, reg) & clk_off);
> }
>
> -static struct intel_shared_dpll *
> +static struct intel_dpll *
> _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
> u32 clk_sel_mask, u32 clk_sel_shift)
> {
> @@ -1576,7 +1576,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll *pll = crtc_state->intel_dpll;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1606,7 +1606,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> -static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> @@ -1620,7 +1620,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll *pll = crtc_state->intel_dpll;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1650,7 +1650,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
> RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> -static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> @@ -1664,7 +1664,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll *pll = crtc_state->intel_dpll;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1703,7 +1703,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
> DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> -static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> @@ -1730,7 +1730,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll *pll = crtc_state->intel_dpll;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1760,7 +1760,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
> +struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> @@ -1774,7 +1774,7 @@ static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll *pll = crtc_state->intel_dpll;
> enum port port = encoder->port;
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1817,7 +1817,7 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll *pll = crtc_state->intel_dpll;
> enum tc_port tc_port = intel_encoder_to_tc(encoder);
> enum port port = encoder->port;
>
> @@ -1868,7 +1868,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
> return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
> }
>
> -static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum tc_port tc_port = intel_encoder_to_tc(encoder);
> @@ -1898,7 +1898,7 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
> return intel_get_shared_dpll_by_id(display, id);
> }
>
> -static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder->base.dev);
> enum intel_dpll_id id;
> @@ -1925,7 +1925,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll *pll = crtc_state->intel_dpll;
> enum port port = encoder->port;
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -1967,7 +1967,7 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
> return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
> }
>
> -static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> @@ -1993,7 +1993,7 @@ void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll *pll = crtc_state->intel_dpll;
> enum port port = encoder->port;
>
> if (drm_WARN_ON(display->drm, !pll))
> @@ -2018,7 +2018,7 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
> return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
> }
>
> -static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
> +static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> @@ -4187,7 +4187,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
>
> void intel_ddi_get_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> @@ -4203,7 +4203,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
>
> icl_set_active_port_dpll(crtc_state, port_dpll_id);
>
> - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
> + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
> &crtc_state->dpll_hw_state);
> }
>
> @@ -4257,7 +4257,7 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
> intel_ddi_get_config(encoder, crtc_state);
> }
>
> -static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
> +static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
> {
> return pll->info->id == DPLL_ID_ICL_TBTPLL;
> }
> @@ -4267,7 +4267,7 @@ icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(encoder);
> - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + const struct intel_dpll *pll = crtc_state->intel_dpll;
>
> if (drm_WARN_ON(display->drm, !pll))
> return ICL_PORT_DPLL_DEFAULT;
> @@ -4290,7 +4290,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
>
> static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> struct intel_display *display = to_intel_display(encoder);
> enum icl_port_dpll_id port_dpll_id;
> @@ -4313,10 +4313,10 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
>
> icl_set_active_port_dpll(crtc_state, port_dpll_id);
>
> - if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
> + if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
> crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
> else
> - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
> + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
> &crtc_state->dpll_hw_state);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 353eb04079e9..c18a69b2ae6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -18,7 +18,7 @@ struct intel_display;
> struct intel_dp;
> struct intel_dpll_hw_state;
> struct intel_encoder;
> -struct intel_shared_dpll;
> +struct intel_dpll;
Nitpick, these should remain sorted.
> enum pipe;
> enum port;
> enum transcoder;
> @@ -40,7 +40,7 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder,
> void intel_ddi_disable_clock(struct intel_encoder *encoder);
> void intel_ddi_get_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> - struct intel_shared_dpll *pll);
> + struct intel_dpll *pll);
> void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void hsw_ddi_disable_clock(struct intel_encoder *encoder);
> @@ -50,7 +50,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void hsw_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
> -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
> +struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
> void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 287110e4e435..b765d5765b32 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1325,7 +1325,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
> if (intel_crtc_needs_modeset(new_crtc_state))
> continue;
>
> - new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
> + new_crtc_state->intel_dpll = old_crtc_state->intel_dpll;
> new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
> }
> }
> @@ -1663,7 +1663,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
>
> intel_encoders_pre_pll_enable(state, crtc);
>
> - if (new_crtc_state->shared_dpll)
> + if (new_crtc_state->intel_dpll)
> intel_enable_shared_dpll(new_crtc_state);
>
> intel_encoders_pre_enable(state, crtc);
> @@ -1959,7 +1959,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> if (HAS_DDI(display) && crtc_state->has_audio)
> set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
>
> - if (crtc_state->shared_dpll)
> + if (crtc_state->intel_dpll)
> set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
>
> if (crtc_state->dsc.compression_enable)
> @@ -4501,7 +4501,7 @@ copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
> /* preserve some things from the slave's original crtc state */
> saved_state->uapi = secondary_crtc_state->uapi;
> saved_state->scaler_state = secondary_crtc_state->scaler_state;
> - saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
> + saved_state->intel_dpll = secondary_crtc_state->intel_dpll;
> saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
>
> intel_crtc_free_hw_state(secondary_crtc_state);
> @@ -4564,7 +4564,7 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
> saved_state->uapi = crtc_state->uapi;
> saved_state->inherited = crtc_state->inherited;
> saved_state->scaler_state = crtc_state->scaler_state;
> - saved_state->shared_dpll = crtc_state->shared_dpll;
> + saved_state->intel_dpll = crtc_state->intel_dpll;
> saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
> sizeof(saved_state->icl_port_dplls));
> @@ -5318,7 +5318,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_BOOL(double_wide);
>
> if (display->dpll.mgr)
> - PIPE_CONF_CHECK_P(shared_dpll);
> + PIPE_CONF_CHECK_P(intel_dpll);
>
> /* FIXME convert everything over the dpll_mgr */
> if (display->dpll.mgr || HAS_GMCH(display))
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index e0221e514326..3121a987d07b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -125,8 +125,8 @@ struct intel_audio {
> struct intel_dpll_global {
> struct mutex lock;
>
> - int num_shared_dpll;
> - struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
> + int num_intel_dpll;
> + struct intel_dpll intel_dplls[I915_NUM_PLLS];
I don't think we have any cases where struct members would be prefixed
intel_. I think this should be just num_dpll and dplls.
With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> const struct intel_dpll_mgr *mgr;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3770ce9469d1..ea9e271bc6ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -618,7 +618,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
> {
> struct intel_display *display = node_to_intel_display(m->private);
> struct drm_printer p = drm_seq_file_printer(m);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> int i;
>
> drm_modeset_lock_all(display->drm);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1bdffaca153a..826af285e7fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1075,8 +1075,8 @@ struct intel_crtc_state {
> * haswell. */
> struct dpll dpll;
>
> - /* Selected dpll when shared or NULL. */
> - struct intel_shared_dpll *shared_dpll;
> + /* Selected dpll. */
Or NULL?
> + struct intel_dpll *intel_dpll;
>
> /* Actual register state of the dpll, for shared dpll cross-checking. */
> struct intel_dpll_hw_state dpll_hw_state;
> @@ -1086,7 +1086,7 @@ struct intel_crtc_state {
> * setting shared_dpll and dpll_hw_state to one of these reserved ones.
> */
> struct icl_port_dpll {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> struct intel_dpll_hw_state hw_state;
> } icl_port_dplls[ICL_PORT_DPLL_COUNT];
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 8db603d9c823..4d1f7fccd28a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1767,9 +1767,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> int ret;
>
> drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
> - drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
> + drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state->intel_dpll);
>
> - if (!crtc_state->hw.enable || crtc_state->shared_dpll)
> + if (!crtc_state->hw.enable || crtc_state->intel_dpll)
> return 0;
>
> if (!display->funcs.dpll->crtc_get_shared_dpll)
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index bdad4d72cc01..e63568be3150 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -70,7 +70,7 @@ struct intel_dpll_funcs {
> * the pll is not already enabled.
> */
> void (*enable)(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state);
>
> /*
> @@ -79,7 +79,7 @@ struct intel_dpll_funcs {
> * tracked users for it.
> */
> void (*disable)(struct intel_display *display,
> - struct intel_shared_dpll *pll);
> + struct intel_dpll *pll);
>
> /*
> * Hook for reading the values currently programmed to the DPLL
> @@ -87,7 +87,7 @@ struct intel_dpll_funcs {
> * verification after a mode set.
> */
> bool (*get_hw_state)(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state);
>
> /*
> @@ -95,7 +95,7 @@ struct intel_dpll_funcs {
> * in state.
> */
> int (*get_freq)(struct intel_display *i915,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state);
> };
>
> @@ -124,7 +124,7 @@ static void
> intel_atomic_duplicate_dpll_state(struct intel_display *display,
> struct intel_dpll_state *dpll_state)
> {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> int i;
>
> /* Copy dpll state */
> @@ -158,11 +158,11 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> * Returns:
> * A pointer to the DPLL with @id
> */
> -struct intel_shared_dpll *
> +struct intel_dpll *
> intel_get_shared_dpll_by_id(struct intel_display *display,
> enum intel_dpll_id id)
> {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> int i;
>
> for_each_dpll(display, pll, i) {
> @@ -176,7 +176,7 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
>
> /* For ILK+ */
> void assert_shared_dpll(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> bool state)
> {
> bool cur_state;
> @@ -205,7 +205,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
>
> static i915_reg_t
> intel_combo_pll_enable_reg(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> if (display->platform.dg1)
> return DG1_DPLL_ENABLE(pll->info->id);
> @@ -218,7 +218,7 @@ intel_combo_pll_enable_reg(struct intel_display *display,
>
> static i915_reg_t
> intel_tc_pll_enable_reg(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
> enum tc_port tc_port = icl_pll_id_to_tc_port(id);
> @@ -230,7 +230,7 @@ intel_tc_pll_enable_reg(struct intel_display *display,
> }
>
> static void _intel_enable_shared_dpll(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> if (pll->info->power_domain)
> pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
> @@ -240,7 +240,7 @@ static void _intel_enable_shared_dpll(struct intel_display *display,
> }
>
> static void _intel_disable_shared_dpll(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> pll->info->funcs->disable(display, pll);
> pll->on = false;
> @@ -259,7 +259,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
> unsigned int old_mask;
>
> @@ -305,7 +305,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
>
> /* PCH only available on ILK+ */
> @@ -344,7 +344,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> static unsigned long
> intel_dpll_mask_all(struct intel_display *display)
> {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> unsigned long dpll_mask = 0;
> int i;
>
> @@ -357,7 +357,7 @@ intel_dpll_mask_all(struct intel_display *display)
> return dpll_mask;
> }
>
> -static struct intel_shared_dpll *
> +static struct intel_dpll *
> intel_find_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> const struct intel_dpll_hw_state *dpll_hw_state,
> @@ -366,7 +366,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> struct intel_display *display = to_intel_display(crtc);
> unsigned long dpll_mask_all = intel_dpll_mask_all(display);
> struct intel_dpll_state *dpll_state;
> - struct intel_shared_dpll *unused_pll = NULL;
> + struct intel_dpll *unused_pll = NULL;
> enum intel_dpll_id id;
>
> dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> @@ -374,7 +374,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
>
> for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
>
> pll = intel_get_shared_dpll_by_id(display, id);
> if (!pll)
> @@ -421,7 +421,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> */
> static void
> intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> struct intel_dpll_state *dpll_state)
> {
> struct intel_display *display = to_intel_display(crtc);
> @@ -437,7 +437,7 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> static void
> intel_reference_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct intel_dpll_state *dpll_state;
> @@ -460,7 +460,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
> */
> void
> intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> struct intel_dpll_state *dpll_state)
> {
> struct intel_display *display = to_intel_display(crtc);
> @@ -475,7 +475,7 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
>
> static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> const struct intel_crtc *crtc,
> - const struct intel_shared_dpll *pll)
> + const struct intel_dpll *pll)
> {
> struct intel_dpll_state *dpll_state;
>
> @@ -492,12 +492,12 @@ static void intel_put_dpll(struct intel_atomic_state *state,
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - new_crtc_state->shared_dpll = NULL;
> + new_crtc_state->intel_dpll = NULL;
>
> - if (!old_crtc_state->shared_dpll)
> + if (!old_crtc_state->intel_dpll)
> return;
>
> - intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
> + intel_unreference_shared_dpll(state, crtc, old_crtc_state->intel_dpll);
> }
>
> /**
> @@ -515,7 +515,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> {
> struct intel_display *display = to_intel_display(state);
> struct intel_dpll_state *dpll_state = state->dpll_state;
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> int i;
>
> if (!state->dpll_set)
> @@ -526,7 +526,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> }
>
> static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> @@ -562,7 +562,7 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
> }
>
> static void ibx_pch_dpll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> @@ -591,7 +591,7 @@ static void ibx_pch_dpll_enable(struct intel_display *display,
> }
>
> static void ibx_pch_dpll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
>
> @@ -614,7 +614,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
> struct intel_display *display = to_intel_display(state);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> enum intel_dpll_id id;
>
> if (HAS_PCH_IBX(display)) {
> @@ -640,7 +640,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
> intel_reference_shared_dpll(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> - crtc_state->shared_dpll = pll;
> + crtc_state->intel_dpll = pll;
>
> return 0;
> }
> @@ -692,7 +692,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
> };
>
> static void hsw_ddi_wrpll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -704,7 +704,7 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display,
> }
>
> static void hsw_ddi_spll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -715,7 +715,7 @@ static void hsw_ddi_spll_enable(struct intel_display *display,
> }
>
> static void hsw_ddi_wrpll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> const enum intel_dpll_id id = pll->info->id;
>
> @@ -731,7 +731,7 @@ static void hsw_ddi_wrpll_disable(struct intel_display *display,
> }
>
> static void hsw_ddi_spll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> enum intel_dpll_id id = pll->info->id;
>
> @@ -747,7 +747,7 @@ static void hsw_ddi_spll_disable(struct intel_display *display,
> }
>
> static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -769,7 +769,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
> }
>
> static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -996,7 +996,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
> }
>
> static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -1059,7 +1059,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
> return 0;
> }
>
> -static struct intel_shared_dpll *
> +static struct intel_dpll *
> hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -1090,11 +1090,11 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
> }
> }
>
> -static struct intel_shared_dpll *
> +static struct intel_dpll *
> hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> enum intel_dpll_id pll_id;
> int clock = crtc_state->port_clock;
>
> @@ -1122,7 +1122,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> }
>
> static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> int link_clock = 0;
> @@ -1162,7 +1162,7 @@ hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
> return 0;
> }
>
> -static struct intel_shared_dpll *
> +static struct intel_dpll *
> hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -1174,7 +1174,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> }
>
> static int hsw_ddi_spll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> @@ -1221,7 +1221,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_shared_dpll *pll = NULL;
> + struct intel_dpll *pll = NULL;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> pll = hsw_ddi_wrpll_get_dpll(state, crtc);
> @@ -1236,7 +1236,7 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
> intel_reference_shared_dpll(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> - crtc_state->shared_dpll = pll;
> + crtc_state->intel_dpll = pll;
>
> return 0;
> }
> @@ -1285,18 +1285,18 @@ static const struct intel_dpll_funcs hsw_ddi_spll_funcs = {
> };
>
> static void hsw_ddi_lcpll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *hw_state)
> {
> }
>
> static void hsw_ddi_lcpll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> }
>
> static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> return true;
> @@ -1364,7 +1364,7 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
> };
>
> static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct skl_dpll_hw_state *hw_state)
> {
> const enum intel_dpll_id id = pll->info->id;
> @@ -1378,7 +1378,7 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
> }
>
> static void skl_ddi_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1400,7 +1400,7 @@ static void skl_ddi_pll_enable(struct intel_display *display,
> }
>
> static void skl_ddi_dpll0_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1409,7 +1409,7 @@ static void skl_ddi_dpll0_enable(struct intel_display *display,
> }
>
> static void skl_ddi_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> const struct skl_dpll_regs *regs = skl_dpll_regs;
> const enum intel_dpll_id id = pll->info->id;
> @@ -1420,12 +1420,12 @@ static void skl_ddi_pll_disable(struct intel_display *display,
> }
>
> static void skl_ddi_dpll0_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> }
>
> static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1463,7 +1463,7 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
> }
>
> static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1736,7 +1736,7 @@ skl_ddi_calculate_wrpll(int clock,
> }
>
> static int skl_ddi_wrpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1884,7 +1884,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> }
>
> static int skl_ddi_lcpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -1939,7 +1939,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> pll = intel_find_shared_dpll(state, crtc,
> @@ -1957,13 +1957,13 @@ static int skl_get_dpll(struct intel_atomic_state *state,
> intel_reference_shared_dpll(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> - crtc_state->shared_dpll = pll;
> + crtc_state->intel_dpll = pll;
>
> return 0;
> }
>
> static int skl_ddi_pll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> @@ -2038,7 +2038,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
> };
>
> static void bxt_ddi_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> @@ -2141,7 +2141,7 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
> }
>
> static void bxt_ddi_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
>
> @@ -2160,7 +2160,7 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
> }
>
> static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> @@ -2360,7 +2360,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> }
>
> static int bxt_ddi_pll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> @@ -2429,7 +2429,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
> struct intel_display *display = to_intel_display(state);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> enum intel_dpll_id id;
>
> /* 1:1 mapping between ports and PLLs */
> @@ -2442,7 +2442,7 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
> intel_reference_shared_dpll(state, crtc,
> pll, &crtc_state->dpll_hw_state);
>
> - crtc_state->shared_dpll = pll;
> + crtc_state->intel_dpll = pll;
>
> return 0;
> }
> @@ -2755,7 +2755,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> }
>
> static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> /*
> @@ -2826,7 +2826,7 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
> }
>
> static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -3199,7 +3199,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> }
>
> static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -3285,7 +3285,7 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> struct icl_port_dpll *port_dpll =
> &crtc_state->icl_port_dplls[port_dpll_id];
>
> - crtc_state->shared_dpll = port_dpll->pll;
> + crtc_state->intel_dpll = port_dpll->pll;
> crtc_state->dpll_hw_state = port_dpll->hw_state;
> }
>
> @@ -3428,8 +3428,8 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> return ret;
>
> /* this is mainly for the fastset check */
> - if (old_crtc_state->shared_dpll &&
> - old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> + if (old_crtc_state->intel_dpll &&
> + old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> else
> icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
> @@ -3521,7 +3521,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> enum icl_port_dpll_id id;
>
> - new_crtc_state->shared_dpll = NULL;
> + new_crtc_state->intel_dpll = NULL;
>
> for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
> const struct icl_port_dpll *old_port_dpll =
> @@ -3539,7 +3539,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
> }
>
> static bool mg_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -3606,7 +3606,7 @@ static bool mg_pll_get_hw_state(struct intel_display *display,
> }
>
> static bool dkl_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -3678,7 +3678,7 @@ static bool dkl_pll_get_hw_state(struct intel_display *display,
> }
>
> static bool icl_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state,
> i915_reg_t enable_reg)
> {
> @@ -3739,7 +3739,7 @@ static bool icl_pll_get_hw_state(struct intel_display *display,
> }
>
> static bool combo_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
> @@ -3748,14 +3748,14 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
> }
>
> static bool tbt_pll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
> }
>
> static void icl_dpll_write(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct icl_dpll_hw_state *hw_state)
> {
> const enum intel_dpll_id id = pll->info->id;
> @@ -3797,7 +3797,7 @@ static void icl_dpll_write(struct intel_display *display,
> }
>
> static void icl_mg_pll_write(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct icl_dpll_hw_state *hw_state)
> {
> enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
> @@ -3840,7 +3840,7 @@ static void icl_mg_pll_write(struct intel_display *display,
> }
>
> static void dkl_pll_write(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct icl_dpll_hw_state *hw_state)
> {
> enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
> @@ -3905,7 +3905,7 @@ static void dkl_pll_write(struct intel_display *display,
> }
>
> static void icl_pll_power_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> i915_reg_t enable_reg)
> {
> intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
> @@ -3920,7 +3920,7 @@ static void icl_pll_power_enable(struct intel_display *display,
> }
>
> static void icl_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> i915_reg_t enable_reg)
> {
> intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
> @@ -3930,7 +3930,7 @@ static void icl_pll_enable(struct intel_display *display,
> drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
> }
>
> -static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll)
> +static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_dpll *pll)
> {
> u32 val;
>
> @@ -3955,7 +3955,7 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte
> }
>
> static void combo_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -3979,7 +3979,7 @@ static void combo_pll_enable(struct intel_display *display,
> }
>
> static void tbt_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -4000,7 +4000,7 @@ static void tbt_pll_enable(struct intel_display *display,
> }
>
> static void mg_pll_enable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> @@ -4025,7 +4025,7 @@ static void mg_pll_enable(struct intel_display *display,
> }
>
> static void icl_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> i915_reg_t enable_reg)
> {
> /* The first steps are done by intel_ddi_post_disable(). */
> @@ -4056,7 +4056,7 @@ static void icl_pll_disable(struct intel_display *display,
> }
>
> static void combo_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
>
> @@ -4064,13 +4064,13 @@ static void combo_pll_disable(struct intel_display *display,
> }
>
> static void tbt_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> icl_pll_disable(display, pll, TBT_PLL_ENABLE);
> }
>
> static void mg_pll_disable(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
>
> @@ -4346,19 +4346,19 @@ void intel_shared_dpll_init(struct intel_display *display)
>
> for (i = 0; dpll_info[i].name; i++) {
> if (drm_WARN_ON(display->drm,
> - i >= ARRAY_SIZE(display->dpll.shared_dplls)))
> + i >= ARRAY_SIZE(display->dpll.intel_dplls)))
> break;
>
> /* must fit into unsigned long bitmask on 32bit */
> if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
> break;
>
> - display->dpll.shared_dplls[i].info = &dpll_info[i];
> - display->dpll.shared_dplls[i].index = i;
> + display->dpll.intel_dplls[i].info = &dpll_info[i];
> + display->dpll.intel_dplls[i].index = i;
> }
>
> display->dpll.mgr = dpll_mgr;
> - display->dpll.num_shared_dpll = i;
> + display->dpll.num_intel_dpll = i;
> }
>
> /**
> @@ -4482,7 +4482,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
> * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
> */
> int intel_dpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
> @@ -4500,14 +4500,14 @@ int intel_dpll_get_freq(struct intel_display *display,
> * Read out @pll's hardware state into @dpll_hw_state.
> */
> bool intel_dpll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
> }
>
> static void readout_dpll_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> struct intel_crtc *crtc;
>
> @@ -4521,7 +4521,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> - if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
> + if (crtc_state->hw.active && crtc_state->intel_dpll == pll)
> intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
> }
> pll->active_mask = pll->state.pipe_mask;
> @@ -4539,7 +4539,7 @@ void intel_dpll_update_ref_clks(struct intel_display *display)
>
> void intel_dpll_readout_hw_state(struct intel_display *display)
> {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> int i;
>
> for_each_dpll(display, pll, i)
> @@ -4547,7 +4547,7 @@ void intel_dpll_readout_hw_state(struct intel_display *display)
> }
>
> static void sanitize_dpll_state(struct intel_display *display,
> - struct intel_shared_dpll *pll)
> + struct intel_dpll *pll)
> {
> if (!pll->on)
> return;
> @@ -4566,7 +4566,7 @@ static void sanitize_dpll_state(struct intel_display *display,
>
> void intel_dpll_sanitize_state(struct intel_display *display)
> {
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> int i;
>
> intel_cx0_pll_power_save_wa(display);
> @@ -4623,7 +4623,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
>
> static void
> verify_single_dpll_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_crtc *crtc,
> const struct intel_crtc_state *new_crtc_state)
> {
> @@ -4676,8 +4676,8 @@ verify_single_dpll_state(struct intel_display *display,
> pll->info->name);
> }
>
> -static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
> - const struct intel_shared_dpll *new_pll)
> +static bool has_alt_port_dpll(const struct intel_dpll *old_pll,
> + const struct intel_dpll *new_pll)
> {
> return old_pll && new_pll && old_pll != new_pll &&
> (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
> @@ -4692,22 +4692,22 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - if (new_crtc_state->shared_dpll)
> - verify_single_dpll_state(display, new_crtc_state->shared_dpll,
> + if (new_crtc_state->intel_dpll)
> + verify_single_dpll_state(display, new_crtc_state->intel_dpll,
> crtc, new_crtc_state);
>
> - if (old_crtc_state->shared_dpll &&
> - old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
> + if (old_crtc_state->intel_dpll &&
> + old_crtc_state->intel_dpll != new_crtc_state->intel_dpll) {
> u8 pipe_mask = BIT(crtc->pipe);
> - struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
> + struct intel_dpll *pll = old_crtc_state->intel_dpll;
>
> INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
> "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
> pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
>
> /* TC ports have both MG/TC and TBT PLL referenced simultaneously */
> - INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll,
> - new_crtc_state->shared_dpll) &&
> + INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->intel_dpll,
> + new_crtc_state->intel_dpll) &&
> pll->state.pipe_mask & pipe_mask,
> "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
> pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
> @@ -4717,7 +4717,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
> {
> struct intel_display *display = to_intel_display(state);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> int i;
>
> for_each_dpll(display, pll, i)
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 658174b99db3..3604ebbc78b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -31,8 +31,8 @@
> #include "intel_wakeref.h"
>
> #define for_each_dpll(__display, __pll, __i) \
> - for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
> - ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
> + for ((__i) = 0; (__i) < (__display)->dpll.num_intel_dpll && \
> + ((__pll) = &(__display)->dpll.intel_dplls[(__i)]) ; (__i)++)
>
> enum tc_port;
> struct drm_printer;
> @@ -344,9 +344,9 @@ struct dpll_info {
> };
>
> /**
> - * struct intel_shared_dpll - display PLL with tracked state and users
> + * struct intel_dpll - display PLL with tracked state and users
> */
> -struct intel_shared_dpll {
> +struct intel_dpll {
> /**
> * @state:
> *
> @@ -388,11 +388,11 @@ struct intel_shared_dpll {
> #define SKL_DPLL3 3
>
> /* shared dpll functions */
> -struct intel_shared_dpll *
> +struct intel_dpll *
> intel_get_shared_dpll_by_id(struct intel_display *display,
> enum intel_dpll_id id);
> void assert_shared_dpll(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> bool state);
> #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> @@ -405,7 +405,7 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> void intel_release_shared_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> struct intel_dpll_state *shared_dpll_state);
> void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> enum icl_port_dpll_id port_dpll_id);
> @@ -413,10 +413,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> int intel_dpll_get_freq(struct intel_display *display,
> - const struct intel_shared_dpll *pll,
> + const struct intel_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state);
> bool intel_dpll_get_hw_state(struct intel_display *display,
> - struct intel_shared_dpll *pll,
> + struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state);
> void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 169bbe154b5c..b1d2ba9b7295 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -910,7 +910,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
> intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
>
> /* Configure Port Clock Select */
> - drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
> + drm_WARN_ON(display->drm, crtc_state->intel_dpll->info->id != DPLL_ID_SPLL);
> intel_ddi_enable_clock(encoder, crtc_state);
>
> /* Start the training iterating through available voltages and emphasis,
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 8ce7c630da52..ec8f38fba178 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -249,7 +249,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
>
> if (HAS_PCH_SPLIT(display)) {
> assert_fdi_rx_pll_disabled(display, pipe);
> - assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
> + assert_shared_dpll_disabled(display, crtc_state->intel_dpll);
> } else {
> assert_pll_disabled(display, pipe);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 0325b0c9506d..46e0002a1358 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -92,10 +92,10 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
> crtc->active = false;
> crtc->base.enabled = false;
>
> - if (crtc_state->shared_dpll)
> + if (crtc_state->intel_dpll)
> intel_unreference_shared_dpll_crtc(crtc,
> - crtc_state->shared_dpll,
> - &crtc_state->shared_dpll->state);
> + crtc_state->intel_dpll,
> + &crtc_state->intel_dpll->state);
> }
>
> static void set_encoder_for_connector(struct intel_connector *connector,
> @@ -565,7 +565,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
> */
> return display->platform.sandybridge &&
> crtc_state->hw.active &&
> - crtc_state->shared_dpll &&
> + crtc_state->intel_dpll &&
> crtc_state->port_clock == 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 1743ebf551cb..b38305c16e77 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -251,7 +251,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> u32 val, pipeconf_val;
>
> /* Make sure PCH DPLL is enabled */
> - assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
> + assert_shared_dpll_enabled(display, crtc_state->intel_dpll);
>
> /* FDI must be feeding us bits for PCH ports */
> assert_fdi_tx_enabled(display, pipe);
> @@ -381,7 +381,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> temp = intel_de_read(display, PCH_DPLL_SEL);
> temp |= TRANS_DPLL_ENABLE(pipe);
> sel = TRANS_DPLLB_SEL(pipe);
> - if (crtc_state->shared_dpll ==
> + if (crtc_state->intel_dpll ==
> intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
> temp |= sel;
> else
> @@ -496,7 +496,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> enum pipe pipe = crtc->pipe;
> enum intel_dpll_id pll_id;
> bool pll_active;
> @@ -528,8 +528,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
> pll_id = DPLL_ID_PCH_PLL_A;
> }
>
> - crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
> - pll = crtc_state->shared_dpll;
> + crtc_state->intel_dpll = intel_get_shared_dpll_by_id(display, pll_id);
> + pll = crtc_state->intel_dpll;
>
> pll_active = intel_dpll_get_hw_state(display, pll,
> &crtc_state->dpll_hw_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 8bec55deff9f..9f6102d7c7be 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -499,7 +499,7 @@ static void lpt_init_pch_refclk(struct intel_display *display)
> static void ilk_init_pch_refclk(struct intel_display *display)
> {
> struct intel_encoder *encoder;
> - struct intel_shared_dpll *pll;
> + struct intel_dpll *pll;
> int i;
> u32 val, final;
> bool has_lvds = false;
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH 06/18] drm/i915/dpll: Rename intel_shared_dpll
2025-05-09 10:13 ` Jani Nikula
@ 2025-05-12 4:00 ` Kandpal, Suraj
0 siblings, 0 replies; 42+ messages in thread
From: Kandpal, Suraj @ 2025-05-12 4:00 UTC (permalink / raw)
To: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Murthy, Arun R
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, May 9, 2025 3:43 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 06/18] drm/i915/dpll: Rename intel_shared_dpll
>
> On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Rename intel_shared_dpll to intel_dpll to represent both
> > shared and individual dplls. Since from MTL each PHY has it's
> > own PLL making the shared PLL naming a little outdated. In an
> > effort to make this framework accepting of future changes this
> > needs to be done.
> >
> > --v2
> > -Use intel_dpll_global to make sure names start with the filename
> > [Jani/Ville]
> > -Explain the need of this rename [Jani]
> >
> > --v3
> > -Just keep it intel_dpll [Jani]
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 52 ++--
> > drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 12 +-
> > .../gpu/drm/i915/display/intel_display_core.h | 4 +-
> > .../drm/i915/display/intel_display_debugfs.c | 2 +-
> > .../drm/i915/display/intel_display_types.h | 6 +-
> > drivers/gpu/drm/i915/display/intel_dpll.c | 4 +-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 228 +++++++++---------
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 18 +-
> > drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> > .../drm/i915/display/intel_modeset_setup.c | 8 +-
> > .../gpu/drm/i915/display/intel_pch_display.c | 10 +-
> > .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
> > 15 files changed, 179 insertions(+), 179 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index ca7033251e91..55f0a20e0874 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -658,7 +658,7 @@ static void gen11_dsi_map_pll(struct intel_encoder
> *encoder,
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> > - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + struct intel_dpll *pll = crtc_state->intel_dpll;
> > enum phy phy;
> > u32 val;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 74132c1d6385..4d631cbc81d2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -236,7 +236,7 @@ static void intel_wait_ddi_buf_active(struct
> intel_encoder *encoder)
> > port_name(port));
> > }
> >
> > -static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
> > +static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll)
> > {
> > switch (pll->info->id) {
> > case DPLL_ID_WRPLL1:
> > @@ -260,7 +260,7 @@ static u32 hsw_pll_to_ddi_pll_sel(const struct
> intel_shared_dpll *pll)
> > static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll *pll = crtc_state->intel_dpll;
> > int clock = crtc_state->port_clock;
> > const enum intel_dpll_id id = pll->info->id;
> >
> > @@ -1561,7 +1561,7 @@ static bool _icl_ddi_is_clock_enabled(struct
> intel_display *display, i915_reg_t
> > return !(intel_de_read(display, reg) & clk_off);
> > }
> >
> > -static struct intel_shared_dpll *
> > +static struct intel_dpll *
> > _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
> > u32 clk_sel_mask, u32 clk_sel_shift)
> > {
> > @@ -1576,7 +1576,7 @@ static void adls_ddi_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll *pll = crtc_state->intel_dpll;
> > enum phy phy = intel_encoder_to_phy(encoder);
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1606,7 +1606,7 @@ static bool adls_ddi_is_clock_enabled(struct
> intel_encoder *encoder)
> >
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> > }
> >
> > -static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum phy phy = intel_encoder_to_phy(encoder);
> > @@ -1620,7 +1620,7 @@ static void rkl_ddi_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll *pll = crtc_state->intel_dpll;
> > enum phy phy = intel_encoder_to_phy(encoder);
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1650,7 +1650,7 @@ static bool rkl_ddi_is_clock_enabled(struct
> intel_encoder *encoder)
> >
> RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> > }
> >
> > -static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum phy phy = intel_encoder_to_phy(encoder);
> > @@ -1664,7 +1664,7 @@ static void dg1_ddi_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll *pll = crtc_state->intel_dpll;
> > enum phy phy = intel_encoder_to_phy(encoder);
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1703,7 +1703,7 @@ static bool dg1_ddi_is_clock_enabled(struct
> intel_encoder *encoder)
> >
> DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> > }
> >
> > -static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum phy phy = intel_encoder_to_phy(encoder);
> > @@ -1730,7 +1730,7 @@ static void icl_ddi_combo_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll *pll = crtc_state->intel_dpll;
> > enum phy phy = intel_encoder_to_phy(encoder);
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1760,7 +1760,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct
> intel_encoder *encoder)
> >
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> > }
> >
> > -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder
> *encoder)
> > +struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum phy phy = intel_encoder_to_phy(encoder);
> > @@ -1774,7 +1774,7 @@ static void jsl_ddi_tc_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll *pll = crtc_state->intel_dpll;
> > enum port port = encoder->port;
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1817,7 +1817,7 @@ static void icl_ddi_tc_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll *pll = crtc_state->intel_dpll;
> > enum tc_port tc_port = intel_encoder_to_tc(encoder);
> > enum port port = encoder->port;
> >
> > @@ -1868,7 +1868,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct
> intel_encoder *encoder)
> > return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
> > }
> >
> > -static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum tc_port tc_port = intel_encoder_to_tc(encoder);
> > @@ -1898,7 +1898,7 @@ static struct intel_shared_dpll
> *icl_ddi_tc_get_pll(struct intel_encoder *encode
> > return intel_get_shared_dpll_by_id(display, id);
> > }
> >
> > -static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder->base.dev);
> > enum intel_dpll_id id;
> > @@ -1925,7 +1925,7 @@ static void skl_ddi_enable_clock(struct
> intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll *pll = crtc_state->intel_dpll;
> > enum port port = encoder->port;
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -1967,7 +1967,7 @@ static bool skl_ddi_is_clock_enabled(struct
> intel_encoder *encoder)
> > return !(intel_de_read(display, DPLL_CTRL2) &
> DPLL_CTRL2_DDI_CLK_OFF(port));
> > }
> >
> > -static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum port port = encoder->port;
> > @@ -1993,7 +1993,7 @@ void hsw_ddi_enable_clock(struct intel_encoder
> *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll *pll = crtc_state->intel_dpll;
> > enum port port = encoder->port;
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > @@ -2018,7 +2018,7 @@ bool hsw_ddi_is_clock_enabled(struct
> intel_encoder *encoder)
> > return intel_de_read(display, PORT_CLK_SEL(port)) !=
> PORT_CLK_SEL_NONE;
> > }
> >
> > -static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder
> *encoder)
> > +static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum port port = encoder->port;
> > @@ -4187,7 +4187,7 @@ static void intel_ddi_get_config(struct
> intel_encoder *encoder,
> >
> > void intel_ddi_get_clock(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> > @@ -4203,7 +4203,7 @@ void intel_ddi_get_clock(struct intel_encoder
> *encoder,
> >
> > icl_set_active_port_dpll(crtc_state, port_dpll_id);
> >
> > - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state-
> >shared_dpll,
> > + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state-
> >intel_dpll,
> > &crtc_state-
> >dpll_hw_state);
> > }
> >
> > @@ -4257,7 +4257,7 @@ static void icl_ddi_combo_get_config(struct
> intel_encoder *encoder,
> > intel_ddi_get_config(encoder, crtc_state);
> > }
> >
> > -static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
> > +static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
> > {
> > return pll->info->id == DPLL_ID_ICL_TBTPLL;
> > }
> > @@ -4267,7 +4267,7 @@ icl_ddi_tc_port_pll_type(struct intel_encoder
> *encoder,
> > const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > - const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + const struct intel_dpll *pll = crtc_state->intel_dpll;
> >
> > if (drm_WARN_ON(display->drm, !pll))
> > return ICL_PORT_DPLL_DEFAULT;
> > @@ -4290,7 +4290,7 @@ intel_ddi_port_pll_type(struct intel_encoder
> *encoder,
> >
> > static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > struct intel_display *display = to_intel_display(encoder);
> > enum icl_port_dpll_id port_dpll_id;
> > @@ -4313,10 +4313,10 @@ static void icl_ddi_tc_get_clock(struct
> intel_encoder *encoder,
> >
> > icl_set_active_port_dpll(crtc_state, port_dpll_id);
> >
> > - if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
> > + if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
> > crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder-
> >port);
> > else
> > - crtc_state->port_clock = intel_dpll_get_freq(display,
> crtc_state->shared_dpll,
> > + crtc_state->port_clock = intel_dpll_get_freq(display,
> crtc_state->intel_dpll,
> > &crtc_state-
> >dpll_hw_state);
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> b/drivers/gpu/drm/i915/display/intel_ddi.h
> > index 353eb04079e9..c18a69b2ae6d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> > @@ -18,7 +18,7 @@ struct intel_display;
> > struct intel_dp;
> > struct intel_dpll_hw_state;
> > struct intel_encoder;
> > -struct intel_shared_dpll;
> > +struct intel_dpll;
>
> Nitpick, these should remain sorted.
>
> > enum pipe;
> > enum port;
> > enum transcoder;
> > @@ -40,7 +40,7 @@ void intel_ddi_enable_clock(struct intel_encoder
> *encoder,
> > void intel_ddi_disable_clock(struct intel_encoder *encoder);
> > void intel_ddi_get_clock(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > - struct intel_shared_dpll *pll);
> > + struct intel_dpll *pll);
> > void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state);
> > void hsw_ddi_disable_clock(struct intel_encoder *encoder);
> > @@ -50,7 +50,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state);
> > void hsw_ddi_get_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state);
> > -struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder
> *encoder);
> > +struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
> > void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state);
> > void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> > index 287110e4e435..b765d5765b32 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1325,7 +1325,7 @@ static void intel_encoders_update_prepare(struct
> intel_atomic_state *state)
> > if (intel_crtc_needs_modeset(new_crtc_state))
> > continue;
> >
> > - new_crtc_state->shared_dpll = old_crtc_state-
> >shared_dpll;
> > + new_crtc_state->intel_dpll = old_crtc_state-
> >intel_dpll;
> > new_crtc_state->dpll_hw_state = old_crtc_state-
> >dpll_hw_state;
> > }
> > }
> > @@ -1663,7 +1663,7 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> >
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > - if (new_crtc_state->shared_dpll)
> > + if (new_crtc_state->intel_dpll)
> > intel_enable_shared_dpll(new_crtc_state);
> >
> > intel_encoders_pre_enable(state, crtc);
> > @@ -1959,7 +1959,7 @@ static void get_crtc_power_domains(struct
> intel_crtc_state *crtc_state,
> > if (HAS_DDI(display) && crtc_state->has_audio)
> > set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
> >
> > - if (crtc_state->shared_dpll)
> > + if (crtc_state->intel_dpll)
> > set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
> >
> > if (crtc_state->dsc.compression_enable)
> > @@ -4501,7 +4501,7 @@ copy_joiner_crtc_state_modeset(struct
> intel_atomic_state *state,
> > /* preserve some things from the slave's original crtc state */
> > saved_state->uapi = secondary_crtc_state->uapi;
> > saved_state->scaler_state = secondary_crtc_state->scaler_state;
> > - saved_state->shared_dpll = secondary_crtc_state->shared_dpll;
> > + saved_state->intel_dpll = secondary_crtc_state->intel_dpll;
> > saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
> >
> > intel_crtc_free_hw_state(secondary_crtc_state);
> > @@ -4564,7 +4564,7 @@ intel_crtc_prepare_cleared_state(struct
> intel_atomic_state *state,
> > saved_state->uapi = crtc_state->uapi;
> > saved_state->inherited = crtc_state->inherited;
> > saved_state->scaler_state = crtc_state->scaler_state;
> > - saved_state->shared_dpll = crtc_state->shared_dpll;
> > + saved_state->intel_dpll = crtc_state->intel_dpll;
> > saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> > memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
> > sizeof(saved_state->icl_port_dplls));
> > @@ -5318,7 +5318,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> > PIPE_CONF_CHECK_BOOL(double_wide);
> >
> > if (display->dpll.mgr)
> > - PIPE_CONF_CHECK_P(shared_dpll);
> > + PIPE_CONF_CHECK_P(intel_dpll);
> >
> > /* FIXME convert everything over the dpll_mgr */
> > if (display->dpll.mgr || HAS_GMCH(display))
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index e0221e514326..3121a987d07b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -125,8 +125,8 @@ struct intel_audio {
> > struct intel_dpll_global {
> > struct mutex lock;
> >
> > - int num_shared_dpll;
> > - struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
> > + int num_intel_dpll;
> > + struct intel_dpll intel_dplls[I915_NUM_PLLS];
>
> I don't think we have any cases where struct members would be prefixed
> intel_. I think this should be just num_dpll and dplls.
>
Got it will fix
> With that fixed,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
> > const struct intel_dpll_mgr *mgr;
> >
> > struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 3770ce9469d1..ea9e271bc6ee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -618,7 +618,7 @@ static int i915_shared_dplls_info(struct seq_file *m,
> void *unused)
> > {
> > struct intel_display *display = node_to_intel_display(m->private);
> > struct drm_printer p = drm_seq_file_printer(m);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > int i;
> >
> > drm_modeset_lock_all(display->drm);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 1bdffaca153a..826af285e7fc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1075,8 +1075,8 @@ struct intel_crtc_state {
> > * haswell. */
> > struct dpll dpll;
> >
> > - /* Selected dpll when shared or NULL. */
> > - struct intel_shared_dpll *shared_dpll;
> > + /* Selected dpll. */
>
> Or NULL?
Sure will fix this
Regards,
Suraj Kandpal
>
> > + struct intel_dpll *intel_dpll;
> >
> > /* Actual register state of the dpll, for shared dpll cross-checking. */
> > struct intel_dpll_hw_state dpll_hw_state;
> > @@ -1086,7 +1086,7 @@ struct intel_crtc_state {
> > * setting shared_dpll and dpll_hw_state to one of these reserved
> ones.
> > */
> > struct icl_port_dpll {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > struct intel_dpll_hw_state hw_state;
> > } icl_port_dplls[ICL_PORT_DPLL_COUNT];
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index 8db603d9c823..4d1f7fccd28a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -1767,9 +1767,9 @@ int intel_dpll_crtc_get_shared_dpll(struct
> intel_atomic_state *state,
> > int ret;
> >
> > drm_WARN_ON(display->drm, !intel_crtc_needs_modeset(crtc_state));
> > - drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state-
> >shared_dpll);
> > + drm_WARN_ON(display->drm, !crtc_state->hw.enable && crtc_state-
> >intel_dpll);
> >
> > - if (!crtc_state->hw.enable || crtc_state->shared_dpll)
> > + if (!crtc_state->hw.enable || crtc_state->intel_dpll)
> > return 0;
> >
> > if (!display->funcs.dpll->crtc_get_shared_dpll)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index bdad4d72cc01..e63568be3150 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -70,7 +70,7 @@ struct intel_dpll_funcs {
> > * the pll is not already enabled.
> > */
> > void (*enable)(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state);
> >
> > /*
> > @@ -79,7 +79,7 @@ struct intel_dpll_funcs {
> > * tracked users for it.
> > */
> > void (*disable)(struct intel_display *display,
> > - struct intel_shared_dpll *pll);
> > + struct intel_dpll *pll);
> >
> > /*
> > * Hook for reading the values currently programmed to the DPLL
> > @@ -87,7 +87,7 @@ struct intel_dpll_funcs {
> > * verification after a mode set.
> > */
> > bool (*get_hw_state)(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state);
> >
> > /*
> > @@ -95,7 +95,7 @@ struct intel_dpll_funcs {
> > * in state.
> > */
> > int (*get_freq)(struct intel_display *i915,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state);
> > };
> >
> > @@ -124,7 +124,7 @@ static void
> > intel_atomic_duplicate_dpll_state(struct intel_display *display,
> > struct intel_dpll_state *dpll_state)
> > {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > int i;
> >
> > /* Copy dpll state */
> > @@ -158,11 +158,11 @@ intel_atomic_get_shared_dpll_state(struct
> drm_atomic_state *s)
> > * Returns:
> > * A pointer to the DPLL with @id
> > */
> > -struct intel_shared_dpll *
> > +struct intel_dpll *
> > intel_get_shared_dpll_by_id(struct intel_display *display,
> > enum intel_dpll_id id)
> > {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > int i;
> >
> > for_each_dpll(display, pll, i) {
> > @@ -176,7 +176,7 @@ intel_get_shared_dpll_by_id(struct intel_display
> *display,
> >
> > /* For ILK+ */
> > void assert_shared_dpll(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > bool state)
> > {
> > bool cur_state;
> > @@ -205,7 +205,7 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum
> tc_port tc_port)
> >
> > static i915_reg_t
> > intel_combo_pll_enable_reg(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > if (display->platform.dg1)
> > return DG1_DPLL_ENABLE(pll->info->id);
> > @@ -218,7 +218,7 @@ intel_combo_pll_enable_reg(struct intel_display
> *display,
> >
> > static i915_reg_t
> > intel_tc_pll_enable_reg(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > const enum intel_dpll_id id = pll->info->id;
> > enum tc_port tc_port = icl_pll_id_to_tc_port(id);
> > @@ -230,7 +230,7 @@ intel_tc_pll_enable_reg(struct intel_display *display,
> > }
> >
> > static void _intel_enable_shared_dpll(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > if (pll->info->power_domain)
> > pll->wakeref = intel_display_power_get(display, pll->info-
> >power_domain);
> > @@ -240,7 +240,7 @@ static void _intel_enable_shared_dpll(struct
> intel_display *display,
> > }
> >
> > static void _intel_disable_shared_dpll(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > pll->info->funcs->disable(display, pll);
> > pll->on = false;
> > @@ -259,7 +259,7 @@ void intel_enable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + struct intel_dpll *pll = crtc_state->intel_dpll;
> > unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
> > unsigned int old_mask;
> >
> > @@ -305,7 +305,7 @@ void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> > + struct intel_dpll *pll = crtc_state->intel_dpll;
> > unsigned int pipe_mask = intel_crtc_joined_pipe_mask(crtc_state);
> >
> > /* PCH only available on ILK+ */
> > @@ -344,7 +344,7 @@ void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> > static unsigned long
> > intel_dpll_mask_all(struct intel_display *display)
> > {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > unsigned long dpll_mask = 0;
> > int i;
> >
> > @@ -357,7 +357,7 @@ intel_dpll_mask_all(struct intel_display *display)
> > return dpll_mask;
> > }
> >
> > -static struct intel_shared_dpll *
> > +static struct intel_dpll *
> > intel_find_shared_dpll(struct intel_atomic_state *state,
> > const struct intel_crtc *crtc,
> > const struct intel_dpll_hw_state *dpll_hw_state,
> > @@ -366,7 +366,7 @@ intel_find_shared_dpll(struct intel_atomic_state
> *state,
> > struct intel_display *display = to_intel_display(crtc);
> > unsigned long dpll_mask_all = intel_dpll_mask_all(display);
> > struct intel_dpll_state *dpll_state;
> > - struct intel_shared_dpll *unused_pll = NULL;
> > + struct intel_dpll *unused_pll = NULL;
> > enum intel_dpll_id id;
> >
> > dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> > @@ -374,7 +374,7 @@ intel_find_shared_dpll(struct intel_atomic_state
> *state,
> > drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
> >
> > for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> >
> > pll = intel_get_shared_dpll_by_id(display, id);
> > if (!pll)
> > @@ -421,7 +421,7 @@ intel_find_shared_dpll(struct intel_atomic_state
> *state,
> > */
> > static void
> > intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > struct intel_dpll_state *dpll_state)
> > {
> > struct intel_display *display = to_intel_display(crtc);
> > @@ -437,7 +437,7 @@ intel_reference_shared_dpll_crtc(const struct
> intel_crtc *crtc,
> > static void
> > intel_reference_shared_dpll(struct intel_atomic_state *state,
> > const struct intel_crtc *crtc,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct intel_dpll_state *dpll_state;
> > @@ -460,7 +460,7 @@ intel_reference_shared_dpll(struct
> intel_atomic_state *state,
> > */
> > void
> > intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > struct intel_dpll_state *dpll_state)
> > {
> > struct intel_display *display = to_intel_display(crtc);
> > @@ -475,7 +475,7 @@ intel_unreference_shared_dpll_crtc(const struct
> intel_crtc *crtc,
> >
> > static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> > const struct intel_crtc *crtc,
> > - const struct intel_shared_dpll *pll)
> > + const struct intel_dpll *pll)
> > {
> > struct intel_dpll_state *dpll_state;
> >
> > @@ -492,12 +492,12 @@ static void intel_put_dpll(struct intel_atomic_state
> *state,
> > struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> >
> > - new_crtc_state->shared_dpll = NULL;
> > + new_crtc_state->intel_dpll = NULL;
> >
> > - if (!old_crtc_state->shared_dpll)
> > + if (!old_crtc_state->intel_dpll)
> > return;
> >
> > - intel_unreference_shared_dpll(state, crtc, old_crtc_state-
> >shared_dpll);
> > + intel_unreference_shared_dpll(state, crtc, old_crtc_state->intel_dpll);
> > }
> >
> > /**
> > @@ -515,7 +515,7 @@ void intel_shared_dpll_swap_state(struct
> intel_atomic_state *state)
> > {
> > struct intel_display *display = to_intel_display(state);
> > struct intel_dpll_state *dpll_state = state->dpll_state;
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > int i;
> >
> > if (!state->dpll_set)
> > @@ -526,7 +526,7 @@ void intel_shared_dpll_swap_state(struct
> intel_atomic_state *state)
> > }
> >
> > static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> > @@ -562,7 +562,7 @@ static void ibx_assert_pch_refclk_enabled(struct
> intel_display *display)
> > }
> >
> > static void ibx_pch_dpll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> > @@ -591,7 +591,7 @@ static void ibx_pch_dpll_enable(struct intel_display
> *display,
> > }
> >
> > static void ibx_pch_dpll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > const enum intel_dpll_id id = pll->info->id;
> >
> > @@ -614,7 +614,7 @@ static int ibx_get_dpll(struct intel_atomic_state
> *state,
> > struct intel_display *display = to_intel_display(state);
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > enum intel_dpll_id id;
> >
> > if (HAS_PCH_IBX(display)) {
> > @@ -640,7 +640,7 @@ static int ibx_get_dpll(struct intel_atomic_state
> *state,
> > intel_reference_shared_dpll(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > - crtc_state->shared_dpll = pll;
> > + crtc_state->intel_dpll = pll;
> >
> > return 0;
> > }
> > @@ -692,7 +692,7 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
> > };
> >
> > static void hsw_ddi_wrpll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -704,7 +704,7 @@ static void hsw_ddi_wrpll_enable(struct intel_display
> *display,
> > }
> >
> > static void hsw_ddi_spll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -715,7 +715,7 @@ static void hsw_ddi_spll_enable(struct intel_display
> *display,
> > }
> >
> > static void hsw_ddi_wrpll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > const enum intel_dpll_id id = pll->info->id;
> >
> > @@ -731,7 +731,7 @@ static void hsw_ddi_wrpll_disable(struct intel_display
> *display,
> > }
> >
> > static void hsw_ddi_spll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > enum intel_dpll_id id = pll->info->id;
> >
> > @@ -747,7 +747,7 @@ static void hsw_ddi_spll_disable(struct intel_display
> *display,
> > }
> >
> > static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -769,7 +769,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct
> intel_display *display,
> > }
> >
> > static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -996,7 +996,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
> > }
> >
> > static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -1059,7 +1059,7 @@ hsw_ddi_wrpll_compute_dpll(struct
> intel_atomic_state *state,
> > return 0;
> > }
> >
> > -static struct intel_shared_dpll *
> > +static struct intel_dpll *
> > hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > @@ -1090,11 +1090,11 @@ hsw_ddi_lcpll_compute_dpll(struct
> intel_crtc_state *crtc_state)
> > }
> > }
> >
> > -static struct intel_shared_dpll *
> > +static struct intel_dpll *
> > hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > enum intel_dpll_id pll_id;
> > int clock = crtc_state->port_clock;
> >
> > @@ -1122,7 +1122,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state
> *crtc_state)
> > }
> >
> > static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > int link_clock = 0;
> > @@ -1162,7 +1162,7 @@ hsw_ddi_spll_compute_dpll(struct
> intel_atomic_state *state,
> > return 0;
> > }
> >
> > -static struct intel_shared_dpll *
> > +static struct intel_dpll *
> > hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > @@ -1174,7 +1174,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state
> *state,
> > }
> >
> > static int hsw_ddi_spll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> > @@ -1221,7 +1221,7 @@ static int hsw_get_dpll(struct intel_atomic_state
> *state,
> > {
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > - struct intel_shared_dpll *pll = NULL;
> > + struct intel_dpll *pll = NULL;
> >
> > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > pll = hsw_ddi_wrpll_get_dpll(state, crtc);
> > @@ -1236,7 +1236,7 @@ static int hsw_get_dpll(struct intel_atomic_state
> *state,
> > intel_reference_shared_dpll(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > - crtc_state->shared_dpll = pll;
> > + crtc_state->intel_dpll = pll;
> >
> > return 0;
> > }
> > @@ -1285,18 +1285,18 @@ static const struct intel_dpll_funcs
> hsw_ddi_spll_funcs = {
> > };
> >
> > static void hsw_ddi_lcpll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *hw_state)
> > {
> > }
> >
> > static void hsw_ddi_lcpll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > }
> >
> > static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > return true;
> > @@ -1364,7 +1364,7 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
> > };
> >
> > static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct skl_dpll_hw_state *hw_state)
> > {
> > const enum intel_dpll_id id = pll->info->id;
> > @@ -1378,7 +1378,7 @@ static void skl_ddi_pll_write_ctrl1(struct
> intel_display *display,
> > }
> >
> > static void skl_ddi_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1400,7 +1400,7 @@ static void skl_ddi_pll_enable(struct intel_display
> *display,
> > }
> >
> > static void skl_ddi_dpll0_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1409,7 +1409,7 @@ static void skl_ddi_dpll0_enable(struct
> intel_display *display,
> > }
> >
> > static void skl_ddi_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > const struct skl_dpll_regs *regs = skl_dpll_regs;
> > const enum intel_dpll_id id = pll->info->id;
> > @@ -1420,12 +1420,12 @@ static void skl_ddi_pll_disable(struct
> intel_display *display,
> > }
> >
> > static void skl_ddi_dpll0_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > }
> >
> > static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1463,7 +1463,7 @@ static bool skl_ddi_pll_get_hw_state(struct
> intel_display *display,
> > }
> >
> > static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1736,7 +1736,7 @@ skl_ddi_calculate_wrpll(int clock,
> > }
> >
> > static int skl_ddi_wrpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1884,7 +1884,7 @@ skl_ddi_dp_set_dpll_hw_state(struct
> intel_crtc_state *crtc_state)
> > }
> >
> > static int skl_ddi_lcpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -1939,7 +1939,7 @@ static int skl_get_dpll(struct intel_atomic_state
> *state,
> > {
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> >
> > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> > pll = intel_find_shared_dpll(state, crtc,
> > @@ -1957,13 +1957,13 @@ static int skl_get_dpll(struct intel_atomic_state
> *state,
> > intel_reference_shared_dpll(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > - crtc_state->shared_dpll = pll;
> > + crtc_state->intel_dpll = pll;
> >
> > return 0;
> > }
> >
> > static int skl_ddi_pll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> > @@ -2038,7 +2038,7 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
> > };
> >
> > static void bxt_ddi_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> > @@ -2141,7 +2141,7 @@ static void bxt_ddi_pll_enable(struct intel_display
> *display,
> > }
> >
> > static void bxt_ddi_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
> >
> > @@ -2160,7 +2160,7 @@ static void bxt_ddi_pll_disable(struct intel_display
> *display,
> > }
> >
> > static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> > @@ -2360,7 +2360,7 @@ static int bxt_ddi_set_dpll_hw_state(struct
> intel_crtc_state *crtc_state,
> > }
> >
> > static int bxt_ddi_pll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> > @@ -2429,7 +2429,7 @@ static int bxt_get_dpll(struct intel_atomic_state
> *state,
> > struct intel_display *display = to_intel_display(state);
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > enum intel_dpll_id id;
> >
> > /* 1:1 mapping between ports and PLLs */
> > @@ -2442,7 +2442,7 @@ static int bxt_get_dpll(struct intel_atomic_state
> *state,
> > intel_reference_shared_dpll(state, crtc,
> > pll, &crtc_state->dpll_hw_state);
> >
> > - crtc_state->shared_dpll = pll;
> > + crtc_state->intel_dpll = pll;
> >
> > return 0;
> > }
> > @@ -2755,7 +2755,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state
> *crtc_state,
> > }
> >
> > static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > /*
> > @@ -2826,7 +2826,7 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
> > }
> >
> > static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -3199,7 +3199,7 @@ static int icl_calc_mg_pll_state(struct
> intel_crtc_state *crtc_state,
> > }
> >
> > static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state
> *dpll_hw_state)
> > {
> > const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -3285,7 +3285,7 @@ void icl_set_active_port_dpll(struct
> intel_crtc_state *crtc_state,
> > struct icl_port_dpll *port_dpll =
> > &crtc_state->icl_port_dplls[port_dpll_id];
> >
> > - crtc_state->shared_dpll = port_dpll->pll;
> > + crtc_state->intel_dpll = port_dpll->pll;
> > crtc_state->dpll_hw_state = port_dpll->hw_state;
> > }
> >
> > @@ -3428,8 +3428,8 @@ static int icl_compute_tc_phy_dplls(struct
> intel_atomic_state *state,
> > return ret;
> >
> > /* this is mainly for the fastset check */
> > - if (old_crtc_state->shared_dpll &&
> > - old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> > + if (old_crtc_state->intel_dpll &&
> > + old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> > icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> > else
> > icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
> > @@ -3521,7 +3521,7 @@ static void icl_put_dplls(struct intel_atomic_state
> *state,
> > intel_atomic_get_new_crtc_state(state, crtc);
> > enum icl_port_dpll_id id;
> >
> > - new_crtc_state->shared_dpll = NULL;
> > + new_crtc_state->intel_dpll = NULL;
> >
> > for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
> > const struct icl_port_dpll *old_port_dpll =
> > @@ -3539,7 +3539,7 @@ static void icl_put_dplls(struct intel_atomic_state
> *state,
> > }
> >
> > static bool mg_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -3606,7 +3606,7 @@ static bool mg_pll_get_hw_state(struct
> intel_display *display,
> > }
> >
> > static bool dkl_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -3678,7 +3678,7 @@ static bool dkl_pll_get_hw_state(struct
> intel_display *display,
> > }
> >
> > static bool icl_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state,
> > i915_reg_t enable_reg)
> > {
> > @@ -3739,7 +3739,7 @@ static bool icl_pll_get_hw_state(struct intel_display
> *display,
> > }
> >
> > static bool combo_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
> > @@ -3748,14 +3748,14 @@ static bool combo_pll_get_hw_state(struct
> intel_display *display,
> > }
> >
> > static bool tbt_pll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > return icl_pll_get_hw_state(display, pll, dpll_hw_state,
> TBT_PLL_ENABLE);
> > }
> >
> > static void icl_dpll_write(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct icl_dpll_hw_state *hw_state)
> > {
> > const enum intel_dpll_id id = pll->info->id;
> > @@ -3797,7 +3797,7 @@ static void icl_dpll_write(struct intel_display
> *display,
> > }
> >
> > static void icl_mg_pll_write(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct icl_dpll_hw_state *hw_state)
> > {
> > enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
> > @@ -3840,7 +3840,7 @@ static void icl_mg_pll_write(struct intel_display
> *display,
> > }
> >
> > static void dkl_pll_write(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct icl_dpll_hw_state *hw_state)
> > {
> > enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
> > @@ -3905,7 +3905,7 @@ static void dkl_pll_write(struct intel_display
> *display,
> > }
> >
> > static void icl_pll_power_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > i915_reg_t enable_reg)
> > {
> > intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
> > @@ -3920,7 +3920,7 @@ static void icl_pll_power_enable(struct
> intel_display *display,
> > }
> >
> > static void icl_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > i915_reg_t enable_reg)
> > {
> > intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
> > @@ -3930,7 +3930,7 @@ static void icl_pll_enable(struct intel_display
> *display,
> > drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
> > }
> >
> > -static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct
> intel_shared_dpll *pll)
> > +static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct
> intel_dpll *pll)
> > {
> > u32 val;
> >
> > @@ -3955,7 +3955,7 @@ static void adlp_cmtg_clock_gating_wa(struct
> intel_display *display, struct inte
> > }
> >
> > static void combo_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -3979,7 +3979,7 @@ static void combo_pll_enable(struct intel_display
> *display,
> > }
> >
> > static void tbt_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -4000,7 +4000,7 @@ static void tbt_pll_enable(struct intel_display
> *display,
> > }
> >
> > static void mg_pll_enable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> > @@ -4025,7 +4025,7 @@ static void mg_pll_enable(struct intel_display
> *display,
> > }
> >
> > static void icl_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > i915_reg_t enable_reg)
> > {
> > /* The first steps are done by intel_ddi_post_disable(). */
> > @@ -4056,7 +4056,7 @@ static void icl_pll_disable(struct intel_display
> *display,
> > }
> >
> > static void combo_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
> >
> > @@ -4064,13 +4064,13 @@ static void combo_pll_disable(struct
> intel_display *display,
> > }
> >
> > static void tbt_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > icl_pll_disable(display, pll, TBT_PLL_ENABLE);
> > }
> >
> > static void mg_pll_disable(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
> >
> > @@ -4346,19 +4346,19 @@ void intel_shared_dpll_init(struct intel_display
> *display)
> >
> > for (i = 0; dpll_info[i].name; i++) {
> > if (drm_WARN_ON(display->drm,
> > - i >= ARRAY_SIZE(display->dpll.shared_dplls)))
> > + i >= ARRAY_SIZE(display->dpll.intel_dplls)))
> > break;
> >
> > /* must fit into unsigned long bitmask on 32bit */
> > if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
> > break;
> >
> > - display->dpll.shared_dplls[i].info = &dpll_info[i];
> > - display->dpll.shared_dplls[i].index = i;
> > + display->dpll.intel_dplls[i].info = &dpll_info[i];
> > + display->dpll.intel_dplls[i].index = i;
> > }
> >
> > display->dpll.mgr = dpll_mgr;
> > - display->dpll.num_shared_dpll = i;
> > + display->dpll.num_intel_dpll = i;
> > }
> >
> > /**
> > @@ -4482,7 +4482,7 @@ void intel_update_active_dpll(struct
> intel_atomic_state *state,
> > * Return the output frequency corresponding to @pll's passed in
> @dpll_hw_state.
> > */
> > int intel_dpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
> > @@ -4500,14 +4500,14 @@ int intel_dpll_get_freq(struct intel_display
> *display,
> > * Read out @pll's hardware state into @dpll_hw_state.
> > */
> > bool intel_dpll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
> > }
> >
> > static void readout_dpll_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > struct intel_crtc *crtc;
> >
> > @@ -4521,7 +4521,7 @@ static void readout_dpll_hw_state(struct
> intel_display *display,
> > struct intel_crtc_state *crtc_state =
> > to_intel_crtc_state(crtc->base.state);
> >
> > - if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
> > + if (crtc_state->hw.active && crtc_state->intel_dpll == pll)
> > intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
> > }
> > pll->active_mask = pll->state.pipe_mask;
> > @@ -4539,7 +4539,7 @@ void intel_dpll_update_ref_clks(struct
> intel_display *display)
> >
> > void intel_dpll_readout_hw_state(struct intel_display *display)
> > {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > int i;
> >
> > for_each_dpll(display, pll, i)
> > @@ -4547,7 +4547,7 @@ void intel_dpll_readout_hw_state(struct
> intel_display *display)
> > }
> >
> > static void sanitize_dpll_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll)
> > + struct intel_dpll *pll)
> > {
> > if (!pll->on)
> > return;
> > @@ -4566,7 +4566,7 @@ static void sanitize_dpll_state(struct intel_display
> *display,
> >
> > void intel_dpll_sanitize_state(struct intel_display *display)
> > {
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > int i;
> >
> > intel_cx0_pll_power_save_wa(display);
> > @@ -4623,7 +4623,7 @@ bool intel_dpll_compare_hw_state(struct
> intel_display *display,
> >
> > static void
> > verify_single_dpll_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_crtc *crtc,
> > const struct intel_crtc_state *new_crtc_state)
> > {
> > @@ -4676,8 +4676,8 @@ verify_single_dpll_state(struct intel_display
> *display,
> > pll->info->name);
> > }
> >
> > -static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
> > - const struct intel_shared_dpll *new_pll)
> > +static bool has_alt_port_dpll(const struct intel_dpll *old_pll,
> > + const struct intel_dpll *new_pll)
> > {
> > return old_pll && new_pll && old_pll != new_pll &&
> > (old_pll->info->is_alt_port_dpll || new_pll->info-
> >is_alt_port_dpll);
> > @@ -4692,22 +4692,22 @@ void intel_shared_dpll_state_verify(struct
> intel_atomic_state *state,
> > const struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> >
> > - if (new_crtc_state->shared_dpll)
> > - verify_single_dpll_state(display, new_crtc_state->shared_dpll,
> > + if (new_crtc_state->intel_dpll)
> > + verify_single_dpll_state(display, new_crtc_state->intel_dpll,
> > crtc, new_crtc_state);
> >
> > - if (old_crtc_state->shared_dpll &&
> > - old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
> > + if (old_crtc_state->intel_dpll &&
> > + old_crtc_state->intel_dpll != new_crtc_state->intel_dpll) {
> > u8 pipe_mask = BIT(crtc->pipe);
> > - struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
> > + struct intel_dpll *pll = old_crtc_state->intel_dpll;
> >
> > INTEL_DISPLAY_STATE_WARN(display, pll->active_mask &
> pipe_mask,
> > "%s: pll active mismatch (didn't expect
> pipe %c in active mask (0x%x))\n",
> > pll->info->name, pipe_name(crtc-
> >pipe), pll->active_mask);
> >
> > /* TC ports have both MG/TC and TBT PLL referenced
> simultaneously */
> > - INTEL_DISPLAY_STATE_WARN(display,
> !has_alt_port_dpll(old_crtc_state->shared_dpll,
> > -
> new_crtc_state->shared_dpll) &&
> > + INTEL_DISPLAY_STATE_WARN(display,
> !has_alt_port_dpll(old_crtc_state->intel_dpll,
> > +
> new_crtc_state->intel_dpll) &&
> > pll->state.pipe_mask & pipe_mask,
> > "%s: pll enabled crtcs mismatch
> (found pipe %c in enabled mask (0x%x))\n",
> > pll->info->name, pipe_name(crtc-
> >pipe), pll->state.pipe_mask);
> > @@ -4717,7 +4717,7 @@ void intel_shared_dpll_state_verify(struct
> intel_atomic_state *state,
> > void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
> > {
> > struct intel_display *display = to_intel_display(state);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > int i;
> >
> > for_each_dpll(display, pll, i)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 658174b99db3..3604ebbc78b5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -31,8 +31,8 @@
> > #include "intel_wakeref.h"
> >
> > #define for_each_dpll(__display, __pll, __i) \
> > - for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
> > - ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
> > + for ((__i) = 0; (__i) < (__display)->dpll.num_intel_dpll && \
> > + ((__pll) = &(__display)->dpll.intel_dplls[(__i)]) ; (__i)++)
> >
> > enum tc_port;
> > struct drm_printer;
> > @@ -344,9 +344,9 @@ struct dpll_info {
> > };
> >
> > /**
> > - * struct intel_shared_dpll - display PLL with tracked state and users
> > + * struct intel_dpll - display PLL with tracked state and users
> > */
> > -struct intel_shared_dpll {
> > +struct intel_dpll {
> > /**
> > * @state:
> > *
> > @@ -388,11 +388,11 @@ struct intel_shared_dpll {
> > #define SKL_DPLL3 3
> >
> > /* shared dpll functions */
> > -struct intel_shared_dpll *
> > +struct intel_dpll *
> > intel_get_shared_dpll_by_id(struct intel_display *display,
> > enum intel_dpll_id id);
> > void assert_shared_dpll(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > bool state);
> > #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> > #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> > @@ -405,7 +405,7 @@ int intel_reserve_shared_dplls(struct
> intel_atomic_state *state,
> > void intel_release_shared_dplls(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
> > void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > struct intel_dpll_state
> *shared_dpll_state);
> > void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> > enum icl_port_dpll_id port_dpll_id);
> > @@ -413,10 +413,10 @@ void intel_update_active_dpll(struct
> intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > struct intel_encoder *encoder);
> > int intel_dpll_get_freq(struct intel_display *display,
> > - const struct intel_shared_dpll *pll,
> > + const struct intel_dpll *pll,
> > const struct intel_dpll_hw_state *dpll_hw_state);
> > bool intel_dpll_get_hw_state(struct intel_display *display,
> > - struct intel_shared_dpll *pll,
> > + struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state);
> > void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
> b/drivers/gpu/drm/i915/display/intel_fdi.c
> > index 169bbe154b5c..b1d2ba9b7295 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> > @@ -910,7 +910,7 @@ void hsw_fdi_link_train(struct intel_encoder
> *encoder,
> > intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val);
> >
> > /* Configure Port Clock Select */
> > - drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id !=
> DPLL_ID_SPLL);
> > + drm_WARN_ON(display->drm, crtc_state->intel_dpll->info->id !=
> DPLL_ID_SPLL);
> > intel_ddi_enable_clock(encoder, crtc_state);
> >
> > /* Start the training iterating through available voltages and emphasis,
> > diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
> b/drivers/gpu/drm/i915/display/intel_lvds.c
> > index 8ce7c630da52..ec8f38fba178 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> > @@ -249,7 +249,7 @@ static void intel_pre_enable_lvds(struct
> intel_atomic_state *state,
> >
> > if (HAS_PCH_SPLIT(display)) {
> > assert_fdi_rx_pll_disabled(display, pipe);
> > - assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
> > + assert_shared_dpll_disabled(display, crtc_state->intel_dpll);
> > } else {
> > assert_pll_disabled(display, pipe);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index 0325b0c9506d..46e0002a1358 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -92,10 +92,10 @@ static void intel_crtc_disable_noatomic_begin(struct
> intel_crtc *crtc,
> > crtc->active = false;
> > crtc->base.enabled = false;
> >
> > - if (crtc_state->shared_dpll)
> > + if (crtc_state->intel_dpll)
> > intel_unreference_shared_dpll_crtc(crtc,
> > - crtc_state->shared_dpll,
> > - &crtc_state->shared_dpll-
> >state);
> > + crtc_state->intel_dpll,
> > + &crtc_state->intel_dpll-
> >state);
> > }
> >
> > static void set_encoder_for_connector(struct intel_connector *connector,
> > @@ -565,7 +565,7 @@ static bool has_bogus_dpll_config(const struct
> intel_crtc_state *crtc_state)
> > */
> > return display->platform.sandybridge &&
> > crtc_state->hw.active &&
> > - crtc_state->shared_dpll &&
> > + crtc_state->intel_dpll &&
> > crtc_state->port_clock == 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > index 1743ebf551cb..b38305c16e77 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > @@ -251,7 +251,7 @@ static void ilk_enable_pch_transcoder(const struct
> intel_crtc_state *crtc_state)
> > u32 val, pipeconf_val;
> >
> > /* Make sure PCH DPLL is enabled */
> > - assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
> > + assert_shared_dpll_enabled(display, crtc_state->intel_dpll);
> >
> > /* FDI must be feeding us bits for PCH ports */
> > assert_fdi_tx_enabled(display, pipe);
> > @@ -381,7 +381,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> > temp = intel_de_read(display, PCH_DPLL_SEL);
> > temp |= TRANS_DPLL_ENABLE(pipe);
> > sel = TRANS_DPLLB_SEL(pipe);
> > - if (crtc_state->shared_dpll ==
> > + if (crtc_state->intel_dpll ==
> > intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
> > temp |= sel;
> > else
> > @@ -496,7 +496,7 @@ void ilk_pch_get_config(struct intel_crtc_state
> *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > enum pipe pipe = crtc->pipe;
> > enum intel_dpll_id pll_id;
> > bool pll_active;
> > @@ -528,8 +528,8 @@ void ilk_pch_get_config(struct intel_crtc_state
> *crtc_state)
> > pll_id = DPLL_ID_PCH_PLL_A;
> > }
> >
> > - crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
> > - pll = crtc_state->shared_dpll;
> > + crtc_state->intel_dpll = intel_get_shared_dpll_by_id(display, pll_id);
> > + pll = crtc_state->intel_dpll;
> >
> > pll_active = intel_dpll_get_hw_state(display, pll,
> > &crtc_state->dpll_hw_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > index 8bec55deff9f..9f6102d7c7be 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > @@ -499,7 +499,7 @@ static void lpt_init_pch_refclk(struct intel_display
> *display)
> > static void ilk_init_pch_refclk(struct intel_display *display)
> > {
> > struct intel_encoder *encoder;
> > - struct intel_shared_dpll *pll;
> > + struct intel_dpll *pll;
> > int i;
> > u32 val, final;
> > bool has_lvds = false;
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 07/18] drm/i915/dpll: Move away from using shared dpll
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (5 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 06/18] drm/i915/dpll: Rename intel_shared_dpll Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:17 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 08/18] drm/i915/dpll: Rename crtc_get_shared_dpll Suraj Kandpal
` (10 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename functions to move away from using shared dpll in the dpll
framework as much as possible since dpll may not always be shared.
--v2
-Use intel_dpll_global instead of global_dpll [Jani]
--v3
-Just use intel_dpll [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
.../drm/i915/display/intel_display_driver.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 10 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 235 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 52 ++--
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c | 6 +-
.../drm/i915/display/intel_modeset_verify.c | 4 +-
.../gpu/drm/i915/display/intel_pch_display.c | 14 +-
10 files changed, 173 insertions(+), 174 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4d631cbc81d2..11ebcb40c91f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1569,7 +1569,7 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_by_id(display, id);
}
static void adls_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1723,7 +1723,7 @@ static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
if (phy >= PHY_C)
id += DPLL_ID_DG1_DPLL2;
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_by_id(display, id);
}
static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
@@ -1895,7 +1895,7 @@ static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_by_id(display, id);
}
static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
@@ -1918,7 +1918,7 @@ static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_by_id(display, id);
}
static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1986,7 +1986,7 @@ static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_by_id(display, id);
}
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2053,7 +2053,7 @@ static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
return NULL;
}
- return intel_get_shared_dpll_by_id(display, id);
+ return intel_get_dpll_by_id(display, id);
}
void intel_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2760,7 +2760,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
* 4. Enable the port PLL.
*
* The PLL enabling itself was already done before this function by
- * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
+ * hsw_crtc_enable()->intel_enable_dpll(). We need only
* configure the PLL to port mapping here.
*/
intel_ddi_enable_clock(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b765d5765b32..ce5c9e74475d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1664,7 +1664,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_encoders_pre_pll_enable(state, crtc);
if (new_crtc_state->intel_dpll)
- intel_enable_shared_dpll(new_crtc_state);
+ intel_enable_dpll(new_crtc_state);
intel_encoders_pre_enable(state, crtc);
@@ -1793,7 +1793,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
intel_encoders_disable(state, crtc);
intel_encoders_post_disable(state, crtc);
- intel_disable_shared_dpll(old_crtc_state);
+ intel_disable_dpll(old_crtc_state);
intel_encoders_post_pll_disable(state, crtc);
@@ -6434,7 +6434,7 @@ int intel_atomic_check(struct drm_device *dev,
any_ms = true;
- intel_release_shared_dplls(state, crtc);
+ intel_release_dplls(state, crtc);
}
if (any_ms && !check_digital_port_conflicts(state)) {
@@ -7531,7 +7531,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state)
intel_atomic_swap_global_state(state);
- intel_shared_dpll_swap_state(state);
+ intel_dpll_swap_state(state);
intel_atomic_track_fbs(state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 5c74ab5fd1aa..16d91be02bb9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -446,7 +446,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
}
intel_plane_possible_crtcs_init(display);
- intel_shared_dpll_init(display);
+ intel_dpll_init(display);
intel_fdi_pll_freq_update(display);
intel_update_czclk(display);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 4d1f7fccd28a..db67e92505d2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1161,7 +1161,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- ret = intel_compute_shared_dplls(state, crtc, encoder);
+ ret = intel_compute_dplls(state, crtc, encoder);
if (ret)
return ret;
@@ -1189,7 +1189,7 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- return intel_reserve_shared_dplls(state, crtc, encoder);
+ return intel_reserve_dplls(state, crtc, encoder);
}
static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1223,7 +1223,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
if (ret)
return ret;
- /* TODO: Do the readback via intel_compute_shared_dplls() */
+ /* TODO: Do the readback via intel_compute_dplls() */
crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
@@ -1394,7 +1394,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
- ret = intel_compute_shared_dplls(state, crtc, NULL);
+ ret = intel_compute_dplls(state, crtc, NULL);
if (ret)
return ret;
@@ -1414,7 +1414,7 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
if (!crtc_state->has_pch_encoder)
return 0;
- return intel_reserve_shared_dplls(state, crtc, NULL);
+ return intel_reserve_dplls(state, crtc, NULL);
}
static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e63568be3150..f1b704f369f9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -52,21 +52,21 @@
* share a PLL if their configurations match.
*
* This file provides an abstraction over display PLLs. The function
- * intel_shared_dpll_init() initializes the PLLs for the given platform. The
+ * intel_dpll_init() initializes the PLLs for the given platform. The
* users of a PLL are tracked and that tracking is integrated with the atomic
* modset interface. During an atomic operation, required PLLs can be reserved
* for a given CRTC and encoder configuration by calling
- * intel_reserve_shared_dplls() and previously reserved PLLs can be released
- * with intel_release_shared_dplls().
+ * intel_reserve_dplls() and previously reserved PLLs can be released
+ * with intel_release_dplls().
* Changes to the users are first staged in the atomic state, and then made
- * effective by calling intel_shared_dpll_swap_state() during the atomic
+ * effective by calling intel_dpll_swap_state() during the atomic
* commit phase.
*/
/* platform specific hooks for managing DPLLs */
struct intel_dpll_funcs {
/*
- * Hook for enabling the pll, called from intel_enable_shared_dpll() if
+ * Hook for enabling the pll, called from intel_enable_dpll() if
* the pll is not already enabled.
*/
void (*enable)(struct intel_display *display,
@@ -74,7 +74,7 @@ struct intel_dpll_funcs {
const struct intel_dpll_hw_state *dpll_hw_state);
/*
- * Hook for disabling the pll, called from intel_disable_shared_dpll()
+ * Hook for disabling the pll, called from intel_disable_dpll()
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
@@ -133,7 +133,7 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display,
}
static struct intel_dpll_state *
-intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
+intel_atomic_get_dpll_state(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
struct intel_display *display = to_intel_display(state);
@@ -151,7 +151,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
}
/**
- * intel_get_shared_dpll_by_id - get a DPLL given its id
+ * intel_get_dpll_by_id - get a DPLL given its id
* @display: intel_display device instance
* @id: pll id
*
@@ -159,8 +159,8 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
* A pointer to the DPLL with @id
*/
struct intel_dpll *
-intel_get_shared_dpll_by_id(struct intel_display *display,
- enum intel_dpll_id id)
+intel_get_dpll_by_id(struct intel_display *display,
+ enum intel_dpll_id id)
{
struct intel_dpll *pll;
int i;
@@ -175,9 +175,9 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
}
/* For ILK+ */
-void assert_shared_dpll(struct intel_display *display,
- struct intel_dpll *pll,
- bool state)
+void assert_dpll(struct intel_display *display,
+ struct intel_dpll *pll,
+ bool state)
{
bool cur_state;
struct intel_dpll_hw_state hw_state;
@@ -250,12 +250,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display,
}
/**
- * intel_enable_shared_dpll - enable a CRTC's shared DPLL
- * @crtc_state: CRTC, and its state, which has a shared DPLL
+ * intel_enable_dpll - enable a CRTC's global DPLL
+ * @crtc_state: CRTC, and its state, which has a DPLL
*
- * Enable the shared DPLL used by @crtc.
+ * Enable DPLL used by @crtc.
*/
-void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
+void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -282,7 +282,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
if (old_mask) {
drm_WARN_ON(display->drm, !pll->on);
- assert_shared_dpll_enabled(display, pll);
+ assert_dpll_enabled(display, pll);
goto out;
}
drm_WARN_ON(display->drm, pll->on);
@@ -296,12 +296,12 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
}
/**
- * intel_disable_shared_dpll - disable a CRTC's shared DPLL
+ * intel_disable_dpll - disable a CRTC's shared DPLL
* @crtc_state: CRTC, and its state, which has a shared DPLL
*
- * Disable the shared DPLL used by @crtc.
+ * Disable DPLL used by @crtc.
*/
-void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
+void intel_disable_dpll(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -326,7 +326,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->info->name, pll->active_mask, pll->on,
crtc->base.base.id, crtc->base.name);
- assert_shared_dpll_enabled(display, pll);
+ assert_dpll_enabled(display, pll);
drm_WARN_ON(display->drm, !pll->on);
pll->active_mask &= ~pipe_mask;
@@ -358,10 +358,10 @@ intel_dpll_mask_all(struct intel_display *display)
}
static struct intel_dpll *
-intel_find_shared_dpll(struct intel_atomic_state *state,
- const struct intel_crtc *crtc,
- const struct intel_dpll_hw_state *dpll_hw_state,
- unsigned long dpll_mask)
+intel_find_dpll(struct intel_atomic_state *state,
+ const struct intel_crtc *crtc,
+ const struct intel_dpll_hw_state *dpll_hw_state,
+ unsigned long dpll_mask)
{
struct intel_display *display = to_intel_display(crtc);
unsigned long dpll_mask_all = intel_dpll_mask_all(display);
@@ -369,14 +369,14 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
struct intel_dpll *unused_pll = NULL;
enum intel_dpll_id id;
- dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_dpll_state(&state->base);
drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
struct intel_dpll *pll;
- pll = intel_get_shared_dpll_by_id(display, id);
+ pll = intel_get_dpll_by_id(display, id);
if (!pll)
continue;
@@ -412,7 +412,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
}
/**
- * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
+ * intel_reference_dpll_crtc - Get a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is taken
* @pll: DPLL for which the reference is taken
* @dpll_state: the DPLL atomic state in which the reference is tracked
@@ -420,9 +420,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
* Take a reference for @pll tracking the use of it by @crtc.
*/
static void
-intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_dpll *pll,
- struct intel_dpll_state *dpll_state)
+intel_reference_dpll_crtc(const struct intel_crtc *crtc,
+ const struct intel_dpll *pll,
+ struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
@@ -435,23 +435,23 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
}
static void
-intel_reference_shared_dpll(struct intel_atomic_state *state,
- const struct intel_crtc *crtc,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+intel_reference_dpll(struct intel_atomic_state *state,
+ const struct intel_crtc *crtc,
+ const struct intel_dpll *pll,
+ const struct intel_dpll_hw_state *dpll_hw_state)
{
struct intel_dpll_state *dpll_state;
- dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_dpll_state(&state->base);
if (dpll_state[pll->index].pipe_mask == 0)
dpll_state[pll->index].hw_state = *dpll_hw_state;
- intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
+ intel_reference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
}
/**
- * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
+ * intel_unreference_dpll_crtc - Drop a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is dropped
* @pll: DPLL for which the reference is dropped
* @dpll_state: the DPLL atomic state in which the reference is tracked
@@ -459,9 +459,9 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
* Drop a reference for @pll tracking the end of use of it by @crtc.
*/
void
-intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_dpll *pll,
- struct intel_dpll_state *dpll_state)
+intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
+ const struct intel_dpll *pll,
+ struct intel_dpll_state *dpll_state)
{
struct intel_display *display = to_intel_display(crtc);
@@ -473,15 +473,15 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
crtc->base.base.id, crtc->base.name, pll->info->name);
}
-static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
- const struct intel_crtc *crtc,
- const struct intel_dpll *pll)
+static void intel_unreference_dpll(struct intel_atomic_state *state,
+ const struct intel_crtc *crtc,
+ const struct intel_dpll *pll)
{
struct intel_dpll_state *dpll_state;
- dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
+ dpll_state = intel_atomic_get_dpll_state(&state->base);
- intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
+ intel_unreference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
}
static void intel_put_dpll(struct intel_atomic_state *state,
@@ -497,11 +497,11 @@ static void intel_put_dpll(struct intel_atomic_state *state,
if (!old_crtc_state->intel_dpll)
return;
- intel_unreference_shared_dpll(state, crtc, old_crtc_state->intel_dpll);
+ intel_unreference_dpll(state, crtc, old_crtc_state->intel_dpll);
}
/**
- * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
+ * intel_dpll_swap_state - make atomic DPLL configuration effective
* @state: atomic state
*
* This is the dpll version of drm_atomic_helper_swap_state() since the
@@ -511,7 +511,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
* i.e. it also puts the current state into @state, even though there is no
* need for that at this moment.
*/
-void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
+void intel_dpll_swap_state(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct intel_dpll_state *dpll_state = state->dpll_state;
@@ -620,25 +620,25 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
if (HAS_PCH_IBX(display)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
id = (enum intel_dpll_id) crtc->pipe;
- pll = intel_get_shared_dpll_by_id(display, id);
+ pll = intel_get_dpll_by_id(display, id);
drm_dbg_kms(display->drm,
"[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name,
pll->info->name);
} else {
- pll = intel_find_shared_dpll(state, crtc,
- &crtc_state->dpll_hw_state,
- BIT(DPLL_ID_PCH_PLL_B) |
- BIT(DPLL_ID_PCH_PLL_A));
+ pll = intel_find_dpll(state, crtc,
+ &crtc_state->dpll_hw_state,
+ BIT(DPLL_ID_PCH_PLL_B) |
+ BIT(DPLL_ID_PCH_PLL_A));
}
if (!pll)
return -EINVAL;
/* reference the pll */
- intel_reference_shared_dpll(state, crtc,
- pll, &crtc_state->dpll_hw_state);
+ intel_reference_dpll(state, crtc,
+ pll, &crtc_state->dpll_hw_state);
crtc_state->intel_dpll = pll;
@@ -1066,7 +1066,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- return intel_find_shared_dpll(state, crtc,
+ return intel_find_dpll(state, crtc,
&crtc_state->dpll_hw_state,
BIT(DPLL_ID_WRPLL2) |
BIT(DPLL_ID_WRPLL1));
@@ -1113,7 +1113,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return NULL;
}
- pll = intel_get_shared_dpll_by_id(display, pll_id);
+ pll = intel_get_dpll_by_id(display, pll_id);
if (!pll)
return NULL;
@@ -1169,7 +1169,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
+ return intel_find_dpll(state, crtc, &crtc_state->dpll_hw_state,
BIT(DPLL_ID_SPLL));
}
@@ -1233,8 +1233,8 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
if (!pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
- pll, &crtc_state->dpll_hw_state);
+ intel_reference_dpll(state, crtc,
+ pll, &crtc_state->dpll_hw_state);
crtc_state->intel_dpll = pll;
@@ -1942,20 +1942,20 @@ static int skl_get_dpll(struct intel_atomic_state *state,
struct intel_dpll *pll;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
- pll = intel_find_shared_dpll(state, crtc,
- &crtc_state->dpll_hw_state,
- BIT(DPLL_ID_SKL_DPLL0));
+ pll = intel_find_dpll(state, crtc,
+ &crtc_state->dpll_hw_state,
+ BIT(DPLL_ID_SKL_DPLL0));
else
- pll = intel_find_shared_dpll(state, crtc,
- &crtc_state->dpll_hw_state,
- BIT(DPLL_ID_SKL_DPLL3) |
- BIT(DPLL_ID_SKL_DPLL2) |
- BIT(DPLL_ID_SKL_DPLL1));
+ pll = intel_find_dpll(state, crtc,
+ &crtc_state->dpll_hw_state,
+ BIT(DPLL_ID_SKL_DPLL3) |
+ BIT(DPLL_ID_SKL_DPLL2) |
+ BIT(DPLL_ID_SKL_DPLL1));
if (!pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
- pll, &crtc_state->dpll_hw_state);
+ intel_reference_dpll(state, crtc,
+ pll, &crtc_state->dpll_hw_state);
crtc_state->intel_dpll = pll;
@@ -2434,13 +2434,13 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
/* 1:1 mapping between ports and PLLs */
id = (enum intel_dpll_id) encoder->port;
- pll = intel_get_shared_dpll_by_id(display, id);
+ pll = intel_get_dpll_by_id(display, id);
drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
crtc->base.base.id, crtc->base.name, pll->info->name);
- intel_reference_shared_dpll(state, crtc,
- pll, &crtc_state->dpll_hw_state);
+ intel_reference_dpll(state, crtc,
+ pll, &crtc_state->dpll_hw_state);
crtc_state->intel_dpll = pll;
@@ -3388,14 +3388,14 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
/* Eliminate DPLLs from consideration if reserved by HTI */
dpll_mask &= ~intel_hti_dpll_mask(display);
- port_dpll->pll = intel_find_shared_dpll(state, crtc,
- &port_dpll->hw_state,
- dpll_mask);
+ port_dpll->pll = intel_find_dpll(state, crtc,
+ &port_dpll->hw_state,
+ dpll_mask);
if (!port_dpll->pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
- port_dpll->pll, &port_dpll->hw_state);
+ intel_reference_dpll(state, crtc,
+ port_dpll->pll, &port_dpll->hw_state);
icl_update_active_dpll(state, crtc, encoder);
@@ -3452,26 +3452,25 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
int ret;
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
- port_dpll->pll = intel_find_shared_dpll(state, crtc,
- &port_dpll->hw_state,
- BIT(DPLL_ID_ICL_TBTPLL));
+ port_dpll->pll = intel_find_dpll(state, crtc,
+ &port_dpll->hw_state,
+ BIT(DPLL_ID_ICL_TBTPLL));
if (!port_dpll->pll)
return -EINVAL;
- intel_reference_shared_dpll(state, crtc,
- port_dpll->pll, &port_dpll->hw_state);
-
+ intel_reference_dpll(state, crtc,
+ port_dpll->pll, &port_dpll->hw_state);
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder));
- port_dpll->pll = intel_find_shared_dpll(state, crtc,
- &port_dpll->hw_state,
- BIT(dpll_id));
+ port_dpll->pll = intel_find_dpll(state, crtc,
+ &port_dpll->hw_state,
+ BIT(dpll_id));
if (!port_dpll->pll) {
ret = -EINVAL;
goto err_unreference_tbt_pll;
}
- intel_reference_shared_dpll(state, crtc,
- port_dpll->pll, &port_dpll->hw_state);
+ intel_reference_dpll(state, crtc,
+ port_dpll->pll, &port_dpll->hw_state);
icl_update_active_dpll(state, crtc, encoder);
@@ -3479,7 +3478,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
err_unreference_tbt_pll:
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
- intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
+ intel_unreference_dpll(state, crtc, port_dpll->pll);
return ret;
}
@@ -3534,7 +3533,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
if (!old_port_dpll->pll)
continue;
- intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
+ intel_unreference_dpll(state, crtc, old_port_dpll->pll);
}
}
@@ -4300,12 +4299,12 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
};
/**
- * intel_shared_dpll_init - Initialize shared DPLLs
+ * intel_dpll_init - Initialize DPLLs
* @display: intel_display device
*
- * Initialize shared DPLLs for @display.
+ * Initialize DPLLs for @display.
*/
-void intel_shared_dpll_init(struct intel_display *display)
+void intel_dpll_init(struct intel_display *display)
{
const struct intel_dpll_mgr *dpll_mgr = NULL;
const struct dpll_info *dpll_info;
@@ -4362,7 +4361,7 @@ void intel_shared_dpll_init(struct intel_display *display)
}
/**
- * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
+ * intel_compute_dplls - compute DPLL state CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to compute DPLLs for
* @encoder: encoder
@@ -4370,14 +4369,14 @@ void intel_shared_dpll_init(struct intel_display *display)
* This function computes the DPLL state for the given CRTC and encoder.
*
* The new configuration in the atomic commit @state is made effective by
- * calling intel_shared_dpll_swap_state().
+ * calling intel_dpll_swap_state().
*
* Returns:
* 0 on success, negative error code on failure.
*/
-int intel_compute_shared_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+int intel_compute_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(state);
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
@@ -4389,7 +4388,7 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
}
/**
- * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
+ * intel_reserve_dplls - reserve DPLLs for CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to reserve DPLLs for
* @encoder: encoder
@@ -4399,18 +4398,18 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
* state.
*
* The new configuration in the atomic commit @state is made effective by
- * calling intel_shared_dpll_swap_state().
+ * calling intel_dpll_swap_state().
*
* The reserved DPLLs should be released by calling
- * intel_release_shared_dplls().
+ * intel_release_dplls().
*
* Returns:
* 0 if all required DPLLs were successfully reserved,
* negative error code otherwise.
*/
-int intel_reserve_shared_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+int intel_reserve_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(state);
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
@@ -4422,18 +4421,18 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
}
/**
- * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
+ * intel_release_dplls - end use of DPLLs by CRTC in atomic state
* @state: atomic state
* @crtc: crtc from which the DPLLs are to be released
*
- * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
+ * This function releases all DPLLs reserved by intel_reserve_dplls()
* from the current atomic commit @state and the old @crtc atomic state.
*
* The new configuration in the atomic commit @state is made effective by
- * calling intel_shared_dpll_swap_state().
+ * calling intel_dpll_swap_state().
*/
-void intel_release_shared_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+void intel_release_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
@@ -4441,7 +4440,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
/*
* FIXME: this function is called for every platform having a
* compute_clock hook, even though the platform doesn't yet support
- * the shared DPLL framework and intel_reserve_shared_dplls() is not
+ * the global DPLL framework and intel_reserve_dplls() is not
* called on those.
*/
if (!dpll_mgr)
@@ -4457,7 +4456,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
* @encoder: encoder determining the type of port DPLL
*
* Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
- * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
+ * from the port DPLLs reserved previously by intel_reserve_dplls(). The
* DPLL selected will be based on the current mode of the encoder's port.
*/
void intel_update_active_dpll(struct intel_atomic_state *state,
@@ -4522,7 +4521,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
to_intel_crtc_state(crtc->base.state);
if (crtc_state->hw.active && crtc_state->intel_dpll == pll)
- intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
+ intel_reference_dpll_crtc(crtc, pll, &pll->state);
}
pll->active_mask = pll->state.pipe_mask;
@@ -4683,8 +4682,8 @@ static bool has_alt_port_dpll(const struct intel_dpll *old_pll,
(old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
}
-void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+void intel_dpll_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
const struct intel_crtc_state *old_crtc_state =
@@ -4714,7 +4713,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
}
}
-void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
+void intel_dpll_verify_disabled(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
struct intel_dpll *pll;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 3604ebbc78b5..99a058deaeda 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -387,26 +387,26 @@ struct intel_dpll {
#define SKL_DPLL2 2
#define SKL_DPLL3 3
-/* shared dpll functions */
+/* global dpll functions */
struct intel_dpll *
-intel_get_shared_dpll_by_id(struct intel_display *display,
- enum intel_dpll_id id);
-void assert_shared_dpll(struct intel_display *display,
- struct intel_dpll *pll,
- bool state);
-#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
-#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
-int intel_compute_shared_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
-int intel_reserve_shared_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
-void intel_release_shared_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
-void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
- const struct intel_dpll *pll,
- struct intel_dpll_state *shared_dpll_state);
+intel_get_dpll_by_id(struct intel_display *display,
+ enum intel_dpll_id id);
+void assert_dpll(struct intel_display *display,
+ struct intel_dpll *pll,
+ bool state);
+#define assert_dpll_enabled(d, p) assert_dpll(d, p, true)
+#define assert_dpll_disabled(d, p) assert_dpll(d, p, false)
+int intel_compute_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
+int intel_reserve_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
+void intel_release_dplls(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+void intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
+ const struct intel_dpll *pll,
+ struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
enum icl_port_dpll_id port_dpll_id);
void intel_update_active_dpll(struct intel_atomic_state *state,
@@ -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display *display,
bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
-void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
-void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
-void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
-void intel_shared_dpll_init(struct intel_display *display);
+void intel_enable_dpll(const struct intel_crtc_state *crtc_state);
+void intel_disable_dpll(const struct intel_crtc_state *crtc_state);
+void intel_dpll_swap_state(struct intel_atomic_state *state);
+void intel_dpll_init(struct intel_display *display);
void intel_dpll_update_ref_clks(struct intel_display *display);
void intel_dpll_readout_hw_state(struct intel_display *display);
void intel_dpll_sanitize_state(struct intel_display *display);
@@ -435,8 +435,8 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);
-void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
-void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);
+void intel_dpll_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+void intel_dpll_verify_disabled(struct intel_atomic_state *state);
#endif /* _INTEL_DPLL_MGR_H_ */
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index ec8f38fba178..f07c7ef56148 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -249,7 +249,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
if (HAS_PCH_SPLIT(display)) {
assert_fdi_rx_pll_disabled(display, pipe);
- assert_shared_dpll_disabled(display, crtc_state->intel_dpll);
+ assert_dpll_disabled(display, crtc_state->intel_dpll);
} else {
assert_pll_disabled(display, pipe);
}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 46e0002a1358..ed4f305e0d3e 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -93,9 +93,9 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
crtc->base.enabled = false;
if (crtc_state->intel_dpll)
- intel_unreference_shared_dpll_crtc(crtc,
- crtc_state->intel_dpll,
- &crtc_state->intel_dpll->state);
+ intel_unreference_dpll_crtc(crtc,
+ crtc_state->intel_dpll,
+ &crtc_state->intel_dpll->state);
}
static void set_encoder_for_connector(struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 766a9983665a..f2f6b9d9afa1 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -243,7 +243,7 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
intel_wm_state_verify(state, crtc);
verify_connector_state(state, crtc);
verify_crtc_state(state, crtc);
- intel_shared_dpll_state_verify(state, crtc);
+ intel_dpll_state_verify(state, crtc);
intel_mpllb_state_verify(state, crtc);
intel_cx0pll_state_verify(state, crtc);
}
@@ -252,5 +252,5 @@ void intel_modeset_verify_disabled(struct intel_atomic_state *state)
{
verify_encoder_state(state);
verify_connector_state(state, NULL);
- intel_shared_dpll_verify_disabled(state);
+ intel_dpll_verify_disabled(state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index b38305c16e77..b59b3c94f711 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -251,7 +251,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
u32 val, pipeconf_val;
/* Make sure PCH DPLL is enabled */
- assert_shared_dpll_enabled(display, crtc_state->intel_dpll);
+ assert_dpll_enabled(display, crtc_state->intel_dpll);
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(display, pipe);
@@ -382,7 +382,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
if (crtc_state->intel_dpll ==
- intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
+ intel_get_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
temp |= sel;
else
temp &= ~sel;
@@ -394,11 +394,11 @@ void ilk_pch_enable(struct intel_atomic_state *state,
* transcoder, and we actually should do this to not upset any PCH
* transcoder that already use the clock when we share it.
*
- * Note that enable_shared_dpll tries to do the right thing, but
- * get_shared_dpll unconditionally resets the pll - we need that
+ * Note that enable_dpll tries to do the right thing, but
+ * get_dpll unconditionally resets the pll - we need that
* to have the right LVDS enable sequence.
*/
- intel_enable_shared_dpll(crtc_state);
+ intel_enable_dpll(crtc_state);
/* set transcoder timing, panel must allow it */
assert_pps_unlocked(display, pipe);
@@ -472,7 +472,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state,
ilk_fdi_pll_disable(crtc);
- intel_disable_shared_dpll(old_crtc_state);
+ intel_disable_dpll(old_crtc_state);
}
static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
@@ -528,7 +528,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
pll_id = DPLL_ID_PCH_PLL_A;
}
- crtc_state->intel_dpll = intel_get_shared_dpll_by_id(display, pll_id);
+ crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id);
pll = crtc_state->intel_dpll;
pll_active = intel_dpll_get_hw_state(display, pll,
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 07/18] drm/i915/dpll: Move away from using shared dpll
2025-05-09 4:27 ` [PATCH 07/18] drm/i915/dpll: Move away from using shared dpll Suraj Kandpal
@ 2025-05-09 10:17 ` Jani Nikula
2025-05-12 4:02 ` Kandpal, Suraj
0 siblings, 1 reply; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:17 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename functions to move away from using shared dpll in the dpll
> framework as much as possible since dpll may not always be shared.
I think you're replacing some "shared dpll" with "global dpll" in
comments, which should just drop shared and not mention global. Comments
inline.
With them fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> --v2
> -Use intel_dpll_global instead of global_dpll [Jani]
>
> --v3
> -Just use intel_dpll [Jani]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
> drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> .../drm/i915/display/intel_display_driver.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 10 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 235 +++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 52 ++--
> drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> .../drm/i915/display/intel_modeset_setup.c | 6 +-
> .../drm/i915/display/intel_modeset_verify.c | 4 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 14 +-
> 10 files changed, 173 insertions(+), 174 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4d631cbc81d2..11ebcb40c91f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1569,7 +1569,7 @@ _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
>
> id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_by_id(display, id);
> }
>
> static void adls_ddi_enable_clock(struct intel_encoder *encoder,
> @@ -1723,7 +1723,7 @@ static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
> if (phy >= PHY_C)
> id += DPLL_ID_DG1_DPLL2;
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_by_id(display, id);
> }
>
> static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
> @@ -1895,7 +1895,7 @@ static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
> return NULL;
> }
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_by_id(display, id);
> }
>
> static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
> @@ -1918,7 +1918,7 @@ static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
> return NULL;
> }
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_by_id(display, id);
> }
>
> static void skl_ddi_enable_clock(struct intel_encoder *encoder,
> @@ -1986,7 +1986,7 @@ static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
> id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
> DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_by_id(display, id);
> }
>
> void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> @@ -2053,7 +2053,7 @@ static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
> return NULL;
> }
>
> - return intel_get_shared_dpll_by_id(display, id);
> + return intel_get_dpll_by_id(display, id);
> }
>
> void intel_ddi_enable_clock(struct intel_encoder *encoder,
> @@ -2760,7 +2760,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> * 4. Enable the port PLL.
> *
> * The PLL enabling itself was already done before this function by
> - * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
> + * hsw_crtc_enable()->intel_enable_dpll(). We need only
> * configure the PLL to port mapping here.
> */
> intel_ddi_enable_clock(encoder, crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b765d5765b32..ce5c9e74475d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1664,7 +1664,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> intel_encoders_pre_pll_enable(state, crtc);
>
> if (new_crtc_state->intel_dpll)
> - intel_enable_shared_dpll(new_crtc_state);
> + intel_enable_dpll(new_crtc_state);
>
> intel_encoders_pre_enable(state, crtc);
>
> @@ -1793,7 +1793,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> intel_encoders_disable(state, crtc);
> intel_encoders_post_disable(state, crtc);
>
> - intel_disable_shared_dpll(old_crtc_state);
> + intel_disable_dpll(old_crtc_state);
>
> intel_encoders_post_pll_disable(state, crtc);
>
> @@ -6434,7 +6434,7 @@ int intel_atomic_check(struct drm_device *dev,
>
> any_ms = true;
>
> - intel_release_shared_dplls(state, crtc);
> + intel_release_dplls(state, crtc);
> }
>
> if (any_ms && !check_digital_port_conflicts(state)) {
> @@ -7531,7 +7531,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state)
>
> intel_atomic_swap_global_state(state);
>
> - intel_shared_dpll_swap_state(state);
> + intel_dpll_swap_state(state);
>
> intel_atomic_track_fbs(state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 5c74ab5fd1aa..16d91be02bb9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -446,7 +446,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
> }
>
> intel_plane_possible_crtcs_init(display);
> - intel_shared_dpll_init(display);
> + intel_dpll_init(display);
> intel_fdi_pll_freq_update(display);
>
> intel_update_czclk(display);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 4d1f7fccd28a..db67e92505d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1161,7 +1161,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
>
> - ret = intel_compute_shared_dplls(state, crtc, encoder);
> + ret = intel_compute_dplls(state, crtc, encoder);
> if (ret)
> return ret;
>
> @@ -1189,7 +1189,7 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
>
> - return intel_reserve_shared_dplls(state, crtc, encoder);
> + return intel_reserve_dplls(state, crtc, encoder);
> }
>
> static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> @@ -1223,7 +1223,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> - /* TODO: Do the readback via intel_compute_shared_dplls() */
> + /* TODO: Do the readback via intel_compute_dplls() */
> crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
>
> crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> @@ -1394,7 +1394,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> ilk_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
>
> - ret = intel_compute_shared_dplls(state, crtc, NULL);
> + ret = intel_compute_dplls(state, crtc, NULL);
> if (ret)
> return ret;
>
> @@ -1414,7 +1414,7 @@ static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> if (!crtc_state->has_pch_encoder)
> return 0;
>
> - return intel_reserve_shared_dplls(state, crtc, NULL);
> + return intel_reserve_dplls(state, crtc, NULL);
> }
>
> static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e63568be3150..f1b704f369f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -52,21 +52,21 @@
> * share a PLL if their configurations match.
> *
> * This file provides an abstraction over display PLLs. The function
> - * intel_shared_dpll_init() initializes the PLLs for the given platform. The
> + * intel_dpll_init() initializes the PLLs for the given platform. The
> * users of a PLL are tracked and that tracking is integrated with the atomic
> * modset interface. During an atomic operation, required PLLs can be reserved
> * for a given CRTC and encoder configuration by calling
> - * intel_reserve_shared_dplls() and previously reserved PLLs can be released
> - * with intel_release_shared_dplls().
> + * intel_reserve_dplls() and previously reserved PLLs can be released
> + * with intel_release_dplls().
> * Changes to the users are first staged in the atomic state, and then made
> - * effective by calling intel_shared_dpll_swap_state() during the atomic
> + * effective by calling intel_dpll_swap_state() during the atomic
> * commit phase.
> */
>
> /* platform specific hooks for managing DPLLs */
> struct intel_dpll_funcs {
> /*
> - * Hook for enabling the pll, called from intel_enable_shared_dpll() if
> + * Hook for enabling the pll, called from intel_enable_dpll() if
> * the pll is not already enabled.
> */
> void (*enable)(struct intel_display *display,
> @@ -74,7 +74,7 @@ struct intel_dpll_funcs {
> const struct intel_dpll_hw_state *dpll_hw_state);
>
> /*
> - * Hook for disabling the pll, called from intel_disable_shared_dpll()
> + * Hook for disabling the pll, called from intel_disable_dpll()
> * only when it is safe to disable the pll, i.e., there are no more
> * tracked users for it.
> */
> @@ -133,7 +133,7 @@ intel_atomic_duplicate_dpll_state(struct intel_display *display,
> }
>
> static struct intel_dpll_state *
> -intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> +intel_atomic_get_dpll_state(struct drm_atomic_state *s)
> {
> struct intel_atomic_state *state = to_intel_atomic_state(s);
> struct intel_display *display = to_intel_display(state);
> @@ -151,7 +151,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> }
>
> /**
> - * intel_get_shared_dpll_by_id - get a DPLL given its id
> + * intel_get_dpll_by_id - get a DPLL given its id
> * @display: intel_display device instance
> * @id: pll id
> *
> @@ -159,8 +159,8 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> * A pointer to the DPLL with @id
> */
> struct intel_dpll *
> -intel_get_shared_dpll_by_id(struct intel_display *display,
> - enum intel_dpll_id id)
> +intel_get_dpll_by_id(struct intel_display *display,
> + enum intel_dpll_id id)
> {
> struct intel_dpll *pll;
> int i;
> @@ -175,9 +175,9 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
> }
>
> /* For ILK+ */
> -void assert_shared_dpll(struct intel_display *display,
> - struct intel_dpll *pll,
> - bool state)
> +void assert_dpll(struct intel_display *display,
> + struct intel_dpll *pll,
> + bool state)
> {
> bool cur_state;
> struct intel_dpll_hw_state hw_state;
> @@ -250,12 +250,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display,
> }
>
> /**
> - * intel_enable_shared_dpll - enable a CRTC's shared DPLL
> - * @crtc_state: CRTC, and its state, which has a shared DPLL
> + * intel_enable_dpll - enable a CRTC's global DPLL
Global?
Isn't what we have in intel_dpll.c now called "global", and this is not
it?
> + * @crtc_state: CRTC, and its state, which has a DPLL
> *
> - * Enable the shared DPLL used by @crtc.
> + * Enable DPLL used by @crtc.
> */
> -void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> +void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -282,7 +282,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
>
> if (old_mask) {
> drm_WARN_ON(display->drm, !pll->on);
> - assert_shared_dpll_enabled(display, pll);
> + assert_dpll_enabled(display, pll);
> goto out;
> }
> drm_WARN_ON(display->drm, pll->on);
> @@ -296,12 +296,12 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> }
>
> /**
> - * intel_disable_shared_dpll - disable a CRTC's shared DPLL
> + * intel_disable_dpll - disable a CRTC's shared DPLL
> * @crtc_state: CRTC, and its state, which has a shared DPLL
> *
> - * Disable the shared DPLL used by @crtc.
> + * Disable DPLL used by @crtc.
> */
> -void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> +void intel_disable_dpll(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -326,7 +326,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
> pll->info->name, pll->active_mask, pll->on,
> crtc->base.base.id, crtc->base.name);
>
> - assert_shared_dpll_enabled(display, pll);
> + assert_dpll_enabled(display, pll);
> drm_WARN_ON(display->drm, !pll->on);
>
> pll->active_mask &= ~pipe_mask;
> @@ -358,10 +358,10 @@ intel_dpll_mask_all(struct intel_display *display)
> }
>
> static struct intel_dpll *
> -intel_find_shared_dpll(struct intel_atomic_state *state,
> - const struct intel_crtc *crtc,
> - const struct intel_dpll_hw_state *dpll_hw_state,
> - unsigned long dpll_mask)
> +intel_find_dpll(struct intel_atomic_state *state,
> + const struct intel_crtc *crtc,
> + const struct intel_dpll_hw_state *dpll_hw_state,
> + unsigned long dpll_mask)
> {
> struct intel_display *display = to_intel_display(crtc);
> unsigned long dpll_mask_all = intel_dpll_mask_all(display);
> @@ -369,14 +369,14 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> struct intel_dpll *unused_pll = NULL;
> enum intel_dpll_id id;
>
> - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> + dpll_state = intel_atomic_get_dpll_state(&state->base);
>
> drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
>
> for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
> struct intel_dpll *pll;
>
> - pll = intel_get_shared_dpll_by_id(display, id);
> + pll = intel_get_dpll_by_id(display, id);
> if (!pll)
> continue;
>
> @@ -412,7 +412,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> }
>
> /**
> - * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
> + * intel_reference_dpll_crtc - Get a DPLL reference for a CRTC
> * @crtc: CRTC on which behalf the reference is taken
> * @pll: DPLL for which the reference is taken
> * @dpll_state: the DPLL atomic state in which the reference is tracked
> @@ -420,9 +420,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> * Take a reference for @pll tracking the use of it by @crtc.
> */
> static void
> -intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> - const struct intel_dpll *pll,
> - struct intel_dpll_state *dpll_state)
> +intel_reference_dpll_crtc(const struct intel_crtc *crtc,
> + const struct intel_dpll *pll,
> + struct intel_dpll_state *dpll_state)
> {
> struct intel_display *display = to_intel_display(crtc);
>
> @@ -435,23 +435,23 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> }
>
> static void
> -intel_reference_shared_dpll(struct intel_atomic_state *state,
> - const struct intel_crtc *crtc,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +intel_reference_dpll(struct intel_atomic_state *state,
> + const struct intel_crtc *crtc,
> + const struct intel_dpll *pll,
> + const struct intel_dpll_hw_state *dpll_hw_state)
> {
> struct intel_dpll_state *dpll_state;
>
> - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> + dpll_state = intel_atomic_get_dpll_state(&state->base);
>
> if (dpll_state[pll->index].pipe_mask == 0)
> dpll_state[pll->index].hw_state = *dpll_hw_state;
>
> - intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> + intel_reference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> }
>
> /**
> - * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
> + * intel_unreference_dpll_crtc - Drop a DPLL reference for a CRTC
> * @crtc: CRTC on which behalf the reference is dropped
> * @pll: DPLL for which the reference is dropped
> * @dpll_state: the DPLL atomic state in which the reference is tracked
> @@ -459,9 +459,9 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
> * Drop a reference for @pll tracking the end of use of it by @crtc.
> */
> void
> -intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> - const struct intel_dpll *pll,
> - struct intel_dpll_state *dpll_state)
> +intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
> + const struct intel_dpll *pll,
> + struct intel_dpll_state *dpll_state)
> {
> struct intel_display *display = to_intel_display(crtc);
>
> @@ -473,15 +473,15 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> crtc->base.base.id, crtc->base.name, pll->info->name);
> }
>
> -static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> - const struct intel_crtc *crtc,
> - const struct intel_dpll *pll)
> +static void intel_unreference_dpll(struct intel_atomic_state *state,
> + const struct intel_crtc *crtc,
> + const struct intel_dpll *pll)
> {
> struct intel_dpll_state *dpll_state;
>
> - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> + dpll_state = intel_atomic_get_dpll_state(&state->base);
>
> - intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> + intel_unreference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> }
>
> static void intel_put_dpll(struct intel_atomic_state *state,
> @@ -497,11 +497,11 @@ static void intel_put_dpll(struct intel_atomic_state *state,
> if (!old_crtc_state->intel_dpll)
> return;
>
> - intel_unreference_shared_dpll(state, crtc, old_crtc_state->intel_dpll);
> + intel_unreference_dpll(state, crtc, old_crtc_state->intel_dpll);
> }
>
> /**
> - * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
> + * intel_dpll_swap_state - make atomic DPLL configuration effective
> * @state: atomic state
> *
> * This is the dpll version of drm_atomic_helper_swap_state() since the
> @@ -511,7 +511,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
> * i.e. it also puts the current state into @state, even though there is no
> * need for that at this moment.
> */
> -void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> +void intel_dpll_swap_state(struct intel_atomic_state *state)
> {
> struct intel_display *display = to_intel_display(state);
> struct intel_dpll_state *dpll_state = state->dpll_state;
> @@ -620,25 +620,25 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
> if (HAS_PCH_IBX(display)) {
> /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
> id = (enum intel_dpll_id) crtc->pipe;
> - pll = intel_get_shared_dpll_by_id(display, id);
> + pll = intel_get_dpll_by_id(display, id);
>
> drm_dbg_kms(display->drm,
> "[CRTC:%d:%s] using pre-allocated %s\n",
> crtc->base.base.id, crtc->base.name,
> pll->info->name);
> } else {
> - pll = intel_find_shared_dpll(state, crtc,
> - &crtc_state->dpll_hw_state,
> - BIT(DPLL_ID_PCH_PLL_B) |
> - BIT(DPLL_ID_PCH_PLL_A));
> + pll = intel_find_dpll(state, crtc,
> + &crtc_state->dpll_hw_state,
> + BIT(DPLL_ID_PCH_PLL_B) |
> + BIT(DPLL_ID_PCH_PLL_A));
> }
>
> if (!pll)
> return -EINVAL;
>
> /* reference the pll */
> - intel_reference_shared_dpll(state, crtc,
> - pll, &crtc_state->dpll_hw_state);
> + intel_reference_dpll(state, crtc,
> + pll, &crtc_state->dpll_hw_state);
>
> crtc_state->intel_dpll = pll;
>
> @@ -1066,7 +1066,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - return intel_find_shared_dpll(state, crtc,
> + return intel_find_dpll(state, crtc,
> &crtc_state->dpll_hw_state,
> BIT(DPLL_ID_WRPLL2) |
> BIT(DPLL_ID_WRPLL1));
> @@ -1113,7 +1113,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> return NULL;
> }
>
> - pll = intel_get_shared_dpll_by_id(display, pll_id);
> + pll = intel_get_dpll_by_id(display, pll_id);
>
> if (!pll)
> return NULL;
> @@ -1169,7 +1169,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
> + return intel_find_dpll(state, crtc, &crtc_state->dpll_hw_state,
> BIT(DPLL_ID_SPLL));
> }
>
> @@ -1233,8 +1233,8 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
> if (!pll)
> return -EINVAL;
>
> - intel_reference_shared_dpll(state, crtc,
> - pll, &crtc_state->dpll_hw_state);
> + intel_reference_dpll(state, crtc,
> + pll, &crtc_state->dpll_hw_state);
>
> crtc_state->intel_dpll = pll;
>
> @@ -1942,20 +1942,20 @@ static int skl_get_dpll(struct intel_atomic_state *state,
> struct intel_dpll *pll;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> - pll = intel_find_shared_dpll(state, crtc,
> - &crtc_state->dpll_hw_state,
> - BIT(DPLL_ID_SKL_DPLL0));
> + pll = intel_find_dpll(state, crtc,
> + &crtc_state->dpll_hw_state,
> + BIT(DPLL_ID_SKL_DPLL0));
> else
> - pll = intel_find_shared_dpll(state, crtc,
> - &crtc_state->dpll_hw_state,
> - BIT(DPLL_ID_SKL_DPLL3) |
> - BIT(DPLL_ID_SKL_DPLL2) |
> - BIT(DPLL_ID_SKL_DPLL1));
> + pll = intel_find_dpll(state, crtc,
> + &crtc_state->dpll_hw_state,
> + BIT(DPLL_ID_SKL_DPLL3) |
> + BIT(DPLL_ID_SKL_DPLL2) |
> + BIT(DPLL_ID_SKL_DPLL1));
> if (!pll)
> return -EINVAL;
>
> - intel_reference_shared_dpll(state, crtc,
> - pll, &crtc_state->dpll_hw_state);
> + intel_reference_dpll(state, crtc,
> + pll, &crtc_state->dpll_hw_state);
>
> crtc_state->intel_dpll = pll;
>
> @@ -2434,13 +2434,13 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
>
> /* 1:1 mapping between ports and PLLs */
> id = (enum intel_dpll_id) encoder->port;
> - pll = intel_get_shared_dpll_by_id(display, id);
> + pll = intel_get_dpll_by_id(display, id);
>
> drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
> crtc->base.base.id, crtc->base.name, pll->info->name);
>
> - intel_reference_shared_dpll(state, crtc,
> - pll, &crtc_state->dpll_hw_state);
> + intel_reference_dpll(state, crtc,
> + pll, &crtc_state->dpll_hw_state);
>
> crtc_state->intel_dpll = pll;
>
> @@ -3388,14 +3388,14 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> /* Eliminate DPLLs from consideration if reserved by HTI */
> dpll_mask &= ~intel_hti_dpll_mask(display);
>
> - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> - &port_dpll->hw_state,
> - dpll_mask);
> + port_dpll->pll = intel_find_dpll(state, crtc,
> + &port_dpll->hw_state,
> + dpll_mask);
> if (!port_dpll->pll)
> return -EINVAL;
>
> - intel_reference_shared_dpll(state, crtc,
> - port_dpll->pll, &port_dpll->hw_state);
> + intel_reference_dpll(state, crtc,
> + port_dpll->pll, &port_dpll->hw_state);
>
> icl_update_active_dpll(state, crtc, encoder);
>
> @@ -3452,26 +3452,25 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
> int ret;
>
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> - &port_dpll->hw_state,
> - BIT(DPLL_ID_ICL_TBTPLL));
> + port_dpll->pll = intel_find_dpll(state, crtc,
> + &port_dpll->hw_state,
> + BIT(DPLL_ID_ICL_TBTPLL));
> if (!port_dpll->pll)
> return -EINVAL;
> - intel_reference_shared_dpll(state, crtc,
> - port_dpll->pll, &port_dpll->hw_state);
> -
> + intel_reference_dpll(state, crtc,
> + port_dpll->pll, &port_dpll->hw_state);
>
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder));
> - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> - &port_dpll->hw_state,
> - BIT(dpll_id));
> + port_dpll->pll = intel_find_dpll(state, crtc,
> + &port_dpll->hw_state,
> + BIT(dpll_id));
> if (!port_dpll->pll) {
> ret = -EINVAL;
> goto err_unreference_tbt_pll;
> }
> - intel_reference_shared_dpll(state, crtc,
> - port_dpll->pll, &port_dpll->hw_state);
> + intel_reference_dpll(state, crtc,
> + port_dpll->pll, &port_dpll->hw_state);
>
> icl_update_active_dpll(state, crtc, encoder);
>
> @@ -3479,7 +3478,7 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>
> err_unreference_tbt_pll:
> port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> - intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
> + intel_unreference_dpll(state, crtc, port_dpll->pll);
>
> return ret;
> }
> @@ -3534,7 +3533,7 @@ static void icl_put_dplls(struct intel_atomic_state *state,
> if (!old_port_dpll->pll)
> continue;
>
> - intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
> + intel_unreference_dpll(state, crtc, old_port_dpll->pll);
> }
> }
>
> @@ -4300,12 +4299,12 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
> };
>
> /**
> - * intel_shared_dpll_init - Initialize shared DPLLs
> + * intel_dpll_init - Initialize DPLLs
> * @display: intel_display device
> *
> - * Initialize shared DPLLs for @display.
> + * Initialize DPLLs for @display.
> */
> -void intel_shared_dpll_init(struct intel_display *display)
> +void intel_dpll_init(struct intel_display *display)
> {
> const struct intel_dpll_mgr *dpll_mgr = NULL;
> const struct dpll_info *dpll_info;
> @@ -4362,7 +4361,7 @@ void intel_shared_dpll_init(struct intel_display *display)
> }
>
> /**
> - * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
> + * intel_compute_dplls - compute DPLL state CRTC and encoder combination
> * @state: atomic state
> * @crtc: CRTC to compute DPLLs for
> * @encoder: encoder
> @@ -4370,14 +4369,14 @@ void intel_shared_dpll_init(struct intel_display *display)
> * This function computes the DPLL state for the given CRTC and encoder.
> *
> * The new configuration in the atomic commit @state is made effective by
> - * calling intel_shared_dpll_swap_state().
> + * calling intel_dpll_swap_state().
> *
> * Returns:
> * 0 on success, negative error code on failure.
> */
> -int intel_compute_shared_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +int intel_compute_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(state);
> const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
> @@ -4389,7 +4388,7 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
> }
>
> /**
> - * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
> + * intel_reserve_dplls - reserve DPLLs for CRTC and encoder combination
> * @state: atomic state
> * @crtc: CRTC to reserve DPLLs for
> * @encoder: encoder
> @@ -4399,18 +4398,18 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
> * state.
> *
> * The new configuration in the atomic commit @state is made effective by
> - * calling intel_shared_dpll_swap_state().
> + * calling intel_dpll_swap_state().
> *
> * The reserved DPLLs should be released by calling
> - * intel_release_shared_dplls().
> + * intel_release_dplls().
> *
> * Returns:
> * 0 if all required DPLLs were successfully reserved,
> * negative error code otherwise.
> */
> -int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +int intel_reserve_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(state);
> const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
> @@ -4422,18 +4421,18 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> }
>
> /**
> - * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
> + * intel_release_dplls - end use of DPLLs by CRTC in atomic state
> * @state: atomic state
> * @crtc: crtc from which the DPLLs are to be released
> *
> - * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
> + * This function releases all DPLLs reserved by intel_reserve_dplls()
> * from the current atomic commit @state and the old @crtc atomic state.
> *
> * The new configuration in the atomic commit @state is made effective by
> - * calling intel_shared_dpll_swap_state().
> + * calling intel_dpll_swap_state().
> */
> -void intel_release_shared_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +void intel_release_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
> @@ -4441,7 +4440,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
> /*
> * FIXME: this function is called for every platform having a
> * compute_clock hook, even though the platform doesn't yet support
> - * the shared DPLL framework and intel_reserve_shared_dplls() is not
> + * the global DPLL framework and intel_reserve_dplls() is not
Global?
> * called on those.
> */
> if (!dpll_mgr)
> @@ -4457,7 +4456,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
> * @encoder: encoder determining the type of port DPLL
> *
> * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
> - * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
> + * from the port DPLLs reserved previously by intel_reserve_dplls(). The
> * DPLL selected will be based on the current mode of the encoder's port.
> */
> void intel_update_active_dpll(struct intel_atomic_state *state,
> @@ -4522,7 +4521,7 @@ static void readout_dpll_hw_state(struct intel_display *display,
> to_intel_crtc_state(crtc->base.state);
>
> if (crtc_state->hw.active && crtc_state->intel_dpll == pll)
> - intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
> + intel_reference_dpll_crtc(crtc, pll, &pll->state);
> }
> pll->active_mask = pll->state.pipe_mask;
>
> @@ -4683,8 +4682,8 @@ static bool has_alt_port_dpll(const struct intel_dpll *old_pll,
> (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll);
> }
>
> -void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +void intel_dpll_state_verify(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> const struct intel_crtc_state *old_crtc_state =
> @@ -4714,7 +4713,7 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> }
> }
>
> -void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
> +void intel_dpll_verify_disabled(struct intel_atomic_state *state)
> {
> struct intel_display *display = to_intel_display(state);
> struct intel_dpll *pll;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 3604ebbc78b5..99a058deaeda 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -387,26 +387,26 @@ struct intel_dpll {
> #define SKL_DPLL2 2
> #define SKL_DPLL3 3
>
> -/* shared dpll functions */
> +/* global dpll functions */
Global?
> struct intel_dpll *
> -intel_get_shared_dpll_by_id(struct intel_display *display,
> - enum intel_dpll_id id);
> -void assert_shared_dpll(struct intel_display *display,
> - struct intel_dpll *pll,
> - bool state);
> -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> -#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> -int intel_compute_shared_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder);
> -int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder);
> -void intel_release_shared_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> -void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> - const struct intel_dpll *pll,
> - struct intel_dpll_state *shared_dpll_state);
> +intel_get_dpll_by_id(struct intel_display *display,
> + enum intel_dpll_id id);
> +void assert_dpll(struct intel_display *display,
> + struct intel_dpll *pll,
> + bool state);
> +#define assert_dpll_enabled(d, p) assert_dpll(d, p, true)
> +#define assert_dpll_disabled(d, p) assert_dpll(d, p, false)
> +int intel_compute_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder);
> +int intel_reserve_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder);
> +void intel_release_dplls(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> +void intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
> + const struct intel_dpll *pll,
> + struct intel_dpll_state *shared_dpll_state);
> void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> enum icl_port_dpll_id port_dpll_id);
> void intel_update_active_dpll(struct intel_atomic_state *state,
> @@ -418,10 +418,10 @@ int intel_dpll_get_freq(struct intel_display *display,
> bool intel_dpll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state);
> -void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> -void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
> -void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
> -void intel_shared_dpll_init(struct intel_display *display);
> +void intel_enable_dpll(const struct intel_crtc_state *crtc_state);
> +void intel_disable_dpll(const struct intel_crtc_state *crtc_state);
> +void intel_dpll_swap_state(struct intel_atomic_state *state);
> +void intel_dpll_init(struct intel_display *display);
> void intel_dpll_update_ref_clks(struct intel_display *display);
> void intel_dpll_readout_hw_state(struct intel_display *display);
> void intel_dpll_sanitize_state(struct intel_display *display);
> @@ -435,8 +435,8 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
> enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
> bool intel_dpll_is_combophy(enum intel_dpll_id id);
>
> -void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> -void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);
> +void intel_dpll_state_verify(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> +void intel_dpll_verify_disabled(struct intel_atomic_state *state);
>
> #endif /* _INTEL_DPLL_MGR_H_ */
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index ec8f38fba178..f07c7ef56148 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -249,7 +249,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
>
> if (HAS_PCH_SPLIT(display)) {
> assert_fdi_rx_pll_disabled(display, pipe);
> - assert_shared_dpll_disabled(display, crtc_state->intel_dpll);
> + assert_dpll_disabled(display, crtc_state->intel_dpll);
> } else {
> assert_pll_disabled(display, pipe);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 46e0002a1358..ed4f305e0d3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -93,9 +93,9 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
> crtc->base.enabled = false;
>
> if (crtc_state->intel_dpll)
> - intel_unreference_shared_dpll_crtc(crtc,
> - crtc_state->intel_dpll,
> - &crtc_state->intel_dpll->state);
> + intel_unreference_dpll_crtc(crtc,
> + crtc_state->intel_dpll,
> + &crtc_state->intel_dpll->state);
> }
>
> static void set_encoder_for_connector(struct intel_connector *connector,
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index 766a9983665a..f2f6b9d9afa1 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -243,7 +243,7 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
> intel_wm_state_verify(state, crtc);
> verify_connector_state(state, crtc);
> verify_crtc_state(state, crtc);
> - intel_shared_dpll_state_verify(state, crtc);
> + intel_dpll_state_verify(state, crtc);
> intel_mpllb_state_verify(state, crtc);
> intel_cx0pll_state_verify(state, crtc);
> }
> @@ -252,5 +252,5 @@ void intel_modeset_verify_disabled(struct intel_atomic_state *state)
> {
> verify_encoder_state(state);
> verify_connector_state(state, NULL);
> - intel_shared_dpll_verify_disabled(state);
> + intel_dpll_verify_disabled(state);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index b38305c16e77..b59b3c94f711 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -251,7 +251,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> u32 val, pipeconf_val;
>
> /* Make sure PCH DPLL is enabled */
> - assert_shared_dpll_enabled(display, crtc_state->intel_dpll);
> + assert_dpll_enabled(display, crtc_state->intel_dpll);
>
> /* FDI must be feeding us bits for PCH ports */
> assert_fdi_tx_enabled(display, pipe);
> @@ -382,7 +382,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> temp |= TRANS_DPLL_ENABLE(pipe);
> sel = TRANS_DPLLB_SEL(pipe);
> if (crtc_state->intel_dpll ==
> - intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
> + intel_get_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
> temp |= sel;
> else
> temp &= ~sel;
> @@ -394,11 +394,11 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> * transcoder, and we actually should do this to not upset any PCH
> * transcoder that already use the clock when we share it.
> *
> - * Note that enable_shared_dpll tries to do the right thing, but
> - * get_shared_dpll unconditionally resets the pll - we need that
> + * Note that enable_dpll tries to do the right thing, but
> + * get_dpll unconditionally resets the pll - we need that
> * to have the right LVDS enable sequence.
> */
> - intel_enable_shared_dpll(crtc_state);
> + intel_enable_dpll(crtc_state);
>
> /* set transcoder timing, panel must allow it */
> assert_pps_unlocked(display, pipe);
> @@ -472,7 +472,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state,
>
> ilk_fdi_pll_disable(crtc);
>
> - intel_disable_shared_dpll(old_crtc_state);
> + intel_disable_dpll(old_crtc_state);
> }
>
> static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
> @@ -528,7 +528,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
> pll_id = DPLL_ID_PCH_PLL_A;
> }
>
> - crtc_state->intel_dpll = intel_get_shared_dpll_by_id(display, pll_id);
> + crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id);
> pll = crtc_state->intel_dpll;
>
> pll_active = intel_dpll_get_hw_state(display, pll,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH 07/18] drm/i915/dpll: Move away from using shared dpll
2025-05-09 10:17 ` Jani Nikula
@ 2025-05-12 4:02 ` Kandpal, Suraj
0 siblings, 0 replies; 42+ messages in thread
From: Kandpal, Suraj @ 2025-05-12 4:02 UTC (permalink / raw)
To: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Murthy, Arun R
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, May 9, 2025 3:47 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 07/18] drm/i915/dpll: Move away from using shared dpll
>
> On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Rename functions to move away from using shared dpll in the dpll
> > framework as much as possible since dpll may not always be shared.
>
> I think you're replacing some "shared dpll" with "global dpll" in comments,
> which should just drop shared and not mention global. Comments inline.
>
Sure will fix them
Regards,
Suraj Kandpal
> With them fixed,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
> >
> > --v2
> > -Use intel_dpll_global instead of global_dpll [Jani]
> >
> > --v3
> > -Just use intel_dpll [Jani]
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > .../drm/i915/display/intel_display_driver.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_dpll.c | 10 +-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 235
> > +++++++++--------- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 52 ++--
> > drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> > .../drm/i915/display/intel_modeset_setup.c | 6 +-
> > .../drm/i915/display/intel_modeset_verify.c | 4 +-
> > .../gpu/drm/i915/display/intel_pch_display.c | 14 +-
> > 10 files changed, 173 insertions(+), 174 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4d631cbc81d2..11ebcb40c91f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1569,7 +1569,7 @@ _icl_ddi_get_pll(struct intel_display *display,
> > i915_reg_t reg,
> >
> > id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_by_id(display, id);
> > }
> >
> > static void adls_ddi_enable_clock(struct intel_encoder *encoder, @@
> > -1723,7 +1723,7 @@ static struct intel_dpll *dg1_ddi_get_pll(struct
> intel_encoder *encoder)
> > if (phy >= PHY_C)
> > id += DPLL_ID_DG1_DPLL2;
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_by_id(display, id);
> > }
> >
> > static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
> > @@ -1895,7 +1895,7 @@ static struct intel_dpll *icl_ddi_tc_get_pll(struct
> intel_encoder *encoder)
> > return NULL;
> > }
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_by_id(display, id);
> > }
> >
> > static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder
> > *encoder) @@ -1918,7 +1918,7 @@ static struct intel_dpll
> *bxt_ddi_get_pll(struct intel_encoder *encoder)
> > return NULL;
> > }
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_by_id(display, id);
> > }
> >
> > static void skl_ddi_enable_clock(struct intel_encoder *encoder, @@
> > -1986,7 +1986,7 @@ static struct intel_dpll *skl_ddi_get_pll(struct
> intel_encoder *encoder)
> > id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
> > DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_by_id(display, id);
> > }
> >
> > void hsw_ddi_enable_clock(struct intel_encoder *encoder, @@ -2053,7
> > +2053,7 @@ static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder
> *encoder)
> > return NULL;
> > }
> >
> > - return intel_get_shared_dpll_by_id(display, id);
> > + return intel_get_dpll_by_id(display, id);
> > }
> >
> > void intel_ddi_enable_clock(struct intel_encoder *encoder, @@ -2760,7
> > +2760,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state
> *state,
> > * 4. Enable the port PLL.
> > *
> > * The PLL enabling itself was already done before this function by
> > - * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
> > + * hsw_crtc_enable()->intel_enable_dpll(). We need only
> > * configure the PLL to port mapping here.
> > */
> > intel_ddi_enable_clock(encoder, crtc_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index b765d5765b32..ce5c9e74475d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1664,7 +1664,7 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > if (new_crtc_state->intel_dpll)
> > - intel_enable_shared_dpll(new_crtc_state);
> > + intel_enable_dpll(new_crtc_state);
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > @@ -1793,7 +1793,7 @@ static void hsw_crtc_disable(struct
> intel_atomic_state *state,
> > intel_encoders_disable(state, crtc);
> > intel_encoders_post_disable(state, crtc);
> >
> > - intel_disable_shared_dpll(old_crtc_state);
> > + intel_disable_dpll(old_crtc_state);
> >
> > intel_encoders_post_pll_disable(state, crtc);
> >
> > @@ -6434,7 +6434,7 @@ int intel_atomic_check(struct drm_device *dev,
> >
> > any_ms = true;
> >
> > - intel_release_shared_dplls(state, crtc);
> > + intel_release_dplls(state, crtc);
> > }
> >
> > if (any_ms && !check_digital_port_conflicts(state)) { @@ -7531,7
> > +7531,7 @@ static int intel_atomic_swap_state(struct
> > intel_atomic_state *state)
> >
> > intel_atomic_swap_global_state(state);
> >
> > - intel_shared_dpll_swap_state(state);
> > + intel_dpll_swap_state(state);
> >
> > intel_atomic_track_fbs(state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > index 5c74ab5fd1aa..16d91be02bb9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > @@ -446,7 +446,7 @@ int intel_display_driver_probe_nogem(struct
> intel_display *display)
> > }
> >
> > intel_plane_possible_crtcs_init(display);
> > - intel_shared_dpll_init(display);
> > + intel_dpll_init(display);
> > intel_fdi_pll_freq_update(display);
> >
> > intel_update_czclk(display);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> > b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index 4d1f7fccd28a..db67e92505d2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -1161,7 +1161,7 @@ static int hsw_crtc_compute_clock(struct
> intel_atomic_state *state,
> > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > return 0;
> >
> > - ret = intel_compute_shared_dplls(state, crtc, encoder);
> > + ret = intel_compute_dplls(state, crtc, encoder);
> > if (ret)
> > return ret;
> >
> > @@ -1189,7 +1189,7 @@ static int hsw_crtc_get_shared_dpll(struct
> intel_atomic_state *state,
> > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > return 0;
> >
> > - return intel_reserve_shared_dplls(state, crtc, encoder);
> > + return intel_reserve_dplls(state, crtc, encoder);
> > }
> >
> > static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> > @@ -1223,7 +1223,7 @@ static int mtl_crtc_compute_clock(struct
> intel_atomic_state *state,
> > if (ret)
> > return ret;
> >
> > - /* TODO: Do the readback via intel_compute_shared_dplls() */
> > + /* TODO: Do the readback via intel_compute_dplls() */
> > crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> > &crtc_state->dpll_hw_state.cx0pll);
> >
> > crtc_state->hw.adjusted_mode.crtc_clock =
> > intel_crtc_dotclock(crtc_state); @@ -1394,7 +1394,7 @@ static int
> ilk_crtc_compute_clock(struct intel_atomic_state *state,
> > ilk_compute_dpll(crtc_state, &crtc_state->dpll,
> > &crtc_state->dpll);
> >
> > - ret = intel_compute_shared_dplls(state, crtc, NULL);
> > + ret = intel_compute_dplls(state, crtc, NULL);
> > if (ret)
> > return ret;
> >
> > @@ -1414,7 +1414,7 @@ static int ilk_crtc_get_shared_dpll(struct
> intel_atomic_state *state,
> > if (!crtc_state->has_pch_encoder)
> > return 0;
> >
> > - return intel_reserve_shared_dplls(state, crtc, NULL);
> > + return intel_reserve_dplls(state, crtc, NULL);
> > }
> >
> > static u32 vlv_dpll(const struct intel_crtc_state *crtc_state) diff
> > --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index e63568be3150..f1b704f369f9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -52,21 +52,21 @@
> > * share a PLL if their configurations match.
> > *
> > * This file provides an abstraction over display PLLs. The function
> > - * intel_shared_dpll_init() initializes the PLLs for the given
> > platform. The
> > + * intel_dpll_init() initializes the PLLs for the given platform.
> > + The
> > * users of a PLL are tracked and that tracking is integrated with the atomic
> > * modset interface. During an atomic operation, required PLLs can be
> reserved
> > * for a given CRTC and encoder configuration by calling
> > - * intel_reserve_shared_dplls() and previously reserved PLLs can be
> > released
> > - * with intel_release_shared_dplls().
> > + * intel_reserve_dplls() and previously reserved PLLs can be released
> > + * with intel_release_dplls().
> > * Changes to the users are first staged in the atomic state, and
> > then made
> > - * effective by calling intel_shared_dpll_swap_state() during the
> > atomic
> > + * effective by calling intel_dpll_swap_state() during the atomic
> > * commit phase.
> > */
> >
> > /* platform specific hooks for managing DPLLs */ struct
> > intel_dpll_funcs {
> > /*
> > - * Hook for enabling the pll, called from intel_enable_shared_dpll() if
> > + * Hook for enabling the pll, called from intel_enable_dpll() if
> > * the pll is not already enabled.
> > */
> > void (*enable)(struct intel_display *display, @@ -74,7 +74,7 @@
> > struct intel_dpll_funcs {
> > const struct intel_dpll_hw_state *dpll_hw_state);
> >
> > /*
> > - * Hook for disabling the pll, called from intel_disable_shared_dpll()
> > + * Hook for disabling the pll, called from intel_disable_dpll()
> > * only when it is safe to disable the pll, i.e., there are no more
> > * tracked users for it.
> > */
> > @@ -133,7 +133,7 @@ intel_atomic_duplicate_dpll_state(struct
> > intel_display *display, }
> >
> > static struct intel_dpll_state *
> > -intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> > +intel_atomic_get_dpll_state(struct drm_atomic_state *s)
> > {
> > struct intel_atomic_state *state = to_intel_atomic_state(s);
> > struct intel_display *display = to_intel_display(state); @@ -151,7
> > +151,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state
> > *s) }
> >
> > /**
> > - * intel_get_shared_dpll_by_id - get a DPLL given its id
> > + * intel_get_dpll_by_id - get a DPLL given its id
> > * @display: intel_display device instance
> > * @id: pll id
> > *
> > @@ -159,8 +159,8 @@ intel_atomic_get_shared_dpll_state(struct
> drm_atomic_state *s)
> > * A pointer to the DPLL with @id
> > */
> > struct intel_dpll *
> > -intel_get_shared_dpll_by_id(struct intel_display *display,
> > - enum intel_dpll_id id)
> > +intel_get_dpll_by_id(struct intel_display *display,
> > + enum intel_dpll_id id)
> > {
> > struct intel_dpll *pll;
> > int i;
> > @@ -175,9 +175,9 @@ intel_get_shared_dpll_by_id(struct intel_display
> > *display, }
> >
> > /* For ILK+ */
> > -void assert_shared_dpll(struct intel_display *display,
> > - struct intel_dpll *pll,
> > - bool state)
> > +void assert_dpll(struct intel_display *display,
> > + struct intel_dpll *pll,
> > + bool state)
> > {
> > bool cur_state;
> > struct intel_dpll_hw_state hw_state; @@ -250,12 +250,12 @@ static
> > void _intel_disable_shared_dpll(struct intel_display *display, }
> >
> > /**
> > - * intel_enable_shared_dpll - enable a CRTC's shared DPLL
> > - * @crtc_state: CRTC, and its state, which has a shared DPLL
> > + * intel_enable_dpll - enable a CRTC's global DPLL
>
> Global?
>
> Isn't what we have in intel_dpll.c now called "global", and this is not it?
>
>
> > + * @crtc_state: CRTC, and its state, which has a DPLL
> > *
> > - * Enable the shared DPLL used by @crtc.
> > + * Enable DPLL used by @crtc.
> > */
> > -void intel_enable_shared_dpll(const struct intel_crtc_state
> > *crtc_state)
> > +void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -282,7 +282,7 @@ void intel_enable_shared_dpll(const struct
> > intel_crtc_state *crtc_state)
> >
> > if (old_mask) {
> > drm_WARN_ON(display->drm, !pll->on);
> > - assert_shared_dpll_enabled(display, pll);
> > + assert_dpll_enabled(display, pll);
> > goto out;
> > }
> > drm_WARN_ON(display->drm, pll->on);
> > @@ -296,12 +296,12 @@ void intel_enable_shared_dpll(const struct
> > intel_crtc_state *crtc_state) }
> >
> > /**
> > - * intel_disable_shared_dpll - disable a CRTC's shared DPLL
> > + * intel_disable_dpll - disable a CRTC's shared DPLL
> > * @crtc_state: CRTC, and its state, which has a shared DPLL
> > *
> > - * Disable the shared DPLL used by @crtc.
> > + * Disable DPLL used by @crtc.
> > */
> > -void intel_disable_shared_dpll(const struct intel_crtc_state
> > *crtc_state)
> > +void intel_disable_dpll(const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -326,7 +326,7 @@ void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> > pll->info->name, pll->active_mask, pll->on,
> > crtc->base.base.id, crtc->base.name);
> >
> > - assert_shared_dpll_enabled(display, pll);
> > + assert_dpll_enabled(display, pll);
> > drm_WARN_ON(display->drm, !pll->on);
> >
> > pll->active_mask &= ~pipe_mask;
> > @@ -358,10 +358,10 @@ intel_dpll_mask_all(struct intel_display
> > *display) }
> >
> > static struct intel_dpll *
> > -intel_find_shared_dpll(struct intel_atomic_state *state,
> > - const struct intel_crtc *crtc,
> > - const struct intel_dpll_hw_state *dpll_hw_state,
> > - unsigned long dpll_mask)
> > +intel_find_dpll(struct intel_atomic_state *state,
> > + const struct intel_crtc *crtc,
> > + const struct intel_dpll_hw_state *dpll_hw_state,
> > + unsigned long dpll_mask)
> > {
> > struct intel_display *display = to_intel_display(crtc);
> > unsigned long dpll_mask_all = intel_dpll_mask_all(display); @@
> > -369,14 +369,14 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
> > struct intel_dpll *unused_pll = NULL;
> > enum intel_dpll_id id;
> >
> > - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> > + dpll_state = intel_atomic_get_dpll_state(&state->base);
> >
> > drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
> >
> > for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
> > struct intel_dpll *pll;
> >
> > - pll = intel_get_shared_dpll_by_id(display, id);
> > + pll = intel_get_dpll_by_id(display, id);
> > if (!pll)
> > continue;
> >
> > @@ -412,7 +412,7 @@ intel_find_shared_dpll(struct intel_atomic_state
> > *state, }
> >
> > /**
> > - * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
> > + * intel_reference_dpll_crtc - Get a DPLL reference for a CRTC
> > * @crtc: CRTC on which behalf the reference is taken
> > * @pll: DPLL for which the reference is taken
> > * @dpll_state: the DPLL atomic state in which the reference is
> > tracked @@ -420,9 +420,9 @@ intel_find_shared_dpll(struct
> intel_atomic_state *state,
> > * Take a reference for @pll tracking the use of it by @crtc.
> > */
> > static void
> > -intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > - const struct intel_dpll *pll,
> > - struct intel_dpll_state *dpll_state)
> > +intel_reference_dpll_crtc(const struct intel_crtc *crtc,
> > + const struct intel_dpll *pll,
> > + struct intel_dpll_state *dpll_state)
> > {
> > struct intel_display *display = to_intel_display(crtc);
> >
> > @@ -435,23 +435,23 @@ intel_reference_shared_dpll_crtc(const struct
> > intel_crtc *crtc, }
> >
> > static void
> > -intel_reference_shared_dpll(struct intel_atomic_state *state,
> > - const struct intel_crtc *crtc,
> > - const struct intel_dpll *pll,
> > - const struct intel_dpll_hw_state *dpll_hw_state)
> > +intel_reference_dpll(struct intel_atomic_state *state,
> > + const struct intel_crtc *crtc,
> > + const struct intel_dpll *pll,
> > + const struct intel_dpll_hw_state *dpll_hw_state)
> > {
> > struct intel_dpll_state *dpll_state;
> >
> > - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> > + dpll_state = intel_atomic_get_dpll_state(&state->base);
> >
> > if (dpll_state[pll->index].pipe_mask == 0)
> > dpll_state[pll->index].hw_state = *dpll_hw_state;
> >
> > - intel_reference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> > + intel_reference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> > }
> >
> > /**
> > - * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a
> > CRTC
> > + * intel_unreference_dpll_crtc - Drop a DPLL reference for a CRTC
> > * @crtc: CRTC on which behalf the reference is dropped
> > * @pll: DPLL for which the reference is dropped
> > * @dpll_state: the DPLL atomic state in which the reference is
> > tracked @@ -459,9 +459,9 @@ intel_reference_shared_dpll(struct
> intel_atomic_state *state,
> > * Drop a reference for @pll tracking the end of use of it by @crtc.
> > */
> > void
> > -intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > - const struct intel_dpll *pll,
> > - struct intel_dpll_state *dpll_state)
> > +intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
> > + const struct intel_dpll *pll,
> > + struct intel_dpll_state *dpll_state)
> > {
> > struct intel_display *display = to_intel_display(crtc);
> >
> > @@ -473,15 +473,15 @@ intel_unreference_shared_dpll_crtc(const struct
> intel_crtc *crtc,
> > crtc->base.base.id, crtc->base.name, pll->info->name); }
> >
> > -static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> > - const struct intel_crtc *crtc,
> > - const struct intel_dpll *pll)
> > +static void intel_unreference_dpll(struct intel_atomic_state *state,
> > + const struct intel_crtc *crtc,
> > + const struct intel_dpll *pll)
> > {
> > struct intel_dpll_state *dpll_state;
> >
> > - dpll_state = intel_atomic_get_shared_dpll_state(&state->base);
> > + dpll_state = intel_atomic_get_dpll_state(&state->base);
> >
> > - intel_unreference_shared_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> > + intel_unreference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> > }
> >
> > static void intel_put_dpll(struct intel_atomic_state *state, @@
> > -497,11 +497,11 @@ static void intel_put_dpll(struct intel_atomic_state
> *state,
> > if (!old_crtc_state->intel_dpll)
> > return;
> >
> > - intel_unreference_shared_dpll(state, crtc, old_crtc_state->intel_dpll);
> > + intel_unreference_dpll(state, crtc, old_crtc_state->intel_dpll);
> > }
> >
> > /**
> > - * intel_shared_dpll_swap_state - make atomic DPLL configuration
> > effective
> > + * intel_dpll_swap_state - make atomic DPLL configuration effective
> > * @state: atomic state
> > *
> > * This is the dpll version of drm_atomic_helper_swap_state() since
> > the @@ -511,7 +511,7 @@ static void intel_put_dpll(struct
> intel_atomic_state *state,
> > * i.e. it also puts the current state into @state, even though there is no
> > * need for that at this moment.
> > */
> > -void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> > +void intel_dpll_swap_state(struct intel_atomic_state *state)
> > {
> > struct intel_display *display = to_intel_display(state);
> > struct intel_dpll_state *dpll_state = state->dpll_state; @@ -620,25
> > +620,25 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
> > if (HAS_PCH_IBX(display)) {
> > /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
> > id = (enum intel_dpll_id) crtc->pipe;
> > - pll = intel_get_shared_dpll_by_id(display, id);
> > + pll = intel_get_dpll_by_id(display, id);
> >
> > drm_dbg_kms(display->drm,
> > "[CRTC:%d:%s] using pre-allocated %s\n",
> > crtc->base.base.id, crtc->base.name,
> > pll->info->name);
> > } else {
> > - pll = intel_find_shared_dpll(state, crtc,
> > - &crtc_state->dpll_hw_state,
> > - BIT(DPLL_ID_PCH_PLL_B) |
> > - BIT(DPLL_ID_PCH_PLL_A));
> > + pll = intel_find_dpll(state, crtc,
> > + &crtc_state->dpll_hw_state,
> > + BIT(DPLL_ID_PCH_PLL_B) |
> > + BIT(DPLL_ID_PCH_PLL_A));
> > }
> >
> > if (!pll)
> > return -EINVAL;
> >
> > /* reference the pll */
> > - intel_reference_shared_dpll(state, crtc,
> > - pll, &crtc_state->dpll_hw_state);
> > + intel_reference_dpll(state, crtc,
> > + pll, &crtc_state->dpll_hw_state);
> >
> > crtc_state->intel_dpll = pll;
> >
> > @@ -1066,7 +1066,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state
> *state,
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> >
> > - return intel_find_shared_dpll(state, crtc,
> > + return intel_find_dpll(state, crtc,
> > &crtc_state->dpll_hw_state,
> > BIT(DPLL_ID_WRPLL2) |
> > BIT(DPLL_ID_WRPLL1));
> > @@ -1113,7 +1113,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state
> *crtc_state)
> > return NULL;
> > }
> >
> > - pll = intel_get_shared_dpll_by_id(display, pll_id);
> > + pll = intel_get_dpll_by_id(display, pll_id);
> >
> > if (!pll)
> > return NULL;
> > @@ -1169,7 +1169,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state
> *state,
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> >
> > - return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
> > + return intel_find_dpll(state, crtc, &crtc_state->dpll_hw_state,
> > BIT(DPLL_ID_SPLL));
> > }
> >
> > @@ -1233,8 +1233,8 @@ static int hsw_get_dpll(struct intel_atomic_state
> *state,
> > if (!pll)
> > return -EINVAL;
> >
> > - intel_reference_shared_dpll(state, crtc,
> > - pll, &crtc_state->dpll_hw_state);
> > + intel_reference_dpll(state, crtc,
> > + pll, &crtc_state->dpll_hw_state);
> >
> > crtc_state->intel_dpll = pll;
> >
> > @@ -1942,20 +1942,20 @@ static int skl_get_dpll(struct intel_atomic_state
> *state,
> > struct intel_dpll *pll;
> >
> > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> > - pll = intel_find_shared_dpll(state, crtc,
> > - &crtc_state->dpll_hw_state,
> > - BIT(DPLL_ID_SKL_DPLL0));
> > + pll = intel_find_dpll(state, crtc,
> > + &crtc_state->dpll_hw_state,
> > + BIT(DPLL_ID_SKL_DPLL0));
> > else
> > - pll = intel_find_shared_dpll(state, crtc,
> > - &crtc_state->dpll_hw_state,
> > - BIT(DPLL_ID_SKL_DPLL3) |
> > - BIT(DPLL_ID_SKL_DPLL2) |
> > - BIT(DPLL_ID_SKL_DPLL1));
> > + pll = intel_find_dpll(state, crtc,
> > + &crtc_state->dpll_hw_state,
> > + BIT(DPLL_ID_SKL_DPLL3) |
> > + BIT(DPLL_ID_SKL_DPLL2) |
> > + BIT(DPLL_ID_SKL_DPLL1));
> > if (!pll)
> > return -EINVAL;
> >
> > - intel_reference_shared_dpll(state, crtc,
> > - pll, &crtc_state->dpll_hw_state);
> > + intel_reference_dpll(state, crtc,
> > + pll, &crtc_state->dpll_hw_state);
> >
> > crtc_state->intel_dpll = pll;
> >
> > @@ -2434,13 +2434,13 @@ static int bxt_get_dpll(struct
> > intel_atomic_state *state,
> >
> > /* 1:1 mapping between ports and PLLs */
> > id = (enum intel_dpll_id) encoder->port;
> > - pll = intel_get_shared_dpll_by_id(display, id);
> > + pll = intel_get_dpll_by_id(display, id);
> >
> > drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
> > crtc->base.base.id, crtc->base.name, pll->info->name);
> >
> > - intel_reference_shared_dpll(state, crtc,
> > - pll, &crtc_state->dpll_hw_state);
> > + intel_reference_dpll(state, crtc,
> > + pll, &crtc_state->dpll_hw_state);
> >
> > crtc_state->intel_dpll = pll;
> >
> > @@ -3388,14 +3388,14 @@ static int icl_get_combo_phy_dpll(struct
> intel_atomic_state *state,
> > /* Eliminate DPLLs from consideration if reserved by HTI */
> > dpll_mask &= ~intel_hti_dpll_mask(display);
> >
> > - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> > - &port_dpll->hw_state,
> > - dpll_mask);
> > + port_dpll->pll = intel_find_dpll(state, crtc,
> > + &port_dpll->hw_state,
> > + dpll_mask);
> > if (!port_dpll->pll)
> > return -EINVAL;
> >
> > - intel_reference_shared_dpll(state, crtc,
> > - port_dpll->pll, &port_dpll->hw_state);
> > + intel_reference_dpll(state, crtc,
> > + port_dpll->pll, &port_dpll->hw_state);
> >
> > icl_update_active_dpll(state, crtc, encoder);
> >
> > @@ -3452,26 +3452,25 @@ static int icl_get_tc_phy_dplls(struct
> intel_atomic_state *state,
> > int ret;
> >
> > port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> > - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> > - &port_dpll->hw_state,
> > - BIT(DPLL_ID_ICL_TBTPLL));
> > + port_dpll->pll = intel_find_dpll(state, crtc,
> > + &port_dpll->hw_state,
> > + BIT(DPLL_ID_ICL_TBTPLL));
> > if (!port_dpll->pll)
> > return -EINVAL;
> > - intel_reference_shared_dpll(state, crtc,
> > - port_dpll->pll, &port_dpll->hw_state);
> > -
> > + intel_reference_dpll(state, crtc,
> > + port_dpll->pll, &port_dpll->hw_state);
> >
> > port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> > dpll_id = icl_tc_port_to_pll_id(intel_encoder_to_tc(encoder));
> > - port_dpll->pll = intel_find_shared_dpll(state, crtc,
> > - &port_dpll->hw_state,
> > - BIT(dpll_id));
> > + port_dpll->pll = intel_find_dpll(state, crtc,
> > + &port_dpll->hw_state,
> > + BIT(dpll_id));
> > if (!port_dpll->pll) {
> > ret = -EINVAL;
> > goto err_unreference_tbt_pll;
> > }
> > - intel_reference_shared_dpll(state, crtc,
> > - port_dpll->pll, &port_dpll->hw_state);
> > + intel_reference_dpll(state, crtc,
> > + port_dpll->pll, &port_dpll->hw_state);
> >
> > icl_update_active_dpll(state, crtc, encoder);
> >
> > @@ -3479,7 +3478,7 @@ static int icl_get_tc_phy_dplls(struct
> > intel_atomic_state *state,
> >
> > err_unreference_tbt_pll:
> > port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> > - intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
> > + intel_unreference_dpll(state, crtc, port_dpll->pll);
> >
> > return ret;
> > }
> > @@ -3534,7 +3533,7 @@ static void icl_put_dplls(struct intel_atomic_state
> *state,
> > if (!old_port_dpll->pll)
> > continue;
> >
> > - intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
> > + intel_unreference_dpll(state, crtc, old_port_dpll->pll);
> > }
> > }
> >
> > @@ -4300,12 +4299,12 @@ static const struct intel_dpll_mgr
> > adlp_pll_mgr = { };
> >
> > /**
> > - * intel_shared_dpll_init - Initialize shared DPLLs
> > + * intel_dpll_init - Initialize DPLLs
> > * @display: intel_display device
> > *
> > - * Initialize shared DPLLs for @display.
> > + * Initialize DPLLs for @display.
> > */
> > -void intel_shared_dpll_init(struct intel_display *display)
> > +void intel_dpll_init(struct intel_display *display)
> > {
> > const struct intel_dpll_mgr *dpll_mgr = NULL;
> > const struct dpll_info *dpll_info;
> > @@ -4362,7 +4361,7 @@ void intel_shared_dpll_init(struct intel_display
> > *display) }
> >
> > /**
> > - * intel_compute_shared_dplls - compute DPLL state CRTC and encoder
> > combination
> > + * intel_compute_dplls - compute DPLL state CRTC and encoder
> > + combination
> > * @state: atomic state
> > * @crtc: CRTC to compute DPLLs for
> > * @encoder: encoder
> > @@ -4370,14 +4369,14 @@ void intel_shared_dpll_init(struct intel_display
> *display)
> > * This function computes the DPLL state for the given CRTC and encoder.
> > *
> > * The new configuration in the atomic commit @state is made
> > effective by
> > - * calling intel_shared_dpll_swap_state().
> > + * calling intel_dpll_swap_state().
> > *
> > * Returns:
> > * 0 on success, negative error code on failure.
> > */
> > -int intel_compute_shared_dplls(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc,
> > - struct intel_encoder *encoder)
> > +int intel_compute_dplls(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc,
> > + struct intel_encoder *encoder)
> > {
> > struct intel_display *display = to_intel_display(state);
> > const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; @@
> > -4389,7 +4388,7 @@ int intel_compute_shared_dplls(struct
> > intel_atomic_state *state, }
> >
> > /**
> > - * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder
> > combination
> > + * intel_reserve_dplls - reserve DPLLs for CRTC and encoder
> > + combination
> > * @state: atomic state
> > * @crtc: CRTC to reserve DPLLs for
> > * @encoder: encoder
> > @@ -4399,18 +4398,18 @@ int intel_compute_shared_dplls(struct
> intel_atomic_state *state,
> > * state.
> > *
> > * The new configuration in the atomic commit @state is made
> > effective by
> > - * calling intel_shared_dpll_swap_state().
> > + * calling intel_dpll_swap_state().
> > *
> > * The reserved DPLLs should be released by calling
> > - * intel_release_shared_dplls().
> > + * intel_release_dplls().
> > *
> > * Returns:
> > * 0 if all required DPLLs were successfully reserved,
> > * negative error code otherwise.
> > */
> > -int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc,
> > - struct intel_encoder *encoder)
> > +int intel_reserve_dplls(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc,
> > + struct intel_encoder *encoder)
> > {
> > struct intel_display *display = to_intel_display(state);
> > const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; @@
> > -4422,18 +4421,18 @@ int intel_reserve_shared_dplls(struct
> > intel_atomic_state *state, }
> >
> > /**
> > - * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic
> > state
> > + * intel_release_dplls - end use of DPLLs by CRTC in atomic state
> > * @state: atomic state
> > * @crtc: crtc from which the DPLLs are to be released
> > *
> > - * This function releases all DPLLs reserved by
> > intel_reserve_shared_dplls()
> > + * This function releases all DPLLs reserved by intel_reserve_dplls()
> > * from the current atomic commit @state and the old @crtc atomic state.
> > *
> > * The new configuration in the atomic commit @state is made
> > effective by
> > - * calling intel_shared_dpll_swap_state().
> > + * calling intel_dpll_swap_state().
> > */
> > -void intel_release_shared_dplls(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc)
> > +void intel_release_dplls(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc)
> > {
> > struct intel_display *display = to_intel_display(state);
> > const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; @@
> > -4441,7 +4440,7 @@ void intel_release_shared_dplls(struct
> intel_atomic_state *state,
> > /*
> > * FIXME: this function is called for every platform having a
> > * compute_clock hook, even though the platform doesn't yet support
> > - * the shared DPLL framework and intel_reserve_shared_dplls() is not
> > + * the global DPLL framework and intel_reserve_dplls() is not
>
> Global?
>
> > * called on those.
> > */
> > if (!dpll_mgr)
> > @@ -4457,7 +4456,7 @@ void intel_release_shared_dplls(struct
> intel_atomic_state *state,
> > * @encoder: encoder determining the type of port DPLL
> > *
> > * Update the active DPLL for the given @crtc/@encoder in @crtc's
> > atomic state,
> > - * from the port DPLLs reserved previously by
> > intel_reserve_shared_dplls(). The
> > + * from the port DPLLs reserved previously by intel_reserve_dplls().
> > + The
> > * DPLL selected will be based on the current mode of the encoder's port.
> > */
> > void intel_update_active_dpll(struct intel_atomic_state *state, @@
> > -4522,7 +4521,7 @@ static void readout_dpll_hw_state(struct intel_display
> *display,
> > to_intel_crtc_state(crtc->base.state);
> >
> > if (crtc_state->hw.active && crtc_state->intel_dpll == pll)
> > - intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
> > + intel_reference_dpll_crtc(crtc, pll, &pll->state);
> > }
> > pll->active_mask = pll->state.pipe_mask;
> >
> > @@ -4683,8 +4682,8 @@ static bool has_alt_port_dpll(const struct intel_dpll
> *old_pll,
> > (old_pll->info->is_alt_port_dpll ||
> > new_pll->info->is_alt_port_dpll); }
> >
> > -void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc)
> > +void intel_dpll_state_verify(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc)
> > {
> > struct intel_display *display = to_intel_display(state);
> > const struct intel_crtc_state *old_crtc_state = @@ -4714,7 +4713,7
> > @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> > }
> > }
> >
> > -void intel_shared_dpll_verify_disabled(struct intel_atomic_state
> > *state)
> > +void intel_dpll_verify_disabled(struct intel_atomic_state *state)
> > {
> > struct intel_display *display = to_intel_display(state);
> > struct intel_dpll *pll;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 3604ebbc78b5..99a058deaeda 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -387,26 +387,26 @@ struct intel_dpll { #define SKL_DPLL2 2
> > #define SKL_DPLL3 3
> >
> > -/* shared dpll functions */
> > +/* global dpll functions */
>
> Global?
>
> > struct intel_dpll *
> > -intel_get_shared_dpll_by_id(struct intel_display *display,
> > - enum intel_dpll_id id);
> > -void assert_shared_dpll(struct intel_display *display,
> > - struct intel_dpll *pll,
> > - bool state);
> > -#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p,
> > true) -#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d,
> > p, false) -int intel_compute_shared_dplls(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc,
> > - struct intel_encoder *encoder);
> > -int intel_reserve_shared_dplls(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc,
> > - struct intel_encoder *encoder);
> > -void intel_release_shared_dplls(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc);
> > -void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
> > - const struct intel_dpll *pll,
> > - struct intel_dpll_state
> *shared_dpll_state);
> > +intel_get_dpll_by_id(struct intel_display *display,
> > + enum intel_dpll_id id);
> > +void assert_dpll(struct intel_display *display,
> > + struct intel_dpll *pll,
> > + bool state);
> > +#define assert_dpll_enabled(d, p) assert_dpll(d, p, true) #define
> > +assert_dpll_disabled(d, p) assert_dpll(d, p, false) int
> > +intel_compute_dplls(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc,
> > + struct intel_encoder *encoder);
> > +int intel_reserve_dplls(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc,
> > + struct intel_encoder *encoder);
> > +void intel_release_dplls(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc);
> > +void intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
> > + const struct intel_dpll *pll,
> > + struct intel_dpll_state *shared_dpll_state);
> > void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> > enum icl_port_dpll_id port_dpll_id); void
> > intel_update_active_dpll(struct intel_atomic_state *state, @@ -418,10
> > +418,10 @@ int intel_dpll_get_freq(struct intel_display *display,
> > bool intel_dpll_get_hw_state(struct intel_display *display,
> > struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state); -void
> > intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> > -void intel_disable_shared_dpll(const struct intel_crtc_state
> > *crtc_state); -void intel_shared_dpll_swap_state(struct
> > intel_atomic_state *state); -void intel_shared_dpll_init(struct
> > intel_display *display);
> > +void intel_enable_dpll(const struct intel_crtc_state *crtc_state);
> > +void intel_disable_dpll(const struct intel_crtc_state *crtc_state);
> > +void intel_dpll_swap_state(struct intel_atomic_state *state); void
> > +intel_dpll_init(struct intel_display *display);
> > void intel_dpll_update_ref_clks(struct intel_display *display); void
> > intel_dpll_readout_hw_state(struct intel_display *display); void
> > intel_dpll_sanitize_state(struct intel_display *display); @@ -435,8
> > +435,8 @@ bool intel_dpll_compare_hw_state(struct intel_display
> > *display, enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port
> > tc_port); bool intel_dpll_is_combophy(enum intel_dpll_id id);
> >
> > -void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc);
> > -void intel_shared_dpll_verify_disabled(struct intel_atomic_state
> > *state);
> > +void intel_dpll_state_verify(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc);
> > +void intel_dpll_verify_disabled(struct intel_atomic_state *state);
> >
> > #endif /* _INTEL_DPLL_MGR_H_ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c
> > b/drivers/gpu/drm/i915/display/intel_lvds.c
> > index ec8f38fba178..f07c7ef56148 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> > @@ -249,7 +249,7 @@ static void intel_pre_enable_lvds(struct
> > intel_atomic_state *state,
> >
> > if (HAS_PCH_SPLIT(display)) {
> > assert_fdi_rx_pll_disabled(display, pipe);
> > - assert_shared_dpll_disabled(display, crtc_state->intel_dpll);
> > + assert_dpll_disabled(display, crtc_state->intel_dpll);
> > } else {
> > assert_pll_disabled(display, pipe);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index 46e0002a1358..ed4f305e0d3e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -93,9 +93,9 @@ static void intel_crtc_disable_noatomic_begin(struct
> intel_crtc *crtc,
> > crtc->base.enabled = false;
> >
> > if (crtc_state->intel_dpll)
> > - intel_unreference_shared_dpll_crtc(crtc,
> > - crtc_state->intel_dpll,
> > - &crtc_state->intel_dpll-
> >state);
> > + intel_unreference_dpll_crtc(crtc,
> > + crtc_state->intel_dpll,
> > + &crtc_state->intel_dpll->state);
> > }
> >
> > static void set_encoder_for_connector(struct intel_connector
> > *connector, diff --git
> > a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > index 766a9983665a..f2f6b9d9afa1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > @@ -243,7 +243,7 @@ void intel_modeset_verify_crtc(struct
> intel_atomic_state *state,
> > intel_wm_state_verify(state, crtc);
> > verify_connector_state(state, crtc);
> > verify_crtc_state(state, crtc);
> > - intel_shared_dpll_state_verify(state, crtc);
> > + intel_dpll_state_verify(state, crtc);
> > intel_mpllb_state_verify(state, crtc);
> > intel_cx0pll_state_verify(state, crtc); } @@ -252,5 +252,5 @@ void
> > intel_modeset_verify_disabled(struct intel_atomic_state *state) {
> > verify_encoder_state(state);
> > verify_connector_state(state, NULL);
> > - intel_shared_dpll_verify_disabled(state);
> > + intel_dpll_verify_disabled(state);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > index b38305c16e77..b59b3c94f711 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > @@ -251,7 +251,7 @@ static void ilk_enable_pch_transcoder(const struct
> intel_crtc_state *crtc_state)
> > u32 val, pipeconf_val;
> >
> > /* Make sure PCH DPLL is enabled */
> > - assert_shared_dpll_enabled(display, crtc_state->intel_dpll);
> > + assert_dpll_enabled(display, crtc_state->intel_dpll);
> >
> > /* FDI must be feeding us bits for PCH ports */
> > assert_fdi_tx_enabled(display, pipe); @@ -382,7 +382,7 @@ void
> > ilk_pch_enable(struct intel_atomic_state *state,
> > temp |= TRANS_DPLL_ENABLE(pipe);
> > sel = TRANS_DPLLB_SEL(pipe);
> > if (crtc_state->intel_dpll ==
> > - intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
> > + intel_get_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
> > temp |= sel;
> > else
> > temp &= ~sel;
> > @@ -394,11 +394,11 @@ void ilk_pch_enable(struct intel_atomic_state
> *state,
> > * transcoder, and we actually should do this to not upset any PCH
> > * transcoder that already use the clock when we share it.
> > *
> > - * Note that enable_shared_dpll tries to do the right thing, but
> > - * get_shared_dpll unconditionally resets the pll - we need that
> > + * Note that enable_dpll tries to do the right thing, but
> > + * get_dpll unconditionally resets the pll - we need that
> > * to have the right LVDS enable sequence.
> > */
> > - intel_enable_shared_dpll(crtc_state);
> > + intel_enable_dpll(crtc_state);
> >
> > /* set transcoder timing, panel must allow it */
> > assert_pps_unlocked(display, pipe);
> > @@ -472,7 +472,7 @@ void ilk_pch_post_disable(struct
> > intel_atomic_state *state,
> >
> > ilk_fdi_pll_disable(crtc);
> >
> > - intel_disable_shared_dpll(old_crtc_state);
> > + intel_disable_dpll(old_crtc_state);
> > }
> >
> > static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) @@
> > -528,7 +528,7 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
> > pll_id = DPLL_ID_PCH_PLL_A;
> > }
> >
> > - crtc_state->intel_dpll = intel_get_shared_dpll_by_id(display, pll_id);
> > + crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id);
> > pll = crtc_state->intel_dpll;
> >
> > pll_active = intel_dpll_get_hw_state(display, pll,
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 08/18] drm/i915/dpll: Rename crtc_get_shared_dpll
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (6 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 07/18] drm/i915/dpll: Move away from using shared dpll Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:19 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 09/18] drm/i915/dpll: Change argument for enable hook in intel_dpll_funcs Suraj Kandpal
` (9 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename crtc_get_shared_dpll to take into the individual PLL framework
which came in at DISPLAY_VER >= 14.
--v2
-Change naming to dpll_global to keep consistency with rest of the
naming
--v3
-Just use intel_dpll [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 24 ++++++++++----------
drivers/gpu/drm/i915/display/intel_dpll.h | 4 ++--
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ce5c9e74475d..b091faff6680 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4225,7 +4225,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (intel_crtc_needs_modeset(crtc_state)) {
- ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
+ ret = intel_dpll_crtc_get_dpll(state, crtc);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index db67e92505d2..e25411c4171c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -27,8 +27,8 @@
struct intel_dpll_global_funcs {
int (*crtc_compute_clock)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
- int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
+ int (*crtc_get_dpll)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
};
struct intel_limit {
@@ -1176,8 +1176,8 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
-static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static int hsw_crtc_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
@@ -1404,8 +1404,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
return ret;
}
-static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static int ilk_crtc_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@@ -1700,12 +1700,12 @@ static const struct intel_dpll_global_funcs dg2_dpll_funcs = {
static const struct intel_dpll_global_funcs hsw_dpll_funcs = {
.crtc_compute_clock = hsw_crtc_compute_clock,
- .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
+ .crtc_get_dpll = hsw_crtc_get_dpll,
};
static const struct intel_dpll_global_funcs ilk_dpll_funcs = {
.crtc_compute_clock = ilk_crtc_compute_clock,
- .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
+ .crtc_get_dpll = ilk_crtc_get_dpll,
};
static const struct intel_dpll_global_funcs chv_dpll_funcs = {
@@ -1758,8 +1758,8 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
-int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
@@ -1772,10 +1772,10 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
if (!crtc_state->hw.enable || crtc_state->intel_dpll)
return 0;
- if (!display->funcs.dpll->crtc_get_shared_dpll)
+ if (!display->funcs.dpll->crtc_get_dpll)
return 0;
- ret = display->funcs.dpll->crtc_get_shared_dpll(state, crtc);
+ ret = display->funcs.dpll->crtc_get_dpll(state, crtc);
if (ret) {
drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
crtc->base.base.id, crtc->base.name);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index 280e90a57c87..3444a2dd3166 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -19,8 +19,8 @@ struct intel_dpll_hw_state;
void intel_dpll_init_clock_hook(struct intel_display *display);
int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc);
-int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
+int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 08/18] drm/i915/dpll: Rename crtc_get_shared_dpll
2025-05-09 4:27 ` [PATCH 08/18] drm/i915/dpll: Rename crtc_get_shared_dpll Suraj Kandpal
@ 2025-05-09 10:19 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:19 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename crtc_get_shared_dpll to take into the individual PLL framework
> which came in at DISPLAY_VER >= 14.
>
> --v2
> -Change naming to dpll_global to keep consistency with rest of the
> naming
>
> --v3
> -Just use intel_dpll [Jani]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Having shared dpll stuff also in intel_dpll.c is just confusing...
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 24 ++++++++++----------
> drivers/gpu/drm/i915/display/intel_dpll.h | 4 ++--
> 3 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ce5c9e74475d..b091faff6680 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4225,7 +4225,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> crtc_state->update_wm_post = true;
>
> if (intel_crtc_needs_modeset(crtc_state)) {
> - ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
> + ret = intel_dpll_crtc_get_dpll(state, crtc);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index db67e92505d2..e25411c4171c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -27,8 +27,8 @@
> struct intel_dpll_global_funcs {
> int (*crtc_compute_clock)(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> - int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> + int (*crtc_get_dpll)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> };
>
> struct intel_limit {
> @@ -1176,8 +1176,8 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> return 0;
> }
>
> -static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static int hsw_crtc_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> struct intel_crtc_state *crtc_state =
> @@ -1404,8 +1404,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> return ret;
> }
>
> -static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static int ilk_crtc_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> @@ -1700,12 +1700,12 @@ static const struct intel_dpll_global_funcs dg2_dpll_funcs = {
>
> static const struct intel_dpll_global_funcs hsw_dpll_funcs = {
> .crtc_compute_clock = hsw_crtc_compute_clock,
> - .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
> + .crtc_get_dpll = hsw_crtc_get_dpll,
> };
>
> static const struct intel_dpll_global_funcs ilk_dpll_funcs = {
> .crtc_compute_clock = ilk_crtc_compute_clock,
> - .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
> + .crtc_get_dpll = ilk_crtc_get_dpll,
> };
>
> static const struct intel_dpll_global_funcs chv_dpll_funcs = {
> @@ -1758,8 +1758,8 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> return 0;
> }
>
> -int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> struct intel_crtc_state *crtc_state =
> @@ -1772,10 +1772,10 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> if (!crtc_state->hw.enable || crtc_state->intel_dpll)
> return 0;
>
> - if (!display->funcs.dpll->crtc_get_shared_dpll)
> + if (!display->funcs.dpll->crtc_get_dpll)
> return 0;
>
> - ret = display->funcs.dpll->crtc_get_shared_dpll(state, crtc);
> + ret = display->funcs.dpll->crtc_get_dpll(state, crtc);
> if (ret) {
> drm_dbg_kms(display->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
> crtc->base.base.id, crtc->base.name);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
> index 280e90a57c87..3444a2dd3166 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.h
> @@ -19,8 +19,8 @@ struct intel_dpll_hw_state;
> void intel_dpll_init_clock_hook(struct intel_display *display);
> int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> -int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> +int intel_dpll_crtc_get_dpll(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
> u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
> void i9xx_dpll_get_hw_state(struct intel_crtc *crtc,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 09/18] drm/i915/dpll: Change argument for enable hook in intel_dpll_funcs
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (7 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 08/18] drm/i915/dpll: Rename crtc_get_shared_dpll Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:22 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 10/18] drm/i915/drm: Rename disable hook in intel_dpll_global_func Suraj Kandpal
` (8 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Change the arguments for enable hook in intel_dpll_funcs to only
accept crtc_state. This is because we really don't need those extra
arguments everything can be derived from crtc_state and we need both
intel_encoder and crtc_state for PLL enablement when DISPLAY_VER() >= 14
which requires us to pass this crtc state if we want the future
PLL framework to fit into the existing one and not use the intel_ddi
hooks
--v2
-Rename global_dpll to dpll_global to keep consistency with filename
[Jani/Ville]
--v3
-Just use intel_dpll [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 100 ++++++++++--------
1 file changed, 54 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f1b704f369f9..21080abc6d42 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -69,9 +69,8 @@ struct intel_dpll_funcs {
* Hook for enabling the pll, called from intel_enable_dpll() if
* the pll is not already enabled.
*/
- void (*enable)(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state);
+ void (*enable)(const struct intel_crtc_state *state,
+ struct intel_encoder *encoder);
/*
* Hook for disabling the pll, called from intel_disable_dpll()
@@ -229,13 +228,15 @@ intel_tc_pll_enable_reg(struct intel_display *display,
return MG_PLL_ENABLE(tc_port);
}
-static void _intel_enable_shared_dpll(struct intel_display *display,
- struct intel_dpll *pll)
+static void _intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+
if (pll->info->power_domain)
pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
- pll->info->funcs->enable(display, pll, &pll->state.hw_state);
+ pll->info->funcs->enable(crtc_state, NULL);
pll->on = true;
}
@@ -289,7 +290,7 @@ void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
- _intel_enable_shared_dpll(display, pll);
+ _intel_enable_shared_dpll(crtc_state);
out:
mutex_unlock(&display->dpll.lock);
@@ -561,11 +562,12 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
"PCH refclk assertion failure, should be active but is disabled\n");
}
-static void ibx_pch_dpll_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void ibx_pch_dpll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+ const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
const enum intel_dpll_id id = pll->info->id;
/* PCH refclock must be enabled first */
@@ -691,11 +693,12 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
.compare_hw_state = ibx_compare_hw_state,
};
-static void hsw_ddi_wrpll_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void hsw_ddi_wrpll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
const enum intel_dpll_id id = pll->info->id;
intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);
@@ -703,11 +706,11 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display,
udelay(20);
}
-static void hsw_ddi_spll_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void hsw_ddi_spll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
intel_de_write(display, SPLL_CTL, hw_state->spll);
intel_de_posting_read(display, SPLL_CTL);
@@ -1284,9 +1287,8 @@ static const struct intel_dpll_funcs hsw_ddi_spll_funcs = {
.get_freq = hsw_ddi_spll_get_freq,
};
-static void hsw_ddi_lcpll_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *hw_state)
+static void hsw_ddi_lcpll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
}
@@ -1377,11 +1379,12 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
intel_de_posting_read(display, DPLL_CTRL1);
}
-static void skl_ddi_pll_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void skl_ddi_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+ const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
const enum intel_dpll_id id = pll->info->id;
@@ -1399,11 +1402,12 @@ static void skl_ddi_pll_enable(struct intel_display *display,
drm_err(display->drm, "DPLL %d not locked\n", id);
}
-static void skl_ddi_dpll0_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void skl_ddi_dpll0_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+ const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
skl_ddi_pll_write_ctrl1(display, pll, hw_state);
}
@@ -2037,11 +2041,12 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
.compare_hw_state = skl_compare_hw_state,
};
-static void bxt_ddi_pll_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void bxt_ddi_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+ const struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy = DPIO_PHY0;
enum dpio_channel ch = DPIO_CH0;
@@ -3953,11 +3958,12 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte
drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
}
-static void combo_pll_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void combo_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
icl_pll_power_enable(display, pll, enable_reg);
@@ -3977,11 +3983,12 @@ static void combo_pll_enable(struct intel_display *display,
/* DVFS post sequence would be here. See the comment above. */
}
-static void tbt_pll_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void tbt_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
@@ -3998,11 +4005,12 @@ static void tbt_pll_enable(struct intel_display *display,
/* DVFS post sequence would be here. See the comment above. */
}
-static void mg_pll_enable(struct intel_display *display,
- struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static void mg_pll_enable(const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
icl_pll_power_enable(display, pll, enable_reg);
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 09/18] drm/i915/dpll: Change argument for enable hook in intel_dpll_funcs
2025-05-09 4:27 ` [PATCH 09/18] drm/i915/dpll: Change argument for enable hook in intel_dpll_funcs Suraj Kandpal
@ 2025-05-09 10:22 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:22 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Change the arguments for enable hook in intel_dpll_funcs to only
> accept crtc_state.
But that does not match the patch! You also add encoder parameter...
> This is because we really don't need those extra
> arguments everything can be derived from crtc_state and we need both
> intel_encoder and crtc_state for PLL enablement when DISPLAY_VER() >= 14
...and you mention it here too.
> which requires us to pass this crtc state if we want the future
> PLL framework to fit into the existing one and not use the intel_ddi
> hooks
>
> --v2
> -Rename global_dpll to dpll_global to keep consistency with filename
> [Jani/Ville]
>
> --v3
> -Just use intel_dpll [Jani]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 100 ++++++++++--------
> 1 file changed, 54 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index f1b704f369f9..21080abc6d42 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -69,9 +69,8 @@ struct intel_dpll_funcs {
> * Hook for enabling the pll, called from intel_enable_dpll() if
> * the pll is not already enabled.
> */
> - void (*enable)(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state);
> + void (*enable)(const struct intel_crtc_state *state,
> + struct intel_encoder *encoder);
You pass in NULL encoder. Why? What does it mean? The comment should
mention that. Or pass in the proper encoder always to reduce special
casing?
BR,
Jani.
>
> /*
> * Hook for disabling the pll, called from intel_disable_dpll()
> @@ -229,13 +228,15 @@ intel_tc_pll_enable_reg(struct intel_display *display,
> return MG_PLL_ENABLE(tc_port);
> }
>
> -static void _intel_enable_shared_dpll(struct intel_display *display,
> - struct intel_dpll *pll)
> +static void _intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> +
> if (pll->info->power_domain)
> pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
>
> - pll->info->funcs->enable(display, pll, &pll->state.hw_state);
> + pll->info->funcs->enable(crtc_state, NULL);
> pll->on = true;
> }
>
> @@ -289,7 +290,7 @@ void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
>
> drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
>
> - _intel_enable_shared_dpll(display, pll);
> + _intel_enable_shared_dpll(crtc_state);
>
> out:
> mutex_unlock(&display->dpll.lock);
> @@ -561,11 +562,12 @@ static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
> "PCH refclk assertion failure, should be active but is disabled\n");
> }
>
> -static void ibx_pch_dpll_enable(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static void ibx_pch_dpll_enable(const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> + const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
> const enum intel_dpll_id id = pll->info->id;
>
> /* PCH refclock must be enabled first */
> @@ -691,11 +693,12 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
> .compare_hw_state = ibx_compare_hw_state,
> };
>
> -static void hsw_ddi_wrpll_enable(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static void hsw_ddi_wrpll_enable(const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> + const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
> const enum intel_dpll_id id = pll->info->id;
>
> intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);
> @@ -703,11 +706,11 @@ static void hsw_ddi_wrpll_enable(struct intel_display *display,
> udelay(20);
> }
>
> -static void hsw_ddi_spll_enable(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static void hsw_ddi_spll_enable(const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> + struct intel_display *display = to_intel_display(crtc_state);
> + const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
>
> intel_de_write(display, SPLL_CTL, hw_state->spll);
> intel_de_posting_read(display, SPLL_CTL);
> @@ -1284,9 +1287,8 @@ static const struct intel_dpll_funcs hsw_ddi_spll_funcs = {
> .get_freq = hsw_ddi_spll_get_freq,
> };
>
> -static void hsw_ddi_lcpll_enable(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *hw_state)
> +static void hsw_ddi_lcpll_enable(const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> }
>
> @@ -1377,11 +1379,12 @@ static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
> intel_de_posting_read(display, DPLL_CTRL1);
> }
>
> -static void skl_ddi_pll_enable(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static void skl_ddi_pll_enable(const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> + const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
> const struct skl_dpll_regs *regs = skl_dpll_regs;
> const enum intel_dpll_id id = pll->info->id;
>
> @@ -1399,11 +1402,12 @@ static void skl_ddi_pll_enable(struct intel_display *display,
> drm_err(display->drm, "DPLL %d not locked\n", id);
> }
>
> -static void skl_ddi_dpll0_enable(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static void skl_ddi_dpll0_enable(const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> + const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
>
> skl_ddi_pll_write_ctrl1(display, pll, hw_state);
> }
> @@ -2037,11 +2041,12 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
> .compare_hw_state = skl_compare_hw_state,
> };
>
> -static void bxt_ddi_pll_enable(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static void bxt_ddi_pll_enable(const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> + const struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
> enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
> enum dpio_phy phy = DPIO_PHY0;
> enum dpio_channel ch = DPIO_CH0;
> @@ -3953,11 +3958,12 @@ static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct inte
> drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
> }
>
> -static void combo_pll_enable(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static void combo_pll_enable(const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> + const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
> i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
>
> icl_pll_power_enable(display, pll, enable_reg);
> @@ -3977,11 +3983,12 @@ static void combo_pll_enable(struct intel_display *display,
> /* DVFS post sequence would be here. See the comment above. */
> }
>
> -static void tbt_pll_enable(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static void tbt_pll_enable(const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> + const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
>
> icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
>
> @@ -3998,11 +4005,12 @@ static void tbt_pll_enable(struct intel_display *display,
> /* DVFS post sequence would be here. See the comment above. */
> }
>
> -static void mg_pll_enable(struct intel_display *display,
> - struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static void mg_pll_enable(const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> + const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
> i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
>
> icl_pll_power_enable(display, pll, enable_reg);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 10/18] drm/i915/drm: Rename disable hook in intel_dpll_global_func
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (8 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 09/18] drm/i915/dpll: Change argument for enable hook in intel_dpll_funcs Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:24 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 11/18] drm/i915/dpll: Introduce new hook in intel_dpll_funcs Suraj Kandpal
` (7 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename the disable hook to disable_shared_dpll since it will be used
only to disable shared dpll and not individual PLL going forward.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 21080abc6d42..51dab49d4fc1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -73,12 +73,12 @@ struct intel_dpll_funcs {
struct intel_encoder *encoder);
/*
- * Hook for disabling the pll, called from intel_disable_dpll()
+ * Hook for disabling the shared pll, called from _intel_disable_shared_dpll()
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
- void (*disable)(struct intel_display *display,
- struct intel_dpll *pll);
+ void (*shared_dpll_disable)(struct intel_display *display,
+ struct intel_dpll *pll);
/*
* Hook for reading the values currently programmed to the DPLL
@@ -243,7 +243,7 @@ static void _intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
static void _intel_disable_shared_dpll(struct intel_display *display,
struct intel_dpll *pll)
{
- pll->info->funcs->disable(display, pll);
+ pll->info->funcs->shared_dpll_disable(display, pll);
pll->on = false;
if (pll->info->power_domain)
@@ -674,7 +674,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_dpll_funcs ibx_pch_dpll_funcs = {
.enable = ibx_pch_dpll_enable,
- .disable = ibx_pch_dpll_disable,
+ .shared_dpll_disable = ibx_pch_dpll_disable,
.get_hw_state = ibx_pch_dpll_get_hw_state,
};
@@ -1275,14 +1275,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_dpll_funcs hsw_ddi_wrpll_funcs = {
.enable = hsw_ddi_wrpll_enable,
- .disable = hsw_ddi_wrpll_disable,
+ .shared_dpll_disable = hsw_ddi_wrpll_disable,
.get_hw_state = hsw_ddi_wrpll_get_hw_state,
.get_freq = hsw_ddi_wrpll_get_freq,
};
static const struct intel_dpll_funcs hsw_ddi_spll_funcs = {
.enable = hsw_ddi_spll_enable,
- .disable = hsw_ddi_spll_disable,
+ .shared_dpll_disable = hsw_ddi_spll_disable,
.get_hw_state = hsw_ddi_spll_get_hw_state,
.get_freq = hsw_ddi_spll_get_freq,
};
@@ -1306,7 +1306,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
static const struct intel_dpll_funcs hsw_ddi_lcpll_funcs = {
.enable = hsw_ddi_lcpll_enable,
- .disable = hsw_ddi_lcpll_disable,
+ .shared_dpll_disable = hsw_ddi_lcpll_disable,
.get_hw_state = hsw_ddi_lcpll_get_hw_state,
.get_freq = hsw_ddi_lcpll_get_freq,
};
@@ -2010,14 +2010,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_dpll_funcs skl_ddi_pll_funcs = {
.enable = skl_ddi_pll_enable,
- .disable = skl_ddi_pll_disable,
+ .shared_dpll_disable = skl_ddi_pll_disable,
.get_hw_state = skl_ddi_pll_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
};
static const struct intel_dpll_funcs skl_ddi_dpll0_funcs = {
.enable = skl_ddi_dpll0_enable,
- .disable = skl_ddi_dpll0_disable,
+ .shared_dpll_disable = skl_ddi_dpll0_disable,
.get_hw_state = skl_ddi_dpll0_get_hw_state,
.get_freq = skl_ddi_pll_get_freq,
};
@@ -2493,7 +2493,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_dpll_funcs bxt_ddi_pll_funcs = {
.enable = bxt_ddi_pll_enable,
- .disable = bxt_ddi_pll_disable,
+ .shared_dpll_disable = bxt_ddi_pll_disable,
.get_hw_state = bxt_ddi_pll_get_hw_state,
.get_freq = bxt_ddi_pll_get_freq,
};
@@ -4138,21 +4138,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
static const struct intel_dpll_funcs combo_pll_funcs = {
.enable = combo_pll_enable,
- .disable = combo_pll_disable,
+ .shared_dpll_disable = combo_pll_disable,
.get_hw_state = combo_pll_get_hw_state,
.get_freq = icl_ddi_combo_pll_get_freq,
};
static const struct intel_dpll_funcs tbt_pll_funcs = {
.enable = tbt_pll_enable,
- .disable = tbt_pll_disable,
+ .shared_dpll_disable = tbt_pll_disable,
.get_hw_state = tbt_pll_get_hw_state,
.get_freq = icl_ddi_tbt_pll_get_freq,
};
static const struct intel_dpll_funcs mg_pll_funcs = {
.enable = mg_pll_enable,
- .disable = mg_pll_disable,
+ .shared_dpll_disable = mg_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
.get_freq = icl_ddi_mg_pll_get_freq,
};
@@ -4200,7 +4200,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
static const struct intel_dpll_funcs dkl_pll_funcs = {
.enable = mg_pll_enable,
- .disable = mg_pll_disable,
+ .shared_dpll_disable = mg_pll_disable,
.get_hw_state = dkl_pll_get_hw_state,
.get_freq = icl_ddi_mg_pll_get_freq,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 10/18] drm/i915/drm: Rename disable hook in intel_dpll_global_func
2025-05-09 4:27 ` [PATCH 10/18] drm/i915/drm: Rename disable hook in intel_dpll_global_func Suraj Kandpal
@ 2025-05-09 10:24 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:24 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename the disable hook to disable_shared_dpll since it will be used
> only to disable shared dpll and not individual PLL going forward.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
This is hard to review with no actual user at hand.
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++----------
> 1 file changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 21080abc6d42..51dab49d4fc1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -73,12 +73,12 @@ struct intel_dpll_funcs {
> struct intel_encoder *encoder);
>
> /*
> - * Hook for disabling the pll, called from intel_disable_dpll()
> + * Hook for disabling the shared pll, called from _intel_disable_shared_dpll()
> * only when it is safe to disable the pll, i.e., there are no more
> * tracked users for it.
> */
> - void (*disable)(struct intel_display *display,
> - struct intel_dpll *pll);
> + void (*shared_dpll_disable)(struct intel_display *display,
> + struct intel_dpll *pll);
>
> /*
> * Hook for reading the values currently programmed to the DPLL
> @@ -243,7 +243,7 @@ static void _intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
> static void _intel_disable_shared_dpll(struct intel_display *display,
> struct intel_dpll *pll)
> {
> - pll->info->funcs->disable(display, pll);
> + pll->info->funcs->shared_dpll_disable(display, pll);
> pll->on = false;
>
> if (pll->info->power_domain)
> @@ -674,7 +674,7 @@ static bool ibx_compare_hw_state(const struct intel_dpll_hw_state *_a,
>
> static const struct intel_dpll_funcs ibx_pch_dpll_funcs = {
> .enable = ibx_pch_dpll_enable,
> - .disable = ibx_pch_dpll_disable,
> + .shared_dpll_disable = ibx_pch_dpll_disable,
> .get_hw_state = ibx_pch_dpll_get_hw_state,
> };
>
> @@ -1275,14 +1275,14 @@ static bool hsw_compare_hw_state(const struct intel_dpll_hw_state *_a,
>
> static const struct intel_dpll_funcs hsw_ddi_wrpll_funcs = {
> .enable = hsw_ddi_wrpll_enable,
> - .disable = hsw_ddi_wrpll_disable,
> + .shared_dpll_disable = hsw_ddi_wrpll_disable,
> .get_hw_state = hsw_ddi_wrpll_get_hw_state,
> .get_freq = hsw_ddi_wrpll_get_freq,
> };
>
> static const struct intel_dpll_funcs hsw_ddi_spll_funcs = {
> .enable = hsw_ddi_spll_enable,
> - .disable = hsw_ddi_spll_disable,
> + .shared_dpll_disable = hsw_ddi_spll_disable,
> .get_hw_state = hsw_ddi_spll_get_hw_state,
> .get_freq = hsw_ddi_spll_get_freq,
> };
> @@ -1306,7 +1306,7 @@ static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
>
> static const struct intel_dpll_funcs hsw_ddi_lcpll_funcs = {
> .enable = hsw_ddi_lcpll_enable,
> - .disable = hsw_ddi_lcpll_disable,
> + .shared_dpll_disable = hsw_ddi_lcpll_disable,
> .get_hw_state = hsw_ddi_lcpll_get_hw_state,
> .get_freq = hsw_ddi_lcpll_get_freq,
> };
> @@ -2010,14 +2010,14 @@ static bool skl_compare_hw_state(const struct intel_dpll_hw_state *_a,
>
> static const struct intel_dpll_funcs skl_ddi_pll_funcs = {
> .enable = skl_ddi_pll_enable,
> - .disable = skl_ddi_pll_disable,
> + .shared_dpll_disable = skl_ddi_pll_disable,
> .get_hw_state = skl_ddi_pll_get_hw_state,
> .get_freq = skl_ddi_pll_get_freq,
> };
>
> static const struct intel_dpll_funcs skl_ddi_dpll0_funcs = {
> .enable = skl_ddi_dpll0_enable,
> - .disable = skl_ddi_dpll0_disable,
> + .shared_dpll_disable = skl_ddi_dpll0_disable,
> .get_hw_state = skl_ddi_dpll0_get_hw_state,
> .get_freq = skl_ddi_pll_get_freq,
> };
> @@ -2493,7 +2493,7 @@ static bool bxt_compare_hw_state(const struct intel_dpll_hw_state *_a,
>
> static const struct intel_dpll_funcs bxt_ddi_pll_funcs = {
> .enable = bxt_ddi_pll_enable,
> - .disable = bxt_ddi_pll_disable,
> + .shared_dpll_disable = bxt_ddi_pll_disable,
> .get_hw_state = bxt_ddi_pll_get_hw_state,
> .get_freq = bxt_ddi_pll_get_freq,
> };
> @@ -4138,21 +4138,21 @@ static bool icl_compare_hw_state(const struct intel_dpll_hw_state *_a,
>
> static const struct intel_dpll_funcs combo_pll_funcs = {
> .enable = combo_pll_enable,
> - .disable = combo_pll_disable,
> + .shared_dpll_disable = combo_pll_disable,
> .get_hw_state = combo_pll_get_hw_state,
> .get_freq = icl_ddi_combo_pll_get_freq,
> };
>
> static const struct intel_dpll_funcs tbt_pll_funcs = {
> .enable = tbt_pll_enable,
> - .disable = tbt_pll_disable,
> + .shared_dpll_disable = tbt_pll_disable,
> .get_hw_state = tbt_pll_get_hw_state,
> .get_freq = icl_ddi_tbt_pll_get_freq,
> };
>
> static const struct intel_dpll_funcs mg_pll_funcs = {
> .enable = mg_pll_enable,
> - .disable = mg_pll_disable,
> + .shared_dpll_disable = mg_pll_disable,
> .get_hw_state = mg_pll_get_hw_state,
> .get_freq = icl_ddi_mg_pll_get_freq,
> };
> @@ -4200,7 +4200,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
>
> static const struct intel_dpll_funcs dkl_pll_funcs = {
> .enable = mg_pll_enable,
> - .disable = mg_pll_disable,
> + .shared_dpll_disable = mg_pll_disable,
> .get_hw_state = dkl_pll_get_hw_state,
> .get_freq = icl_ddi_mg_pll_get_freq,
> };
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 11/18] drm/i915/dpll: Introduce new hook in intel_dpll_funcs
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (9 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 10/18] drm/i915/drm: Rename disable hook in intel_dpll_global_func Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:25 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 12/18] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook Suraj Kandpal
` (6 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Introduce disable hook to disable individual dpll which is to
be used by DISPLAY_VER() >= 14.
--v2
-Rename intel_global_dpll to intel_dpll_global [Jani/Ville]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 51dab49d4fc1..85f726b1c5c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -73,7 +73,13 @@ struct intel_dpll_funcs {
struct intel_encoder *encoder);
/*
- * Hook for disabling the shared pll, called from _intel_disable_shared_dpll()
+ * Hook for disabling the individual pll, used from DISPLAY_VER() >= 14
+ */
+ void (*disable)(struct intel_display *display,
+ struct intel_dpll *pll);
+
+ /*
+ * Hook for disabling the shared pll, called from intel_disable_global_dpll()
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 11/18] drm/i915/dpll: Introduce new hook in intel_dpll_funcs
2025-05-09 4:27 ` [PATCH 11/18] drm/i915/dpll: Introduce new hook in intel_dpll_funcs Suraj Kandpal
@ 2025-05-09 10:25 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:25 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Introduce disable hook to disable individual dpll which is to
> be used by DISPLAY_VER() >= 14.
>
> --v2
> -Rename intel_global_dpll to intel_dpll_global [Jani/Ville]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
This is hard to review with no actual user at hand.
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 51dab49d4fc1..85f726b1c5c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -73,7 +73,13 @@ struct intel_dpll_funcs {
> struct intel_encoder *encoder);
>
> /*
> - * Hook for disabling the shared pll, called from _intel_disable_shared_dpll()
> + * Hook for disabling the individual pll, used from DISPLAY_VER() >= 14
> + */
> + void (*disable)(struct intel_display *display,
> + struct intel_dpll *pll);
> +
> + /*
> + * Hook for disabling the shared pll, called from intel_disable_global_dpll()
> * only when it is safe to disable the pll, i.e., there are no more
> * tracked users for it.
> */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 12/18] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (10 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 11/18] drm/i915/dpll: Introduce new hook in intel_dpll_funcs Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:25 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 13/18] drm/i915/dpll: Change arguments for get_freq hook Suraj Kandpal
` (5 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Add intel_encoder argument in the get_hw_state hook as encoders
and the data stored within them are essential to read the hw state
starting DISPLAY_VER() >= 14.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 ++++++++++++-------
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 85f726b1c5c8..4a184d1e83a3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -93,7 +93,8 @@ struct intel_dpll_funcs {
*/
bool (*get_hw_state)(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state);
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder);
/*
* Hook for calculating the pll's output frequency based on its passed
@@ -534,7 +535,8 @@ void intel_dpll_swap_state(struct intel_atomic_state *state)
static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
const enum intel_dpll_id id = pll->info->id;
@@ -757,7 +759,8 @@ static void hsw_ddi_spll_disable(struct intel_display *display,
static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
const enum intel_dpll_id id = pll->info->id;
@@ -779,7 +782,8 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
intel_wakeref_t wakeref;
@@ -1305,7 +1309,8 @@ static void hsw_ddi_lcpll_disable(struct intel_display *display,
static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
return true;
}
@@ -1436,7 +1441,8 @@ static void skl_ddi_dpll0_disable(struct intel_display *display,
static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
@@ -1474,7 +1480,8 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
const struct skl_dpll_regs *regs = skl_dpll_regs;
@@ -2172,7 +2179,8 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
@@ -3550,7 +3558,8 @@ static void icl_put_dplls(struct intel_atomic_state *state,
static bool mg_pll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
@@ -3617,7 +3626,8 @@ static bool mg_pll_get_hw_state(struct intel_display *display,
static bool dkl_pll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
const enum intel_dpll_id id = pll->info->id;
@@ -3750,7 +3760,8 @@ static bool icl_pll_get_hw_state(struct intel_display *display,
static bool combo_pll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
@@ -3759,7 +3770,8 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
static bool tbt_pll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
- struct intel_dpll_hw_state *dpll_hw_state)
+ struct intel_dpll_hw_state *dpll_hw_state,
+ struct intel_encoder *encoder)
{
return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
}
@@ -4516,7 +4528,7 @@ bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
- return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
+ return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state, NULL);
}
static void readout_dpll_hw_state(struct intel_display *display,
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 12/18] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook
2025-05-09 4:27 ` [PATCH 12/18] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook Suraj Kandpal
@ 2025-05-09 10:25 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:25 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Add intel_encoder argument in the get_hw_state hook as encoders
> and the data stored within them are essential to read the hw state
> starting DISPLAY_VER() >= 14.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
This is hard to review with no user at hand.
Also, what does it mean to pass NULL for the encoder?
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 ++++++++++++-------
> 1 file changed, 25 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 85f726b1c5c8..4a184d1e83a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -93,7 +93,8 @@ struct intel_dpll_funcs {
> */
> bool (*get_hw_state)(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state);
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder);
>
> /*
> * Hook for calculating the pll's output frequency based on its passed
> @@ -534,7 +535,8 @@ void intel_dpll_swap_state(struct intel_atomic_state *state)
>
> static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
> const enum intel_dpll_id id = pll->info->id;
> @@ -757,7 +759,8 @@ static void hsw_ddi_spll_disable(struct intel_display *display,
>
> static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> const enum intel_dpll_id id = pll->info->id;
> @@ -779,7 +782,8 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
>
> static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> intel_wakeref_t wakeref;
> @@ -1305,7 +1309,8 @@ static void hsw_ddi_lcpll_disable(struct intel_display *display,
>
> static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> return true;
> }
> @@ -1436,7 +1441,8 @@ static void skl_ddi_dpll0_disable(struct intel_display *display,
>
> static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> const struct skl_dpll_regs *regs = skl_dpll_regs;
> @@ -1474,7 +1480,8 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
>
> static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> const struct skl_dpll_regs *regs = skl_dpll_regs;
> @@ -2172,7 +2179,8 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
>
> static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
> @@ -3550,7 +3558,8 @@ static void icl_put_dplls(struct intel_atomic_state *state,
>
> static bool mg_pll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> const enum intel_dpll_id id = pll->info->id;
> @@ -3617,7 +3626,8 @@ static bool mg_pll_get_hw_state(struct intel_display *display,
>
> static bool dkl_pll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> const enum intel_dpll_id id = pll->info->id;
> @@ -3750,7 +3760,8 @@ static bool icl_pll_get_hw_state(struct intel_display *display,
>
> static bool combo_pll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
>
> @@ -3759,7 +3770,8 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
>
> static bool tbt_pll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> - struct intel_dpll_hw_state *dpll_hw_state)
> + struct intel_dpll_hw_state *dpll_hw_state,
> + struct intel_encoder *encoder)
> {
> return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
> }
> @@ -4516,7 +4528,7 @@ bool intel_dpll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> - return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
> + return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state, NULL);
> }
>
> static void readout_dpll_hw_state(struct intel_display *display,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 13/18] drm/i915/dpll: Change arguments for get_freq hook
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (11 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 12/18] drm/i915/dpll: Add intel_encoder argument to get_hw_state hook Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:27 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 14/18] drm/i915/dpll: Rename intel_[enable/disable]_dpll Suraj Kandpal
` (4 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Change the arguments for get_freq hook in intel_dpll_funcs
to use only intel_crtc_state and intel_encoder since that all we need
and the rest can be derived from the above two.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 107 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 5 +-
3 files changed, 57 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 11ebcb40c91f..66dea34ebcd3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4203,8 +4203,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = intel_dpll_get_freq(crtc_state, encoder);
}
static void mtl_ddi_get_config(struct intel_encoder *encoder,
@@ -4316,8 +4315,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
else
- crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = intel_dpll_get_freq(crtc_state, encoder);
}
static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4a184d1e83a3..3a724d84861b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -79,7 +79,7 @@ struct intel_dpll_funcs {
struct intel_dpll *pll);
/*
- * Hook for disabling the shared pll, called from intel_disable_global_dpll()
+ * Hook for disabling the shared pll, called from intel_disable_dpll()
* only when it is safe to disable the pll, i.e., there are no more
* tracked users for it.
*/
@@ -100,9 +100,8 @@ struct intel_dpll_funcs {
* Hook for calculating the pll's output frequency based on its passed
* in state.
*/
- int (*get_freq)(struct intel_display *i915,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state);
+ int (*get_freq)(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder);
};
struct intel_dpll_mgr {
@@ -1008,11 +1007,11 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
*r2_out = best.r2;
}
-static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int hsw_ddi_wrpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
int refclk;
int n, p, r;
u32 wrpll = hw_state->wrpll;
@@ -1053,7 +1052,6 @@ static int
hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct intel_display *display = to_intel_display(state);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
@@ -1066,8 +1064,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
WRPLL_DIVIDER_POST(p);
- crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = hsw_ddi_wrpll_get_freq(crtc_state, NULL);
return 0;
}
@@ -1134,10 +1131,11 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
return pll;
}
-static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int hsw_ddi_lcpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
int link_clock = 0;
switch (pll->info->id) {
@@ -1186,11 +1184,11 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
BIT(DPLL_ID_SPLL));
}
-static int hsw_ddi_spll_get_freq(struct intel_display *display,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int hsw_ddi_spll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
int link_clock = 0;
switch (hw_state->spll & SPLL_FREQ_MASK) {
@@ -1979,20 +1977,21 @@ static int skl_get_dpll(struct intel_atomic_state *state,
return 0;
}
-static int skl_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int skl_ddi_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+ const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
/*
* ctrl1 register is already shifted for each pll, just use 0 to get
* the internal shift for each field
*/
if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
- return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
+ return skl_ddi_wrpll_get_freq(display, pll, &crtc_state->dpll_hw_state);
else
- return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
+ return skl_ddi_lcpll_get_freq(display, pll, &crtc_state->dpll_hw_state);
}
static void skl_update_dpll_ref_clks(struct intel_display *display)
@@ -2378,11 +2377,11 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
return 0;
}
-static int bxt_ddi_pll_get_freq(struct intel_display *display,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int bxt_ddi_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
struct dpll clock;
clock.m1 = 2;
@@ -2410,7 +2409,6 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
static int
bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
struct dpll clk_div = {};
int ret;
@@ -2420,8 +2418,7 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
if (ret)
return ret;
- crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,
- &crtc_state->dpll_hw_state);
+ crtc_state->port_clock = bxt_ddi_pll_get_freq(crtc_state, NULL);
return 0;
}
@@ -2773,10 +2770,11 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int icl_ddi_tbt_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+
/*
* The PLL outputs multiple frequencies at the same time, selection is
* made at DDI clock mux level.
@@ -2844,11 +2842,11 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int icl_ddi_combo_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
int ref_clock = icl_wrpll_ref_clock(display);
u32 dco_fraction;
u32 p0, p1, p2, dco_freq;
@@ -3217,11 +3215,11 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
return 0;
}
-static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+static int icl_ddi_mg_pll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
- const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
@@ -3354,8 +3352,7 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
/* this is mainly for the fastset check */
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
- crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,
- &port_dpll->hw_state);
+ crtc_state->port_clock = icl_ddi_combo_pll_get_freq(crtc_state, NULL);
return 0;
}
@@ -3453,8 +3450,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
else
icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
- crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,
- &port_dpll->hw_state);
+ crtc_state->port_clock = icl_ddi_mg_pll_get_freq(crtc_state, NULL);
return 0;
}
@@ -4500,20 +4496,23 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
/**
* intel_dpll_get_freq - calculate the DPLL's output frequency
- * @display: intel_display device
- * @pll: DPLL for which to calculate the output frequency
- * @dpll_hw_state: DPLL state from which to calculate the output frequency
+ * @crtc_state: crtc_state which contains the DPLL state from which we
+ * calculate frequency
+ * @encoder: Encoder for which the freq is calculated
*
- * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
+ * Return the output frequency corresponding to @pll's passed in
+ * @crtc_state->dpll_hw_state.
*/
-int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state)
+int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_dpll *pll = crtc_state->intel_dpll;
+
if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
return 0;
- return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
+ return pll->info->funcs->get_freq(crtc_state, encoder);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 99a058deaeda..49eb02d72f44 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -412,9 +412,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-int intel_dpll_get_freq(struct intel_display *display,
- const struct intel_dpll *pll,
- const struct intel_dpll_hw_state *dpll_hw_state);
+int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder);
bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 13/18] drm/i915/dpll: Change arguments for get_freq hook
2025-05-09 4:27 ` [PATCH 13/18] drm/i915/dpll: Change arguments for get_freq hook Suraj Kandpal
@ 2025-05-09 10:27 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:27 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Change the arguments for get_freq hook in intel_dpll_funcs
> to use only intel_crtc_state and intel_encoder since that all we need
> and the rest can be derived from the above two.
Same as before, hard to review with no user, what does NULL mean.
It's generally not enough to say "we need" when you don't say why, and
there's no user to justify.
BR,
Jani.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 107 +++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 5 +-
> 3 files changed, 57 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 11ebcb40c91f..66dea34ebcd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4203,8 +4203,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
>
> icl_set_active_port_dpll(crtc_state, port_dpll_id);
>
> - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
> - &crtc_state->dpll_hw_state);
> + crtc_state->port_clock = intel_dpll_get_freq(crtc_state, encoder);
> }
>
> static void mtl_ddi_get_config(struct intel_encoder *encoder,
> @@ -4316,8 +4315,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
> if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
> crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
> else
> - crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
> - &crtc_state->dpll_hw_state);
> + crtc_state->port_clock = intel_dpll_get_freq(crtc_state, encoder);
> }
>
> static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 4a184d1e83a3..3a724d84861b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -79,7 +79,7 @@ struct intel_dpll_funcs {
> struct intel_dpll *pll);
>
> /*
> - * Hook for disabling the shared pll, called from intel_disable_global_dpll()
> + * Hook for disabling the shared pll, called from intel_disable_dpll()
> * only when it is safe to disable the pll, i.e., there are no more
> * tracked users for it.
> */
> @@ -100,9 +100,8 @@ struct intel_dpll_funcs {
> * Hook for calculating the pll's output frequency based on its passed
> * in state.
> */
> - int (*get_freq)(struct intel_display *i915,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state);
> + int (*get_freq)(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder);
> };
>
> struct intel_dpll_mgr {
> @@ -1008,11 +1007,11 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
> *r2_out = best.r2;
> }
>
> -static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static int hsw_ddi_wrpll_get_freq(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> + struct intel_display *display = to_intel_display(crtc_state);
> + const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
> int refclk;
> int n, p, r;
> u32 wrpll = hw_state->wrpll;
> @@ -1053,7 +1052,6 @@ static int
> hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> - struct intel_display *display = to_intel_display(state);
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
> @@ -1066,8 +1064,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
> WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
> WRPLL_DIVIDER_POST(p);
>
> - crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,
> - &crtc_state->dpll_hw_state);
> + crtc_state->port_clock = hsw_ddi_wrpll_get_freq(crtc_state, NULL);
>
> return 0;
> }
> @@ -1134,10 +1131,11 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
> return pll;
> }
>
> -static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static int hsw_ddi_lcpll_get_freq(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> int link_clock = 0;
>
> switch (pll->info->id) {
> @@ -1186,11 +1184,11 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
> BIT(DPLL_ID_SPLL));
> }
>
> -static int hsw_ddi_spll_get_freq(struct intel_display *display,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static int hsw_ddi_spll_get_freq(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
> + struct intel_display *display = to_intel_display(crtc_state);
> + const struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
> int link_clock = 0;
>
> switch (hw_state->spll & SPLL_FREQ_MASK) {
> @@ -1979,20 +1977,21 @@ static int skl_get_dpll(struct intel_atomic_state *state,
> return 0;
> }
>
> -static int skl_ddi_pll_get_freq(struct intel_display *display,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static int skl_ddi_pll_get_freq(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> + const struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
>
> /*
> * ctrl1 register is already shifted for each pll, just use 0 to get
> * the internal shift for each field
> */
> if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
> - return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
> + return skl_ddi_wrpll_get_freq(display, pll, &crtc_state->dpll_hw_state);
> else
> - return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
> + return skl_ddi_lcpll_get_freq(display, pll, &crtc_state->dpll_hw_state);
> }
>
> static void skl_update_dpll_ref_clks(struct intel_display *display)
> @@ -2378,11 +2377,11 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> -static int bxt_ddi_pll_get_freq(struct intel_display *display,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static int bxt_ddi_pll_get_freq(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> + struct intel_display *display = to_intel_display(crtc_state);
> + const struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
> struct dpll clock;
>
> clock.m1 = 2;
> @@ -2410,7 +2409,6 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> static int
> bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> {
> - struct intel_display *display = to_intel_display(crtc_state);
> struct dpll clk_div = {};
> int ret;
>
> @@ -2420,8 +2418,7 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> if (ret)
> return ret;
>
> - crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,
> - &crtc_state->dpll_hw_state);
> + crtc_state->port_clock = bxt_ddi_pll_get_freq(crtc_state, NULL);
>
> return 0;
> }
> @@ -2773,10 +2770,11 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> -static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static int icl_ddi_tbt_pll_get_freq(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> /*
> * The PLL outputs multiple frequencies at the same time, selection is
> * made at DDI clock mux level.
> @@ -2844,11 +2842,11 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> -static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static int icl_ddi_combo_pll_get_freq(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> + struct intel_display *display = to_intel_display(crtc_state);
> + const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
> int ref_clock = icl_wrpll_ref_clock(display);
> u32 dco_fraction;
> u32 p0, p1, p2, dco_freq;
> @@ -3217,11 +3215,11 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> -static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +static int icl_ddi_mg_pll_get_freq(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> - const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> + struct intel_display *display = to_intel_display(crtc_state);
> + const struct icl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.icl;
> u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
> u64 tmp;
>
> @@ -3354,8 +3352,7 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
> /* this is mainly for the fastset check */
> icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
>
> - crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,
> - &port_dpll->hw_state);
> + crtc_state->port_clock = icl_ddi_combo_pll_get_freq(crtc_state, NULL);
>
> return 0;
> }
> @@ -3453,8 +3450,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> else
> icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
>
> - crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,
> - &port_dpll->hw_state);
> + crtc_state->port_clock = icl_ddi_mg_pll_get_freq(crtc_state, NULL);
>
> return 0;
> }
> @@ -4500,20 +4496,23 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
>
> /**
> * intel_dpll_get_freq - calculate the DPLL's output frequency
> - * @display: intel_display device
> - * @pll: DPLL for which to calculate the output frequency
> - * @dpll_hw_state: DPLL state from which to calculate the output frequency
> + * @crtc_state: crtc_state which contains the DPLL state from which we
> + * calculate frequency
> + * @encoder: Encoder for which the freq is calculated
> *
> - * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
> + * Return the output frequency corresponding to @pll's passed in
> + * @crtc_state->dpll_hw_state.
> */
> -int intel_dpll_get_freq(struct intel_display *display,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state)
> +int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_dpll *pll = crtc_state->intel_dpll;
> +
> if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
> return 0;
>
> - return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
> + return pll->info->funcs->get_freq(crtc_state, encoder);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 99a058deaeda..49eb02d72f44 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -412,9 +412,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> void intel_update_active_dpll(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> -int intel_dpll_get_freq(struct intel_display *display,
> - const struct intel_dpll *pll,
> - const struct intel_dpll_hw_state *dpll_hw_state);
> +int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder);
> bool intel_dpll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 14/18] drm/i915/dpll: Rename intel_[enable/disable]_dpll
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (12 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 13/18] drm/i915/dpll: Change arguments for get_freq hook Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:29 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 15/18] drm/i915/dpll: Rename intel_unreference_dpll__crtc Suraj Kandpal
` (3 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename intel_[enable/disable]_dpll to intel_dpll_[enable/disable]
in an effort to make sure all functions that are exported
start with the filename.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
drivers/gpu/drm/i915/display/intel_pch_display.c | 6 +++---
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b091faff6680..8ee4833daede 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1664,7 +1664,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_encoders_pre_pll_enable(state, crtc);
if (new_crtc_state->intel_dpll)
- intel_enable_dpll(new_crtc_state);
+ intel_dpll_enable(new_crtc_state);
intel_encoders_pre_enable(state, crtc);
@@ -1793,7 +1793,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
intel_encoders_disable(state, crtc);
intel_encoders_post_disable(state, crtc);
- intel_disable_dpll(old_crtc_state);
+ intel_dpll_disable(old_crtc_state);
intel_encoders_post_pll_disable(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 3a724d84861b..d1399ab24d8c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -257,12 +257,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display,
}
/**
- * intel_enable_dpll - enable a CRTC's global DPLL
+ * intel_dpll_enable - enable a CRTC's global DPLL
* @crtc_state: CRTC, and its state, which has a DPLL
*
* Enable DPLL used by @crtc.
*/
-void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
+void intel_dpll_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -303,12 +303,12 @@ void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
}
/**
- * intel_disable_dpll - disable a CRTC's shared DPLL
+ * intel_dpll_disable - disable a CRTC's shared DPLL
* @crtc_state: CRTC, and its state, which has a shared DPLL
*
* Disable DPLL used by @crtc.
*/
-void intel_disable_dpll(const struct intel_crtc_state *crtc_state)
+void intel_dpll_disable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 49eb02d72f44..f497a9ec863d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -417,8 +417,8 @@ int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
bool intel_dpll_get_hw_state(struct intel_display *display,
struct intel_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state);
-void intel_enable_dpll(const struct intel_crtc_state *crtc_state);
-void intel_disable_dpll(const struct intel_crtc_state *crtc_state);
+void intel_dpll_enable(const struct intel_crtc_state *crtc_state);
+void intel_dpll_disable(const struct intel_crtc_state *crtc_state);
void intel_dpll_swap_state(struct intel_atomic_state *state);
void intel_dpll_init(struct intel_display *display);
void intel_dpll_update_ref_clks(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index b59b3c94f711..ca85596dfc9e 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -394,11 +394,11 @@ void ilk_pch_enable(struct intel_atomic_state *state,
* transcoder, and we actually should do this to not upset any PCH
* transcoder that already use the clock when we share it.
*
- * Note that enable_dpll tries to do the right thing, but
+ * Note that dpll_enable tries to do the right thing, but
* get_dpll unconditionally resets the pll - we need that
* to have the right LVDS enable sequence.
*/
- intel_enable_dpll(crtc_state);
+ intel_dpll_enable(crtc_state);
/* set transcoder timing, panel must allow it */
assert_pps_unlocked(display, pipe);
@@ -472,7 +472,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state,
ilk_fdi_pll_disable(crtc);
- intel_disable_dpll(old_crtc_state);
+ intel_dpll_disable(old_crtc_state);
}
static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 14/18] drm/i915/dpll: Rename intel_[enable/disable]_dpll
2025-05-09 4:27 ` [PATCH 14/18] drm/i915/dpll: Rename intel_[enable/disable]_dpll Suraj Kandpal
@ 2025-05-09 10:29 ` Jani Nikula
2025-05-12 3:19 ` Kandpal, Suraj
0 siblings, 1 reply; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:29 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_[enable/disable]_dpll to intel_dpll_[enable/disable]
> in an effort to make sure all functions that are exported
> start with the filename.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
I think you should repost the series with the controversial or
incomplete stuff dropped, and get the straightforward renames merged.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++----
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
> drivers/gpu/drm/i915/display/intel_pch_display.c | 6 +++---
> 4 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b091faff6680..8ee4833daede 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1664,7 +1664,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> intel_encoders_pre_pll_enable(state, crtc);
>
> if (new_crtc_state->intel_dpll)
> - intel_enable_dpll(new_crtc_state);
> + intel_dpll_enable(new_crtc_state);
>
> intel_encoders_pre_enable(state, crtc);
>
> @@ -1793,7 +1793,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
> intel_encoders_disable(state, crtc);
> intel_encoders_post_disable(state, crtc);
>
> - intel_disable_dpll(old_crtc_state);
> + intel_dpll_disable(old_crtc_state);
>
> intel_encoders_post_pll_disable(state, crtc);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 3a724d84861b..d1399ab24d8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -257,12 +257,12 @@ static void _intel_disable_shared_dpll(struct intel_display *display,
> }
>
> /**
> - * intel_enable_dpll - enable a CRTC's global DPLL
> + * intel_dpll_enable - enable a CRTC's global DPLL
> * @crtc_state: CRTC, and its state, which has a DPLL
> *
> * Enable DPLL used by @crtc.
> */
> -void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
> +void intel_dpll_enable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -303,12 +303,12 @@ void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
> }
>
> /**
> - * intel_disable_dpll - disable a CRTC's shared DPLL
> + * intel_dpll_disable - disable a CRTC's shared DPLL
> * @crtc_state: CRTC, and its state, which has a shared DPLL
> *
> * Disable DPLL used by @crtc.
> */
> -void intel_disable_dpll(const struct intel_crtc_state *crtc_state)
> +void intel_dpll_disable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 49eb02d72f44..f497a9ec863d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -417,8 +417,8 @@ int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
> bool intel_dpll_get_hw_state(struct intel_display *display,
> struct intel_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state);
> -void intel_enable_dpll(const struct intel_crtc_state *crtc_state);
> -void intel_disable_dpll(const struct intel_crtc_state *crtc_state);
> +void intel_dpll_enable(const struct intel_crtc_state *crtc_state);
> +void intel_dpll_disable(const struct intel_crtc_state *crtc_state);
> void intel_dpll_swap_state(struct intel_atomic_state *state);
> void intel_dpll_init(struct intel_display *display);
> void intel_dpll_update_ref_clks(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index b59b3c94f711..ca85596dfc9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -394,11 +394,11 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> * transcoder, and we actually should do this to not upset any PCH
> * transcoder that already use the clock when we share it.
> *
> - * Note that enable_dpll tries to do the right thing, but
> + * Note that dpll_enable tries to do the right thing, but
> * get_dpll unconditionally resets the pll - we need that
> * to have the right LVDS enable sequence.
> */
> - intel_enable_dpll(crtc_state);
> + intel_dpll_enable(crtc_state);
>
> /* set transcoder timing, panel must allow it */
> assert_pps_unlocked(display, pipe);
> @@ -472,7 +472,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state,
>
> ilk_fdi_pll_disable(crtc);
>
> - intel_disable_dpll(old_crtc_state);
> + intel_dpll_disable(old_crtc_state);
> }
>
> static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH 14/18] drm/i915/dpll: Rename intel_[enable/disable]_dpll
2025-05-09 10:29 ` Jani Nikula
@ 2025-05-12 3:19 ` Kandpal, Suraj
0 siblings, 0 replies; 42+ messages in thread
From: Kandpal, Suraj @ 2025-05-12 3:19 UTC (permalink / raw)
To: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Murthy, Arun R
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, May 9, 2025 3:59 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 14/18] drm/i915/dpll: Rename intel_[enable/disable]_dpll
>
> On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Rename intel_[enable/disable]_dpll to intel_dpll_[enable/disable] in
> > an effort to make sure all functions that are exported start with the
> > filename.
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> I think you should repost the series with the controversial or incomplete stuff
> dropped, and get the straightforward renames merged.
I think you are correct , I'll break it into two series will send the controversial changes
With the second part where we refactor the rest of the dpll framework to take into account
The cx0 phy.
Regards,
Suraj Kandpal
>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++----
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
> > drivers/gpu/drm/i915/display/intel_pch_display.c | 6 +++---
> > 4 files changed, 11 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index b091faff6680..8ee4833daede 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1664,7 +1664,7 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> > intel_encoders_pre_pll_enable(state, crtc);
> >
> > if (new_crtc_state->intel_dpll)
> > - intel_enable_dpll(new_crtc_state);
> > + intel_dpll_enable(new_crtc_state);
> >
> > intel_encoders_pre_enable(state, crtc);
> >
> > @@ -1793,7 +1793,7 @@ static void hsw_crtc_disable(struct
> intel_atomic_state *state,
> > intel_encoders_disable(state, crtc);
> > intel_encoders_post_disable(state, crtc);
> >
> > - intel_disable_dpll(old_crtc_state);
> > + intel_dpll_disable(old_crtc_state);
> >
> > intel_encoders_post_pll_disable(state, crtc);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 3a724d84861b..d1399ab24d8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -257,12 +257,12 @@ static void _intel_disable_shared_dpll(struct
> > intel_display *display, }
> >
> > /**
> > - * intel_enable_dpll - enable a CRTC's global DPLL
> > + * intel_dpll_enable - enable a CRTC's global DPLL
> > * @crtc_state: CRTC, and its state, which has a DPLL
> > *
> > * Enable DPLL used by @crtc.
> > */
> > -void intel_enable_dpll(const struct intel_crtc_state *crtc_state)
> > +void intel_dpll_enable(const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -303,12 +303,12 @@ void intel_enable_dpll(const struct
> > intel_crtc_state *crtc_state) }
> >
> > /**
> > - * intel_disable_dpll - disable a CRTC's shared DPLL
> > + * intel_dpll_disable - disable a CRTC's shared DPLL
> > * @crtc_state: CRTC, and its state, which has a shared DPLL
> > *
> > * Disable DPLL used by @crtc.
> > */
> > -void intel_disable_dpll(const struct intel_crtc_state *crtc_state)
> > +void intel_dpll_disable(const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 49eb02d72f44..f497a9ec863d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -417,8 +417,8 @@ int intel_dpll_get_freq(struct intel_crtc_state
> > *crtc_state, bool intel_dpll_get_hw_state(struct intel_display *display,
> > struct intel_dpll *pll,
> > struct intel_dpll_hw_state *dpll_hw_state); -void
> > intel_enable_dpll(const struct intel_crtc_state *crtc_state); -void
> > intel_disable_dpll(const struct intel_crtc_state *crtc_state);
> > +void intel_dpll_enable(const struct intel_crtc_state *crtc_state);
> > +void intel_dpll_disable(const struct intel_crtc_state *crtc_state);
> > void intel_dpll_swap_state(struct intel_atomic_state *state); void
> > intel_dpll_init(struct intel_display *display); void
> > intel_dpll_update_ref_clks(struct intel_display *display); diff --git
> > a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > index b59b3c94f711..ca85596dfc9e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > @@ -394,11 +394,11 @@ void ilk_pch_enable(struct intel_atomic_state
> *state,
> > * transcoder, and we actually should do this to not upset any PCH
> > * transcoder that already use the clock when we share it.
> > *
> > - * Note that enable_dpll tries to do the right thing, but
> > + * Note that dpll_enable tries to do the right thing, but
> > * get_dpll unconditionally resets the pll - we need that
> > * to have the right LVDS enable sequence.
> > */
> > - intel_enable_dpll(crtc_state);
> > + intel_dpll_enable(crtc_state);
> >
> > /* set transcoder timing, panel must allow it */
> > assert_pps_unlocked(display, pipe);
> > @@ -472,7 +472,7 @@ void ilk_pch_post_disable(struct
> > intel_atomic_state *state,
> >
> > ilk_fdi_pll_disable(crtc);
> >
> > - intel_disable_dpll(old_crtc_state);
> > + intel_dpll_disable(old_crtc_state);
> > }
> >
> > static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 15/18] drm/i915/dpll: Rename intel_unreference_dpll__crtc
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (13 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 14/18] drm/i915/dpll: Rename intel_[enable/disable]_dpll Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:31 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 16/18] drm/i915/dpll: Rename intel_<release/reserve>_dpll Suraj Kandpal
` (2 subsequent siblings)
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename intel_unreference_dpll_crtc to intel_dpll_unreference_crtc
in an effort to keep names of exported functions start with the filename.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d1399ab24d8c..c954515145a3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -458,7 +458,7 @@ intel_reference_dpll(struct intel_atomic_state *state,
}
/**
- * intel_unreference_dpll_crtc - Drop a DPLL reference for a CRTC
+ * intel_dpll_unreference_crtc - Drop a DPLL reference for a CRTC
* @crtc: CRTC on which behalf the reference is dropped
* @pll: DPLL for which the reference is dropped
* @dpll_state: the DPLL atomic state in which the reference is tracked
@@ -466,7 +466,7 @@ intel_reference_dpll(struct intel_atomic_state *state,
* Drop a reference for @pll tracking the end of use of it by @crtc.
*/
void
-intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
+intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
const struct intel_dpll *pll,
struct intel_dpll_state *dpll_state)
{
@@ -488,7 +488,7 @@ static void intel_unreference_dpll(struct intel_atomic_state *state,
dpll_state = intel_atomic_get_dpll_state(&state->base);
- intel_unreference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
+ intel_dpll_unreference_crtc(crtc, pll, &dpll_state[pll->index]);
}
static void intel_put_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f497a9ec863d..8b596a96344f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -404,7 +404,7 @@ int intel_reserve_dplls(struct intel_atomic_state *state,
struct intel_encoder *encoder);
void intel_release_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc);
-void intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
+void intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
const struct intel_dpll *pll,
struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index ed4f305e0d3e..ee156cf2c5ce 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -93,7 +93,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
crtc->base.enabled = false;
if (crtc_state->intel_dpll)
- intel_unreference_dpll_crtc(crtc,
+ intel_dpll_unreference_crtc(crtc,
crtc_state->intel_dpll,
&crtc_state->intel_dpll->state);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 15/18] drm/i915/dpll: Rename intel_unreference_dpll__crtc
2025-05-09 4:27 ` [PATCH 15/18] drm/i915/dpll: Rename intel_unreference_dpll__crtc Suraj Kandpal
@ 2025-05-09 10:31 ` Jani Nikula
2025-05-12 4:27 ` Kandpal, Suraj
0 siblings, 1 reply; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:31 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_unreference_dpll_crtc to intel_dpll_unreference_crtc
> in an effort to keep names of exported functions start with the filename.
That's a fine goal, but to me "intel dpll unreference crtc" means drop
the crtc reference from dpll, not the other way round as it is...
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
> drivers/gpu/drm/i915/display/intel_modeset_setup.c | 2 +-
> 3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index d1399ab24d8c..c954515145a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -458,7 +458,7 @@ intel_reference_dpll(struct intel_atomic_state *state,
> }
>
> /**
> - * intel_unreference_dpll_crtc - Drop a DPLL reference for a CRTC
> + * intel_dpll_unreference_crtc - Drop a DPLL reference for a CRTC
> * @crtc: CRTC on which behalf the reference is dropped
> * @pll: DPLL for which the reference is dropped
> * @dpll_state: the DPLL atomic state in which the reference is tracked
> @@ -466,7 +466,7 @@ intel_reference_dpll(struct intel_atomic_state *state,
> * Drop a reference for @pll tracking the end of use of it by @crtc.
> */
> void
> -intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
> +intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
> const struct intel_dpll *pll,
> struct intel_dpll_state *dpll_state)
> {
> @@ -488,7 +488,7 @@ static void intel_unreference_dpll(struct intel_atomic_state *state,
>
> dpll_state = intel_atomic_get_dpll_state(&state->base);
>
> - intel_unreference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> + intel_dpll_unreference_crtc(crtc, pll, &dpll_state[pll->index]);
> }
>
> static void intel_put_dpll(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index f497a9ec863d..8b596a96344f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -404,7 +404,7 @@ int intel_reserve_dplls(struct intel_atomic_state *state,
> struct intel_encoder *encoder);
> void intel_release_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> -void intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
> +void intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
> const struct intel_dpll *pll,
> struct intel_dpll_state *shared_dpll_state);
> void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index ed4f305e0d3e..ee156cf2c5ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -93,7 +93,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
> crtc->base.enabled = false;
>
> if (crtc_state->intel_dpll)
> - intel_unreference_dpll_crtc(crtc,
> + intel_dpll_unreference_crtc(crtc,
> crtc_state->intel_dpll,
> &crtc_state->intel_dpll->state);
> }
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread* RE: [PATCH 15/18] drm/i915/dpll: Rename intel_unreference_dpll__crtc
2025-05-09 10:31 ` Jani Nikula
@ 2025-05-12 4:27 ` Kandpal, Suraj
0 siblings, 0 replies; 42+ messages in thread
From: Kandpal, Suraj @ 2025-05-12 4:27 UTC (permalink / raw)
To: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Murthy, Arun R
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, May 9, 2025 4:02 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 15/18] drm/i915/dpll: Rename intel_unreference_dpll__crtc
>
> On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Rename intel_unreference_dpll_crtc to intel_dpll_unreference_crtc in
> > an effort to keep names of exported functions start with the filename.
>
> That's a fine goal, but to me "intel dpll unreference crtc" means drop the crtc
> reference from dpll, not the other way round as it is...
Some suggestions for alternatives?
Intel_dpll_crtc_drop
Intel_dpll_crtc_put
I can update the intel_referece_dpll_crtc to intel_dpll_crtc_get
Regards,
Suraj Kandpal
>
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 +++---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
> > drivers/gpu/drm/i915/display/intel_modeset_setup.c | 2 +-
> > 3 files changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index d1399ab24d8c..c954515145a3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -458,7 +458,7 @@ intel_reference_dpll(struct intel_atomic_state
> > *state, }
> >
> > /**
> > - * intel_unreference_dpll_crtc - Drop a DPLL reference for a CRTC
> > + * intel_dpll_unreference_crtc - Drop a DPLL reference for a CRTC
> > * @crtc: CRTC on which behalf the reference is dropped
> > * @pll: DPLL for which the reference is dropped
> > * @dpll_state: the DPLL atomic state in which the reference is
> > tracked @@ -466,7 +466,7 @@ intel_reference_dpll(struct intel_atomic_state
> *state,
> > * Drop a reference for @pll tracking the end of use of it by @crtc.
> > */
> > void
> > -intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
> > +intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
> > const struct intel_dpll *pll,
> > struct intel_dpll_state *dpll_state) { @@ -488,7
> +488,7 @@
> > static void intel_unreference_dpll(struct intel_atomic_state *state,
> >
> > dpll_state = intel_atomic_get_dpll_state(&state->base);
> >
> > - intel_unreference_dpll_crtc(crtc, pll, &dpll_state[pll->index]);
> > + intel_dpll_unreference_crtc(crtc, pll, &dpll_state[pll->index]);
> > }
> >
> > static void intel_put_dpll(struct intel_atomic_state *state, diff
> > --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index f497a9ec863d..8b596a96344f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -404,7 +404,7 @@ int intel_reserve_dplls(struct intel_atomic_state
> *state,
> > struct intel_encoder *encoder);
> > void intel_release_dplls(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
> > -void intel_unreference_dpll_crtc(const struct intel_crtc *crtc,
> > +void intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
> > const struct intel_dpll *pll,
> > struct intel_dpll_state *shared_dpll_state);
> void
> > icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, diff
> > --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index ed4f305e0d3e..ee156cf2c5ce 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -93,7 +93,7 @@ static void intel_crtc_disable_noatomic_begin(struct
> intel_crtc *crtc,
> > crtc->base.enabled = false;
> >
> > if (crtc_state->intel_dpll)
> > - intel_unreference_dpll_crtc(crtc,
> > + intel_dpll_unreference_crtc(crtc,
> > crtc_state->intel_dpll,
> > &crtc_state->intel_dpll->state); }
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 16/18] drm/i915/dpll: Rename intel_<release/reserve>_dpll
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (14 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 15/18] drm/i915/dpll: Rename intel_unreference_dpll__crtc Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:32 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 17/18] drm/i915/dpll: Rename intel_compute_dpll Suraj Kandpal
2025-05-09 4:27 ` [PATCH 18/18] drm/i915/dpll: Rename intel_update_active_dpll Suraj Kandpal
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename intel_<release/reserve>_dpll to
intel_dpll_<release/reserve> in an effort to keep names of
exported functions start with the filename.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 4 +--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 26 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 10 +++----
4 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8ee4833daede..d26c2fd201dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6434,7 +6434,7 @@ int intel_atomic_check(struct drm_device *dev,
any_ms = true;
- intel_release_dplls(state, crtc);
+ intel_dpll_release(state, crtc);
}
if (any_ms && !check_digital_port_conflicts(state)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index e25411c4171c..6a0bb12eafc4 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1189,7 +1189,7 @@ static int hsw_crtc_get_dpll(struct intel_atomic_state *state,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- return intel_reserve_dplls(state, crtc, encoder);
+ return intel_dpll_reserve(state, crtc, encoder);
}
static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1414,7 +1414,7 @@ static int ilk_crtc_get_dpll(struct intel_atomic_state *state,
if (!crtc_state->has_pch_encoder)
return 0;
- return intel_reserve_dplls(state, crtc, NULL);
+ return intel_dpll_reserve(state, crtc, NULL);
}
static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c954515145a3..65dd8c3a3aed 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -56,8 +56,8 @@
* users of a PLL are tracked and that tracking is integrated with the atomic
* modset interface. During an atomic operation, required PLLs can be reserved
* for a given CRTC and encoder configuration by calling
- * intel_reserve_dplls() and previously reserved PLLs can be released
- * with intel_release_dplls().
+ * intel_dpll_reserve() and previously reserved PLLs can be released
+ * with intel_dpll_release().
* Changes to the users are first staged in the atomic state, and then made
* effective by calling intel_dpll_swap_state() during the atomic
* commit phase.
@@ -4410,7 +4410,7 @@ int intel_compute_dplls(struct intel_atomic_state *state,
}
/**
- * intel_reserve_dplls - reserve DPLLs for CRTC and encoder combination
+ * intel_dpll_reserve - reserve DPLLs for CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to reserve DPLLs for
* @encoder: encoder
@@ -4423,15 +4423,15 @@ int intel_compute_dplls(struct intel_atomic_state *state,
* calling intel_dpll_swap_state().
*
* The reserved DPLLs should be released by calling
- * intel_release_dplls().
+ * intel_dpll_release().
*
* Returns:
* 0 if all required DPLLs were successfully reserved,
* negative error code otherwise.
*/
-int intel_reserve_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+int intel_dpll_reserve(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(state);
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
@@ -4443,18 +4443,18 @@ int intel_reserve_dplls(struct intel_atomic_state *state,
}
/**
- * intel_release_dplls - end use of DPLLs by CRTC in atomic state
+ * intel_dpll_release - end use of DPLLs by CRTC in atomic state
* @state: atomic state
* @crtc: crtc from which the DPLLs are to be released
*
- * This function releases all DPLLs reserved by intel_reserve_dplls()
+ * This function releases all DPLLs reserved by intel_dpll_reserve()
* from the current atomic commit @state and the old @crtc atomic state.
*
* The new configuration in the atomic commit @state is made effective by
* calling intel_dpll_swap_state().
*/
-void intel_release_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+void intel_dpll_release(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
@@ -4462,7 +4462,7 @@ void intel_release_dplls(struct intel_atomic_state *state,
/*
* FIXME: this function is called for every platform having a
* compute_clock hook, even though the platform doesn't yet support
- * the global DPLL framework and intel_reserve_dplls() is not
+ * the global DPLL framework and intel_dpll_reserve() is not
* called on those.
*/
if (!dpll_mgr)
@@ -4478,7 +4478,7 @@ void intel_release_dplls(struct intel_atomic_state *state,
* @encoder: encoder determining the type of port DPLL
*
* Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
- * from the port DPLLs reserved previously by intel_reserve_dplls(). The
+ * from the port DPLLs reserved previously by intel_dpll_reserve(). The
* DPLL selected will be based on the current mode of the encoder's port.
*/
void intel_update_active_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 8b596a96344f..4f8074580582 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -399,11 +399,11 @@ void assert_dpll(struct intel_display *display,
int intel_compute_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
-int intel_reserve_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
-void intel_release_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
+int intel_dpll_reserve(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
+void intel_dpll_release(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
const struct intel_dpll *pll,
struct intel_dpll_state *shared_dpll_state);
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 16/18] drm/i915/dpll: Rename intel_<release/reserve>_dpll
2025-05-09 4:27 ` [PATCH 16/18] drm/i915/dpll: Rename intel_<release/reserve>_dpll Suraj Kandpal
@ 2025-05-09 10:32 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:32 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_<release/reserve>_dpll to
> intel_dpll_<release/reserve> in an effort to keep names of
> exported functions start with the filename.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll.c | 4 +--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 26 +++++++++----------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 10 +++----
> 4 files changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8ee4833daede..d26c2fd201dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6434,7 +6434,7 @@ int intel_atomic_check(struct drm_device *dev,
>
> any_ms = true;
>
> - intel_release_dplls(state, crtc);
> + intel_dpll_release(state, crtc);
> }
>
> if (any_ms && !check_digital_port_conflicts(state)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index e25411c4171c..6a0bb12eafc4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1189,7 +1189,7 @@ static int hsw_crtc_get_dpll(struct intel_atomic_state *state,
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
>
> - return intel_reserve_dplls(state, crtc, encoder);
> + return intel_dpll_reserve(state, crtc, encoder);
> }
>
> static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> @@ -1414,7 +1414,7 @@ static int ilk_crtc_get_dpll(struct intel_atomic_state *state,
> if (!crtc_state->has_pch_encoder)
> return 0;
>
> - return intel_reserve_dplls(state, crtc, NULL);
> + return intel_dpll_reserve(state, crtc, NULL);
> }
>
> static u32 vlv_dpll(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index c954515145a3..65dd8c3a3aed 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -56,8 +56,8 @@
> * users of a PLL are tracked and that tracking is integrated with the atomic
> * modset interface. During an atomic operation, required PLLs can be reserved
> * for a given CRTC and encoder configuration by calling
> - * intel_reserve_dplls() and previously reserved PLLs can be released
> - * with intel_release_dplls().
> + * intel_dpll_reserve() and previously reserved PLLs can be released
> + * with intel_dpll_release().
> * Changes to the users are first staged in the atomic state, and then made
> * effective by calling intel_dpll_swap_state() during the atomic
> * commit phase.
> @@ -4410,7 +4410,7 @@ int intel_compute_dplls(struct intel_atomic_state *state,
> }
>
> /**
> - * intel_reserve_dplls - reserve DPLLs for CRTC and encoder combination
> + * intel_dpll_reserve - reserve DPLLs for CRTC and encoder combination
> * @state: atomic state
> * @crtc: CRTC to reserve DPLLs for
> * @encoder: encoder
> @@ -4423,15 +4423,15 @@ int intel_compute_dplls(struct intel_atomic_state *state,
> * calling intel_dpll_swap_state().
> *
> * The reserved DPLLs should be released by calling
> - * intel_release_dplls().
> + * intel_dpll_release().
> *
> * Returns:
> * 0 if all required DPLLs were successfully reserved,
> * negative error code otherwise.
> */
> -int intel_reserve_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +int intel_dpll_reserve(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(state);
> const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
> @@ -4443,18 +4443,18 @@ int intel_reserve_dplls(struct intel_atomic_state *state,
> }
>
> /**
> - * intel_release_dplls - end use of DPLLs by CRTC in atomic state
> + * intel_dpll_release - end use of DPLLs by CRTC in atomic state
> * @state: atomic state
> * @crtc: crtc from which the DPLLs are to be released
> *
> - * This function releases all DPLLs reserved by intel_reserve_dplls()
> + * This function releases all DPLLs reserved by intel_dpll_reserve()
> * from the current atomic commit @state and the old @crtc atomic state.
> *
> * The new configuration in the atomic commit @state is made effective by
> * calling intel_dpll_swap_state().
> */
> -void intel_release_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +void intel_dpll_release(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
> @@ -4462,7 +4462,7 @@ void intel_release_dplls(struct intel_atomic_state *state,
> /*
> * FIXME: this function is called for every platform having a
> * compute_clock hook, even though the platform doesn't yet support
> - * the global DPLL framework and intel_reserve_dplls() is not
> + * the global DPLL framework and intel_dpll_reserve() is not
> * called on those.
> */
> if (!dpll_mgr)
> @@ -4478,7 +4478,7 @@ void intel_release_dplls(struct intel_atomic_state *state,
> * @encoder: encoder determining the type of port DPLL
> *
> * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
> - * from the port DPLLs reserved previously by intel_reserve_dplls(). The
> + * from the port DPLLs reserved previously by intel_dpll_reserve(). The
> * DPLL selected will be based on the current mode of the encoder's port.
> */
> void intel_update_active_dpll(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 8b596a96344f..4f8074580582 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -399,11 +399,11 @@ void assert_dpll(struct intel_display *display,
> int intel_compute_dplls(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> -int intel_reserve_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder);
> -void intel_release_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> +int intel_dpll_reserve(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder);
> +void intel_dpll_release(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> void intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
> const struct intel_dpll *pll,
> struct intel_dpll_state *shared_dpll_state);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 17/18] drm/i915/dpll: Rename intel_compute_dpll
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (15 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 16/18] drm/i915/dpll: Rename intel_<release/reserve>_dpll Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:33 ` Jani Nikula
2025-05-09 4:27 ` [PATCH 18/18] drm/i915/dpll: Rename intel_update_active_dpll Suraj Kandpal
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename intel_compute_dpll to intel_dpll_compute in an
effort to make sure all function names that are exported have
the filename at start.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +++---
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 6a0bb12eafc4..c15a9af53313 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1161,7 +1161,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- ret = intel_compute_dplls(state, crtc, encoder);
+ ret = intel_dpll_compute(state, crtc, encoder);
if (ret)
return ret;
@@ -1223,7 +1223,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
if (ret)
return ret;
- /* TODO: Do the readback via intel_compute_dplls() */
+ /* TODO: Do the readback via intel_dpll_compute() */
crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
@@ -1394,7 +1394,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
- ret = intel_compute_dplls(state, crtc, NULL);
+ ret = intel_dpll_compute(state, crtc, NULL);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 65dd8c3a3aed..05714e6fbad5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4383,7 +4383,7 @@ void intel_dpll_init(struct intel_display *display)
}
/**
- * intel_compute_dplls - compute DPLL state CRTC and encoder combination
+ * intel_dpll_compute - compute DPLL state CRTC and encoder combination
* @state: atomic state
* @crtc: CRTC to compute DPLLs for
* @encoder: encoder
@@ -4396,9 +4396,9 @@ void intel_dpll_init(struct intel_display *display)
* Returns:
* 0 on success, negative error code on failure.
*/
-int intel_compute_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder)
+int intel_dpll_compute(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(state);
const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 4f8074580582..c2658ad409e4 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -396,9 +396,9 @@ void assert_dpll(struct intel_display *display,
bool state);
#define assert_dpll_enabled(d, p) assert_dpll(d, p, true)
#define assert_dpll_disabled(d, p) assert_dpll(d, p, false)
-int intel_compute_dplls(struct intel_atomic_state *state,
- struct intel_crtc *crtc,
- struct intel_encoder *encoder);
+int intel_dpll_compute(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_encoder *encoder);
int intel_dpll_reserve(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 17/18] drm/i915/dpll: Rename intel_compute_dpll
2025-05-09 4:27 ` [PATCH 17/18] drm/i915/dpll: Rename intel_compute_dpll Suraj Kandpal
@ 2025-05-09 10:33 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:33 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_compute_dpll to intel_dpll_compute in an
> effort to make sure all function names that are exported have
> the filename at start.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++----
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 +++---
> 3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 6a0bb12eafc4..c15a9af53313 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1161,7 +1161,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> return 0;
>
> - ret = intel_compute_dplls(state, crtc, encoder);
> + ret = intel_dpll_compute(state, crtc, encoder);
> if (ret)
> return ret;
>
> @@ -1223,7 +1223,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> - /* TODO: Do the readback via intel_compute_dplls() */
> + /* TODO: Do the readback via intel_dpll_compute() */
> crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
>
> crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> @@ -1394,7 +1394,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> ilk_compute_dpll(crtc_state, &crtc_state->dpll,
> &crtc_state->dpll);
>
> - ret = intel_compute_dplls(state, crtc, NULL);
> + ret = intel_dpll_compute(state, crtc, NULL);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 65dd8c3a3aed..05714e6fbad5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4383,7 +4383,7 @@ void intel_dpll_init(struct intel_display *display)
> }
>
> /**
> - * intel_compute_dplls - compute DPLL state CRTC and encoder combination
> + * intel_dpll_compute - compute DPLL state CRTC and encoder combination
> * @state: atomic state
> * @crtc: CRTC to compute DPLLs for
> * @encoder: encoder
> @@ -4396,9 +4396,9 @@ void intel_dpll_init(struct intel_display *display)
> * Returns:
> * 0 on success, negative error code on failure.
> */
> -int intel_compute_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder)
> +int intel_dpll_compute(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(state);
> const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 4f8074580582..c2658ad409e4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -396,9 +396,9 @@ void assert_dpll(struct intel_display *display,
> bool state);
> #define assert_dpll_enabled(d, p) assert_dpll(d, p, true)
> #define assert_dpll_disabled(d, p) assert_dpll(d, p, false)
> -int intel_compute_dplls(struct intel_atomic_state *state,
> - struct intel_crtc *crtc,
> - struct intel_encoder *encoder);
> +int intel_dpll_compute(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_encoder *encoder);
> int intel_dpll_reserve(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH 18/18] drm/i915/dpll: Rename intel_update_active_dpll
2025-05-09 4:27 [PATCH 00/18] DPLL framework redesign Suraj Kandpal
` (16 preceding siblings ...)
2025-05-09 4:27 ` [PATCH 17/18] drm/i915/dpll: Rename intel_compute_dpll Suraj Kandpal
@ 2025-05-09 4:27 ` Suraj Kandpal
2025-05-09 10:33 ` Jani Nikula
17 siblings, 1 reply; 42+ messages in thread
From: Suraj Kandpal @ 2025-05-09 4:27 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
Rename intel_update_active_dpll to intel_dpll_update_active in an
effort to have function names which are exported to start with
filenames they are exported from.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 66dea34ebcd3..be26e6b4bc97 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3650,7 +3650,7 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
intel_crtc_joined_pipe_mask(crtc_state))
- intel_update_active_dpll(state, pipe_crtc, encoder);
+ intel_dpll_update_active(state, pipe_crtc, encoder);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 05714e6fbad5..939d92b4cf0f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4472,7 +4472,7 @@ void intel_dpll_release(struct intel_atomic_state *state,
}
/**
- * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
+ * intel_dpll_update_active - update the active DPLL for a CRTC/encoder
* @state: atomic state
* @crtc: the CRTC for which to update the active DPLL
* @encoder: encoder determining the type of port DPLL
@@ -4481,7 +4481,7 @@ void intel_dpll_release(struct intel_atomic_state *state,
* from the port DPLLs reserved previously by intel_dpll_reserve(). The
* DPLL selected will be based on the current mode of the encoder's port.
*/
-void intel_update_active_dpll(struct intel_atomic_state *state,
+void intel_dpll_update_active(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index c2658ad409e4..821ffcc4b8d0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -409,7 +409,7 @@ void intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
struct intel_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
enum icl_port_dpll_id port_dpll_id);
-void intel_update_active_dpll(struct intel_atomic_state *state,
+void intel_dpll_update_active(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_encoder *encoder);
int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH 18/18] drm/i915/dpll: Rename intel_update_active_dpll
2025-05-09 4:27 ` [PATCH 18/18] drm/i915/dpll: Rename intel_update_active_dpll Suraj Kandpal
@ 2025-05-09 10:33 ` Jani Nikula
0 siblings, 0 replies; 42+ messages in thread
From: Jani Nikula @ 2025-05-09 10:33 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, arun.r.murthy, Suraj Kandpal
On Fri, 09 May 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Rename intel_update_active_dpll to intel_dpll_update_active in an
> effort to have function names which are exported to start with
> filenames they are exported from.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +-
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 66dea34ebcd3..be26e6b4bc97 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3650,7 +3650,7 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
>
> for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
> intel_crtc_joined_pipe_mask(crtc_state))
> - intel_update_active_dpll(state, pipe_crtc, encoder);
> + intel_dpll_update_active(state, pipe_crtc, encoder);
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 05714e6fbad5..939d92b4cf0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4472,7 +4472,7 @@ void intel_dpll_release(struct intel_atomic_state *state,
> }
>
> /**
> - * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
> + * intel_dpll_update_active - update the active DPLL for a CRTC/encoder
> * @state: atomic state
> * @crtc: the CRTC for which to update the active DPLL
> * @encoder: encoder determining the type of port DPLL
> @@ -4481,7 +4481,7 @@ void intel_dpll_release(struct intel_atomic_state *state,
> * from the port DPLLs reserved previously by intel_dpll_reserve(). The
> * DPLL selected will be based on the current mode of the encoder's port.
> */
> -void intel_update_active_dpll(struct intel_atomic_state *state,
> +void intel_dpll_update_active(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index c2658ad409e4..821ffcc4b8d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -409,7 +409,7 @@ void intel_dpll_unreference_crtc(const struct intel_crtc *crtc,
> struct intel_dpll_state *shared_dpll_state);
> void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
> enum icl_port_dpll_id port_dpll_id);
> -void intel_update_active_dpll(struct intel_atomic_state *state,
> +void intel_dpll_update_active(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> int intel_dpll_get_freq(struct intel_crtc_state *crtc_state,
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 42+ messages in thread