From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Murthy, Arun R" <arun.r.murthy@intel.com>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: RE: [PATCH] drm/i915/display: BMG supports UHBR13.5
Date: Tue, 27 Aug 2024 11:08:58 +0300 [thread overview]
Message-ID: <874j761j6t.fsf@intel.com> (raw)
In-Reply-To: <IA0PR11MB7307E3C377E8F3725937B7B2BA942@IA0PR11MB7307.namprd11.prod.outlook.com>
On Tue, 27 Aug 2024, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@linux.intel.com>
>> Sent: Tuesday, August 27, 2024 1:11 PM
>> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-xe@lists.freedesktop.org;
>> intel-gfx@lists.freedesktop.org
>> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
>> Subject: Re: [PATCH] drm/i915/display: BMG supports UHBR13.5
>>
>> On Tue, 27 Aug 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> > UHBR20 is not supported by battlemage and the maximum link rate
>> > supported is UHBR13.5
>> >
>> > HSD: 16023263677
>> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
>> > 1 file changed, 11 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 789c2f78826d..3232ec4b2889 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -528,6 +528,10 @@ static void
>> > intel_dp_set_source_rates(struct intel_dp *intel_dp) {
>> > /* The values must be in increasing order */
>> > + static const int bmg_rates[] = {
>> > + 162000, 216000, 243000, 270000, 324000, 432000, 540000,
>> 675000,
>> > + 810000, 1000000, 1350000,
>> > + };
>> > static const int mtl_rates[] = {
>> > 162000, 216000, 243000, 270000, 324000, 432000, 540000,
>> 675000,
>> > 810000, 1000000, 2000000,
>> > @@ -558,8 +562,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>> > intel_dp->source_rates || intel_dp->num_source_rates);
>> >
>> > if (DISPLAY_VER(dev_priv) >= 14) {
>> > - source_rates = mtl_rates;
>> > - size = ARRAY_SIZE(mtl_rates);
>> > + if (IS_DGFX(dev_priv)) {
>>
>> Why dgfx instead of bmg? Should be explained in commit message at the very
>> least.
>>
> Likewise IS_DH2 / IS_MTL we don't have IS_BMG as its Display 14.1. One of the way to differentiate this is DISPLAY < 14 are integrated and this BMG is discrete and hence using IS_DGFX() for identifying BMG platform.
But isn't dgfx completely incidental here?
>
> Will add this in the commit message if not other comments and get Rb on this patch.
>
> Thanks and Regards,
> Arun R Murthy
> -------------------
>
>> BR,
>> Jani.
>>
>> > + source_rates = bmg_rates;
>> > + size = ARRAY_SIZE(bmg_rates);
>> > + } else {
>> > + source_rates = mtl_rates;
>> > + size = ARRAY_SIZE(mtl_rates);
>> > + }
>> > max_rate = mtl_max_source_rate(intel_dp);
>> > } else if (DISPLAY_VER(dev_priv) >= 11) {
>> > source_rates = icl_rates;
>>
>> --
>> Jani Nikula, Intel
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-08-27 8:09 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-27 6:40 [PATCH] drm/i915/display: BMG supports UHBR13.5 Arun R Murthy
2024-08-27 6:55 ` ✓ CI.Patch_applied: success for " Patchwork
2024-08-27 6:56 ` ✓ CI.checkpatch: " Patchwork
2024-08-27 6:57 ` ✓ CI.KUnit: " Patchwork
2024-08-27 7:08 ` ✗ CI.Build: failure " Patchwork
2024-08-27 7:40 ` [PATCH] " Jani Nikula
2024-08-27 7:54 ` Murthy, Arun R
2024-08-27 8:08 ` Jani Nikula [this message]
2024-08-27 8:10 ` Jani Nikula
2024-08-27 8:23 ` Murthy, Arun R
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