From: Jani Nikula <jani.nikula@linux.intel.com>
To: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Matt Roper <matthew.d.roper@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Subject: Re: [PATCH v2 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR
Date: Wed, 03 Apr 2024 14:53:57 +0300 [thread overview]
Message-ID: <874jciek6i.fsf@intel.com> (raw)
In-Reply-To: <20240403112253.1432390-17-balasubramani.vivekanandan@intel.com>
On Wed, 03 Apr 2024, Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> wrote:
> Defined a new DRAM type to be used in the following patches.
> The following patch first makes use of this new type in the i915
> display. So without this define, build would fail when the shared
> display code is built for Xe.
Just make it part of that patch I think.
>
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 1df3dcc17d75..e7aa2dd3df8d 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -480,6 +480,7 @@ struct xe_device {
> INTEL_DRAM_LPDDR4,
> INTEL_DRAM_DDR5,
> INTEL_DRAM_LPDDR5,
> + INTEL_DRAM_GDDR,
> } type;
> u8 num_qgv_points;
> u8 num_psf_gv_points;
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-04-03 11:54 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-03 11:22 [PATCH v2 00/25] Enable dislay support for Battlemage Balasubramani Vivekanandan
2024-04-03 11:22 ` [PATCH v2 01/25] drm/i915/display: Prepare to handle new C20 PLL register address Balasubramani Vivekanandan
2024-04-03 11:40 ` Jani Nikula
2024-04-03 11:22 ` [PATCH v2 02/25] drm/xe/bmg: Add BMG platform definition Balasubramani Vivekanandan
2024-04-03 13:16 ` Lucas De Marchi
2024-04-03 11:22 ` [PATCH v2 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro Balasubramani Vivekanandan
2024-04-03 18:05 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 04/25] drm/i915/bmg: " Balasubramani Vivekanandan
2024-04-03 18:11 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms Balasubramani Vivekanandan
2024-04-03 19:02 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 06/25] drm/i915/xe2hpd: Initial cdclk table Balasubramani Vivekanandan
2024-04-03 19:05 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Balasubramani Vivekanandan
2024-04-03 19:14 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 08/25] drm/i915/bmg: Extend DG2 tc check to future Balasubramani Vivekanandan
2024-04-03 19:15 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 09/25] drm/i915/xe2hpd: Properly disable power in port A Balasubramani Vivekanandan
2024-04-03 19:28 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 10/25] drm/i915/xe2hpd: Add new C20 PLL register address Balasubramani Vivekanandan
2024-04-03 12:00 ` Jani Nikula
2024-04-03 11:22 ` [PATCH v2 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration Balasubramani Vivekanandan
2024-04-03 20:11 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec Balasubramani Vivekanandan
2024-04-03 20:41 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 13/25] drm/i915/xe2hpd: Add display info Balasubramani Vivekanandan
2024-04-03 21:12 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming Balasubramani Vivekanandan
2024-04-03 21:00 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 15/25] drm/xe/display: Lane reversal requires writes to both context lanes Balasubramani Vivekanandan
2024-04-03 11:52 ` Jani Nikula
2024-04-03 11:22 ` [PATCH v2 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR Balasubramani Vivekanandan
2024-04-03 11:53 ` Jani Nikula [this message]
2024-04-03 11:22 ` [PATCH v2 17/25] drm/i915/xe2hpd: Add max memory bandwidth algorithm Balasubramani Vivekanandan
2024-04-03 11:22 ` [PATCH v2 18/25] drm/i915/display: Enable RM timeout detection Balasubramani Vivekanandan
2024-04-03 11:57 ` Jani Nikula
2024-04-03 18:02 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits Balasubramani Vivekanandan
2024-04-03 21:20 ` Matt Roper
2024-04-03 11:22 ` [PATCH v2 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic Balasubramani Vivekanandan
2024-04-08 13:00 ` Bhadane, Dnyaneshwar
2024-04-03 11:22 ` [PATCH v2 21/25] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 Balasubramani Vivekanandan
2024-04-08 3:22 ` Chauhan, Shekhar
2024-04-03 11:22 ` [PATCH v2 22/25] drm/xe/gt_print: add xe_gt_err_once() Balasubramani Vivekanandan
2024-04-03 12:07 ` Nirmoy Das
2024-04-03 11:22 ` [PATCH v2 23/25] drm/xe/device: implement transient flush Balasubramani Vivekanandan
2024-04-03 12:13 ` Nirmoy Das
2024-04-03 11:22 ` [PATCH v2 24/25] drm/i915/display: perform " Balasubramani Vivekanandan
2024-04-03 12:15 ` Nirmoy Das
2024-04-03 11:22 ` [PATCH v2 25/25] drm/xe/bmg: Enable the display support Balasubramani Vivekanandan
2024-04-08 3:16 ` Chauhan, Shekhar
2024-04-08 6:23 ` Vivekanandan, Balasubramani
2024-04-03 11:29 ` ✓ CI.Patch_applied: success for Enable dislay support for Battlemage (rev2) Patchwork
2024-04-03 11:30 ` ✗ CI.checkpatch: warning " Patchwork
2024-04-03 11:31 ` ✓ CI.KUnit: success " Patchwork
2024-04-03 11:42 ` ✓ CI.Build: " Patchwork
2024-04-03 12:00 ` ✓ CI.Hooks: " Patchwork
2024-04-03 12:01 ` ✗ CI.checksparse: warning " Patchwork
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