* [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
@ 2026-03-16 17:58 Harish Chegondi
2026-03-16 22:04 ` ✓ CI.KUnit: success for series starting with [v2,1/1] " Patchwork
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Harish Chegondi @ 2026-03-16 17:58 UTC (permalink / raw)
To: intel-xe
Cc: felix.j.degrood, matias.a.cabral, joshua.santosh.ranjan,
Harish Chegondi, Ashutosh Dixit
If a reset (GT or engine) happens during EU stall data sampling, all the
EU stall registers can get reset to 0. This will result in EU stall data
buffers' read and write pointer register values to be out of sync with
the cached values. This will result in read() returning invalid data. To
prevent this, check the value of a EU stall base register. If it is zero,
it indicates a reset may have happened that wiped the register to zero.
If this happens, return EBADFD from read() upon which the user space
should close the fd and open a new fd for a new EU stall data
collection session.
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
---
v2: Move base register check from read to the poll function
drivers/gpu/drm/xe/xe_eu_stall.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index c34408cfd292..7e14de73a2c9 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -44,6 +44,7 @@ struct per_xecore_buf {
struct xe_eu_stall_data_stream {
bool pollin;
bool enabled;
+ bool reset_detected;
int wait_num_reports;
int sampling_rate_mult;
wait_queue_head_t poll_wq;
@@ -428,6 +429,17 @@ static bool eu_stall_data_buf_poll(struct xe_eu_stall_data_stream *stream)
set_bit(xecore, stream->data_drop.mask);
xecore_buf->write = write_ptr;
}
+ /* If a GT or engine reset happens during EU stall sampling,
+ * all EU stall registers get reset to 0 and the cached values of
+ * the EU stall data buffers' read pointers are out of sync with
+ * the register values. This causes invalid data to be returned
+ * from read(). To prevent this, check the value of a EU stall base
+ * register. If it is zero, there has been a reset.
+ */
+ if (unlikely(!xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE))) {
+ stream->reset_detected = true;
+ min_data_present = true;
+ }
mutex_unlock(&stream->xecore_buf_lock);
return min_data_present;
@@ -554,6 +566,15 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
}
stream->data_drop.reported_to_user = false;
}
+ /* If EU stall registers got reset due to a GT/engine reset,
+ * continuing with the read() will return invalid data to
+ * the user space. Just return -EBADFD instead.
+ */
+ if (unlikely(stream->reset_detected)) {
+ xe_gt_dbg(gt, "EU stall base register has been reset\n");
+ mutex_unlock(&stream->xecore_buf_lock);
+ return -EBADFD;
+ }
for_each_dss_steering(xecore, gt, group, instance) {
ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size,
@@ -692,6 +713,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
xecore_buf->write = write_ptr;
xecore_buf->read = write_ptr;
}
+ stream->reset_detected = false;
stream->data_drop.reported_to_user = false;
bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
@@ -717,7 +739,7 @@ static void eu_stall_data_buf_poll_work_fn(struct work_struct *work)
container_of(work, typeof(*stream), buf_poll_work.work);
struct xe_gt *gt = stream->gt;
- if (eu_stall_data_buf_poll(stream)) {
+ if (stream->reset_detected || eu_stall_data_buf_poll(stream)) {
stream->pollin = true;
wake_up(&stream->poll_wq);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✓ CI.KUnit: success for series starting with [v2,1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-16 17:58 [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset Harish Chegondi
@ 2026-03-16 22:04 ` Patchwork
2026-03-16 22:51 ` ✓ Xe.CI.BAT: " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-03-16 22:04 UTC (permalink / raw)
To: Harish Chegondi; +Cc: intel-xe
== Series Details ==
Series: series starting with [v2,1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
URL : https://patchwork.freedesktop.org/series/163306/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[22:03:23] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:03:27] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:03:58] Starting KUnit Kernel (1/1)...
[22:03:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:03:58] ================== guc_buf (11 subtests) ===================
[22:03:58] [PASSED] test_smallest
[22:03:58] [PASSED] test_largest
[22:03:58] [PASSED] test_granular
[22:03:58] [PASSED] test_unique
[22:03:58] [PASSED] test_overlap
[22:03:58] [PASSED] test_reusable
[22:03:58] [PASSED] test_too_big
[22:03:58] [PASSED] test_flush
[22:03:58] [PASSED] test_lookup
[22:03:58] [PASSED] test_data
[22:03:58] [PASSED] test_class
[22:03:58] ===================== [PASSED] guc_buf =====================
[22:03:58] =================== guc_dbm (7 subtests) ===================
[22:03:58] [PASSED] test_empty
[22:03:58] [PASSED] test_default
[22:03:58] ======================== test_size ========================
[22:03:58] [PASSED] 4
[22:03:58] [PASSED] 8
[22:03:58] [PASSED] 32
[22:03:58] [PASSED] 256
[22:03:58] ==================== [PASSED] test_size ====================
[22:03:58] ======================= test_reuse ========================
[22:03:58] [PASSED] 4
[22:03:58] [PASSED] 8
[22:03:58] [PASSED] 32
[22:03:58] [PASSED] 256
[22:03:58] =================== [PASSED] test_reuse ====================
[22:03:58] =================== test_range_overlap ====================
[22:03:58] [PASSED] 4
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[22:03:58] [PASSED] 32
[22:03:58] [PASSED] 256
[22:03:58] =============== [PASSED] test_range_overlap ================
[22:03:58] =================== test_range_compact ====================
[22:03:58] [PASSED] 4
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[22:03:58] [PASSED] 256
[22:03:58] =============== [PASSED] test_range_compact ================
[22:03:58] ==================== test_range_spare =====================
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[22:03:58] ================ [PASSED] test_range_spare =================
[22:03:58] ===================== [PASSED] guc_dbm =====================
[22:03:58] =================== guc_idm (6 subtests) ===================
[22:03:58] [PASSED] bad_init
[22:03:58] [PASSED] no_init
[22:03:58] [PASSED] init_fini
[22:03:58] [PASSED] check_used
[22:03:58] [PASSED] check_quota
[22:03:58] [PASSED] check_all
[22:03:58] ===================== [PASSED] guc_idm =====================
[22:03:58] ================== no_relay (3 subtests) ===================
[22:03:58] [PASSED] xe_drops_guc2pf_if_not_ready
[22:03:58] [PASSED] xe_drops_guc2vf_if_not_ready
[22:03:58] [PASSED] xe_rejects_send_if_not_ready
[22:03:58] ==================== [PASSED] no_relay =====================
[22:03:58] ================== pf_relay (14 subtests) ==================
[22:03:58] [PASSED] pf_rejects_guc2pf_too_short
[22:03:58] [PASSED] pf_rejects_guc2pf_too_long
[22:03:58] [PASSED] pf_rejects_guc2pf_no_payload
[22:03:58] [PASSED] pf_fails_no_payload
[22:03:58] [PASSED] pf_fails_bad_origin
[22:03:58] [PASSED] pf_fails_bad_type
[22:03:58] [PASSED] pf_txn_reports_error
[22:03:58] [PASSED] pf_txn_sends_pf2guc
[22:03:58] [PASSED] pf_sends_pf2guc
[22:03:58] [SKIPPED] pf_loopback_nop
[22:03:58] [SKIPPED] pf_loopback_echo
[22:03:58] [SKIPPED] pf_loopback_fail
[22:03:58] [SKIPPED] pf_loopback_busy
[22:03:58] [SKIPPED] pf_loopback_retry
[22:03:58] ==================== [PASSED] pf_relay =====================
[22:03:58] ================== vf_relay (3 subtests) ===================
[22:03:58] [PASSED] vf_rejects_guc2vf_too_short
[22:03:58] [PASSED] vf_rejects_guc2vf_too_long
[22:03:58] [PASSED] vf_rejects_guc2vf_no_payload
[22:03:58] ==================== [PASSED] vf_relay =====================
[22:03:58] ================ pf_gt_config (9 subtests) =================
[22:03:58] [PASSED] fair_contexts_1vf
[22:03:58] [PASSED] fair_doorbells_1vf
[22:03:58] [PASSED] fair_ggtt_1vf
[22:03:58] ====================== fair_vram_1vf ======================
[22:03:58] [PASSED] 3.50 GiB
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[22:03:58] [PASSED] 63.5 GiB
[22:03:58] [PASSED] 1.91 GiB
[22:03:58] ================== [PASSED] fair_vram_1vf ==================
[22:03:58] ================ fair_vram_1vf_admin_only =================
[22:03:58] [PASSED] 3.50 GiB
[22:03:58] [PASSED] 11.5 GiB
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[22:03:58] [PASSED] 1.91 GiB
[22:03:58] ============ [PASSED] fair_vram_1vf_admin_only =============
[22:03:58] ====================== fair_contexts ======================
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[22:03:58] ================== [PASSED] fair_contexts ==================
[22:03:58] ===================== fair_doorbells ======================
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[22:03:58] ================= [PASSED] fair_doorbells ==================
[22:03:58] ======================== fair_ggtt ========================
[22:03:58] [PASSED] 1 VF
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[22:03:58] ==================== [PASSED] fair_ggtt ====================
[22:03:58] ======================== fair_vram ========================
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[22:03:58] ==================== [PASSED] fair_vram ====================
[22:03:58] ================== [PASSED] pf_gt_config ===================
[22:03:58] ===================== lmtt (1 subtest) =====================
[22:03:58] ======================== test_ops =========================
[22:03:58] [PASSED] 2-level
[22:03:58] [PASSED] multi-level
[22:03:58] ==================== [PASSED] test_ops =====================
[22:03:58] ====================== [PASSED] lmtt =======================
[22:03:58] ================= pf_service (11 subtests) =================
[22:03:58] [PASSED] pf_negotiate_any
[22:03:58] [PASSED] pf_negotiate_base_match
[22:03:58] [PASSED] pf_negotiate_base_newer
[22:03:58] [PASSED] pf_negotiate_base_next
[22:03:58] [SKIPPED] pf_negotiate_base_older
[22:03:58] [PASSED] pf_negotiate_base_prev
[22:03:58] [PASSED] pf_negotiate_latest_match
[22:03:58] [PASSED] pf_negotiate_latest_newer
[22:03:58] [PASSED] pf_negotiate_latest_next
[22:03:58] [SKIPPED] pf_negotiate_latest_older
[22:03:58] [SKIPPED] pf_negotiate_latest_prev
[22:03:58] =================== [PASSED] pf_service ====================
[22:03:58] ================= xe_guc_g2g (2 subtests) ==================
[22:03:58] ============== xe_live_guc_g2g_kunit_default ==============
[22:03:58] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[22:03:58] ============== xe_live_guc_g2g_kunit_allmem ===============
[22:03:58] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[22:03:58] =================== [SKIPPED] xe_guc_g2g ===================
[22:03:58] =================== xe_mocs (2 subtests) ===================
[22:03:58] ================ xe_live_mocs_kernel_kunit ================
[22:03:58] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[22:03:58] ================ xe_live_mocs_reset_kunit =================
[22:03:58] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[22:03:58] ==================== [SKIPPED] xe_mocs =====================
[22:03:58] ================= xe_migrate (2 subtests) ==================
[22:03:58] ================= xe_migrate_sanity_kunit =================
[22:03:58] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[22:03:58] ================== xe_validate_ccs_kunit ==================
[22:03:58] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[22:03:58] =================== [SKIPPED] xe_migrate ===================
[22:03:58] ================== xe_dma_buf (1 subtest) ==================
[22:03:58] ==================== xe_dma_buf_kunit =====================
[22:03:58] ================ [SKIPPED] xe_dma_buf_kunit ================
[22:03:58] =================== [SKIPPED] xe_dma_buf ===================
[22:03:58] ================= xe_bo_shrink (1 subtest) =================
[22:03:58] =================== xe_bo_shrink_kunit ====================
[22:03:58] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[22:03:58] ================== [SKIPPED] xe_bo_shrink ==================
[22:03:58] ==================== xe_bo (2 subtests) ====================
[22:03:58] ================== xe_ccs_migrate_kunit ===================
[22:03:58] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[22:03:58] ==================== xe_bo_evict_kunit ====================
[22:03:58] =============== [SKIPPED] xe_bo_evict_kunit ================
[22:03:58] ===================== [SKIPPED] xe_bo ======================
[22:03:58] ==================== args (13 subtests) ====================
[22:03:58] [PASSED] count_args_test
[22:03:58] [PASSED] call_args_example
[22:03:58] [PASSED] call_args_test
[22:03:58] [PASSED] drop_first_arg_example
[22:03:58] [PASSED] drop_first_arg_test
[22:03:58] [PASSED] first_arg_example
[22:03:58] [PASSED] first_arg_test
[22:03:58] [PASSED] last_arg_example
[22:03:58] [PASSED] last_arg_test
[22:03:58] [PASSED] pick_arg_example
[22:03:58] [PASSED] if_args_example
[22:03:58] [PASSED] if_args_test
[22:03:58] [PASSED] sep_comma_example
[22:03:58] ====================== [PASSED] args =======================
[22:03:58] =================== xe_pci (3 subtests) ====================
[22:03:58] ==================== check_graphics_ip ====================
[22:03:58] [PASSED] 12.00 Xe_LP
[22:03:58] [PASSED] 12.10 Xe_LP+
[22:03:58] [PASSED] 12.55 Xe_HPG
[22:03:58] [PASSED] 12.60 Xe_HPC
[22:03:58] [PASSED] 12.70 Xe_LPG
[22:03:58] [PASSED] 12.71 Xe_LPG
[22:03:58] [PASSED] 12.74 Xe_LPG+
[22:03:58] [PASSED] 20.01 Xe2_HPG
[22:03:58] [PASSED] 20.02 Xe2_HPG
[22:03:58] [PASSED] 20.04 Xe2_LPG
[22:03:58] [PASSED] 30.00 Xe3_LPG
[22:03:58] [PASSED] 30.01 Xe3_LPG
[22:03:58] [PASSED] 30.03 Xe3_LPG
[22:03:58] [PASSED] 30.04 Xe3_LPG
[22:03:58] [PASSED] 30.05 Xe3_LPG
[22:03:58] [PASSED] 35.10 Xe3p_LPG
[22:03:58] [PASSED] 35.11 Xe3p_XPC
[22:03:58] ================ [PASSED] check_graphics_ip ================
[22:03:58] ===================== check_media_ip ======================
[22:03:58] [PASSED] 12.00 Xe_M
[22:03:58] [PASSED] 12.55 Xe_HPM
[22:03:58] [PASSED] 13.00 Xe_LPM+
[22:03:58] [PASSED] 13.01 Xe2_HPM
[22:03:58] [PASSED] 20.00 Xe2_LPM
[22:03:58] [PASSED] 30.00 Xe3_LPM
[22:03:58] [PASSED] 30.02 Xe3_LPM
[22:03:58] [PASSED] 35.00 Xe3p_LPM
[22:03:58] [PASSED] 35.03 Xe3p_HPM
[22:03:58] ================= [PASSED] check_media_ip ==================
[22:03:58] =================== check_platform_desc ===================
[22:03:58] [PASSED] 0x9A60 (TIGERLAKE)
[22:03:58] [PASSED] 0x9A68 (TIGERLAKE)
[22:03:58] [PASSED] 0x9A70 (TIGERLAKE)
[22:03:58] [PASSED] 0x9A40 (TIGERLAKE)
[22:03:58] [PASSED] 0x9A49 (TIGERLAKE)
[22:03:58] [PASSED] 0x9A59 (TIGERLAKE)
[22:03:58] [PASSED] 0x9A78 (TIGERLAKE)
[22:03:58] [PASSED] 0x9AC0 (TIGERLAKE)
[22:03:58] [PASSED] 0x9AC9 (TIGERLAKE)
[22:03:58] [PASSED] 0x9AD9 (TIGERLAKE)
[22:03:58] [PASSED] 0x9AF8 (TIGERLAKE)
[22:03:58] [PASSED] 0x4C80 (ROCKETLAKE)
[22:03:58] [PASSED] 0x4C8A (ROCKETLAKE)
[22:03:58] [PASSED] 0x4C8B (ROCKETLAKE)
[22:03:58] [PASSED] 0x4C8C (ROCKETLAKE)
[22:03:58] [PASSED] 0x4C90 (ROCKETLAKE)
[22:03:58] [PASSED] 0x4C9A (ROCKETLAKE)
[22:03:58] [PASSED] 0x4680 (ALDERLAKE_S)
[22:03:58] [PASSED] 0x4682 (ALDERLAKE_S)
[22:03:58] [PASSED] 0x4688 (ALDERLAKE_S)
[22:03:58] [PASSED] 0x468A (ALDERLAKE_S)
[22:03:58] [PASSED] 0x468B (ALDERLAKE_S)
[22:03:58] [PASSED] 0x4690 (ALDERLAKE_S)
[22:03:58] [PASSED] 0x4692 (ALDERLAKE_S)
[22:03:58] [PASSED] 0x4693 (ALDERLAKE_S)
[22:03:58] [PASSED] 0x46A0 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46A1 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46A2 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46A3 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46A6 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46A8 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46AA (ALDERLAKE_P)
[22:03:58] [PASSED] 0x462A (ALDERLAKE_P)
[22:03:58] [PASSED] 0x4626 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x4628 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46B0 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46B1 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46B2 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46B3 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46C0 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46C1 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46C2 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46C3 (ALDERLAKE_P)
[22:03:58] [PASSED] 0x46D0 (ALDERLAKE_N)
[22:03:58] [PASSED] 0x46D1 (ALDERLAKE_N)
[22:03:58] [PASSED] 0x46D2 (ALDERLAKE_N)
[22:03:58] [PASSED] 0x46D3 (ALDERLAKE_N)
[22:03:58] [PASSED] 0x46D4 (ALDERLAKE_N)
[22:03:58] [PASSED] 0xA721 (ALDERLAKE_P)
[22:03:58] [PASSED] 0xA7A1 (ALDERLAKE_P)
[22:03:58] [PASSED] 0xA7A9 (ALDERLAKE_P)
[22:03:58] [PASSED] 0xA7AC (ALDERLAKE_P)
[22:03:58] [PASSED] 0xA7AD (ALDERLAKE_P)
[22:03:58] [PASSED] 0xA720 (ALDERLAKE_P)
[22:03:58] [PASSED] 0xA7A0 (ALDERLAKE_P)
[22:03:58] [PASSED] 0xA7A8 (ALDERLAKE_P)
[22:03:58] [PASSED] 0xA7AA (ALDERLAKE_P)
[22:03:58] [PASSED] 0xA7AB (ALDERLAKE_P)
[22:03:58] [PASSED] 0xA780 (ALDERLAKE_S)
[22:03:58] [PASSED] 0xA781 (ALDERLAKE_S)
[22:03:58] [PASSED] 0xA782 (ALDERLAKE_S)
[22:03:58] [PASSED] 0xA783 (ALDERLAKE_S)
[22:03:58] [PASSED] 0xA788 (ALDERLAKE_S)
[22:03:58] [PASSED] 0xA789 (ALDERLAKE_S)
[22:03:58] [PASSED] 0xA78A (ALDERLAKE_S)
[22:03:58] [PASSED] 0xA78B (ALDERLAKE_S)
[22:03:58] [PASSED] 0x4905 (DG1)
[22:03:58] [PASSED] 0x4906 (DG1)
[22:03:58] [PASSED] 0x4907 (DG1)
[22:03:58] [PASSED] 0x4908 (DG1)
[22:03:58] [PASSED] 0x4909 (DG1)
[22:03:58] [PASSED] 0x56C0 (DG2)
[22:03:58] [PASSED] 0x56C2 (DG2)
[22:03:58] [PASSED] 0x56C1 (DG2)
[22:03:58] [PASSED] 0x7D51 (METEORLAKE)
[22:03:58] [PASSED] 0x7DD1 (METEORLAKE)
[22:03:58] [PASSED] 0x7D41 (METEORLAKE)
[22:03:58] [PASSED] 0x7D67 (METEORLAKE)
[22:03:58] [PASSED] 0xB640 (METEORLAKE)
[22:03:58] [PASSED] 0x56A0 (DG2)
[22:03:58] [PASSED] 0x56A1 (DG2)
[22:03:58] [PASSED] 0x56A2 (DG2)
[22:03:58] [PASSED] 0x56BE (DG2)
[22:03:58] [PASSED] 0x56BF (DG2)
[22:03:58] [PASSED] 0x5690 (DG2)
[22:03:58] [PASSED] 0x5691 (DG2)
[22:03:58] [PASSED] 0x5692 (DG2)
[22:03:58] [PASSED] 0x56A5 (DG2)
[22:03:58] [PASSED] 0x56A6 (DG2)
[22:03:58] [PASSED] 0x56B0 (DG2)
[22:03:58] [PASSED] 0x56B1 (DG2)
[22:03:58] [PASSED] 0x56BA (DG2)
[22:03:58] [PASSED] 0x56BB (DG2)
[22:03:58] [PASSED] 0x56BC (DG2)
[22:03:58] [PASSED] 0x56BD (DG2)
[22:03:58] [PASSED] 0x5693 (DG2)
[22:03:58] [PASSED] 0x5694 (DG2)
[22:03:58] [PASSED] 0x5695 (DG2)
[22:03:58] [PASSED] 0x56A3 (DG2)
[22:03:58] [PASSED] 0x56A4 (DG2)
[22:03:58] [PASSED] 0x56B2 (DG2)
[22:03:58] [PASSED] 0x56B3 (DG2)
[22:03:58] [PASSED] 0x5696 (DG2)
[22:03:58] [PASSED] 0x5697 (DG2)
[22:03:58] [PASSED] 0xB69 (PVC)
[22:03:58] [PASSED] 0xB6E (PVC)
[22:03:58] [PASSED] 0xBD4 (PVC)
[22:03:58] [PASSED] 0xBD5 (PVC)
[22:03:58] [PASSED] 0xBD6 (PVC)
[22:03:58] [PASSED] 0xBD7 (PVC)
[22:03:58] [PASSED] 0xBD8 (PVC)
[22:03:58] [PASSED] 0xBD9 (PVC)
[22:03:58] [PASSED] 0xBDA (PVC)
[22:03:58] [PASSED] 0xBDB (PVC)
[22:03:58] [PASSED] 0xBE0 (PVC)
[22:03:58] [PASSED] 0xBE1 (PVC)
[22:03:58] [PASSED] 0xBE5 (PVC)
[22:03:58] [PASSED] 0x7D40 (METEORLAKE)
[22:03:58] [PASSED] 0x7D45 (METEORLAKE)
[22:03:58] [PASSED] 0x7D55 (METEORLAKE)
[22:03:58] [PASSED] 0x7D60 (METEORLAKE)
[22:03:58] [PASSED] 0x7DD5 (METEORLAKE)
[22:03:58] [PASSED] 0x6420 (LUNARLAKE)
[22:03:58] [PASSED] 0x64A0 (LUNARLAKE)
[22:03:58] [PASSED] 0x64B0 (LUNARLAKE)
[22:03:58] [PASSED] 0xE202 (BATTLEMAGE)
[22:03:58] [PASSED] 0xE209 (BATTLEMAGE)
[22:03:58] [PASSED] 0xE20B (BATTLEMAGE)
[22:03:58] [PASSED] 0xE20C (BATTLEMAGE)
[22:03:58] [PASSED] 0xE20D (BATTLEMAGE)
[22:03:58] [PASSED] 0xE210 (BATTLEMAGE)
[22:03:58] [PASSED] 0xE211 (BATTLEMAGE)
[22:03:58] [PASSED] 0xE212 (BATTLEMAGE)
[22:03:58] [PASSED] 0xE216 (BATTLEMAGE)
[22:03:58] [PASSED] 0xE220 (BATTLEMAGE)
[22:03:58] [PASSED] 0xE221 (BATTLEMAGE)
[22:03:58] [PASSED] 0xE222 (BATTLEMAGE)
[22:03:58] [PASSED] 0xE223 (BATTLEMAGE)
[22:03:58] [PASSED] 0xB080 (PANTHERLAKE)
[22:03:58] [PASSED] 0xB081 (PANTHERLAKE)
[22:03:58] [PASSED] 0xB082 (PANTHERLAKE)
[22:03:58] [PASSED] 0xB083 (PANTHERLAKE)
[22:03:58] [PASSED] 0xB084 (PANTHERLAKE)
[22:03:58] [PASSED] 0xB085 (PANTHERLAKE)
[22:03:58] [PASSED] 0xB086 (PANTHERLAKE)
[22:03:58] [PASSED] 0xB087 (PANTHERLAKE)
[22:03:58] [PASSED] 0xB08F (PANTHERLAKE)
[22:03:58] [PASSED] 0xB090 (PANTHERLAKE)
[22:03:58] [PASSED] 0xB0A0 (PANTHERLAKE)
[22:03:58] [PASSED] 0xB0B0 (PANTHERLAKE)
[22:03:58] [PASSED] 0xFD80 (PANTHERLAKE)
[22:03:58] [PASSED] 0xFD81 (PANTHERLAKE)
[22:03:58] [PASSED] 0xD740 (NOVALAKE_S)
[22:03:58] [PASSED] 0xD741 (NOVALAKE_S)
[22:03:58] [PASSED] 0xD742 (NOVALAKE_S)
[22:03:58] [PASSED] 0xD743 (NOVALAKE_S)
[22:03:58] [PASSED] 0xD744 (NOVALAKE_S)
[22:03:58] [PASSED] 0xD745 (NOVALAKE_S)
[22:03:58] [PASSED] 0x674C (CRESCENTISLAND)
[22:03:58] [PASSED] 0xD750 (NOVALAKE_P)
[22:03:58] [PASSED] 0xD751 (NOVALAKE_P)
[22:03:58] [PASSED] 0xD752 (NOVALAKE_P)
[22:03:58] [PASSED] 0xD753 (NOVALAKE_P)
[22:03:58] [PASSED] 0xD754 (NOVALAKE_P)
[22:03:58] [PASSED] 0xD755 (NOVALAKE_P)
[22:03:58] [PASSED] 0xD756 (NOVALAKE_P)
[22:03:58] [PASSED] 0xD757 (NOVALAKE_P)
[22:03:58] [PASSED] 0xD75F (NOVALAKE_P)
[22:03:58] =============== [PASSED] check_platform_desc ===============
[22:03:58] ===================== [PASSED] xe_pci ======================
[22:03:58] =================== xe_rtp (2 subtests) ====================
[22:03:58] =============== xe_rtp_process_to_sr_tests ================
[22:03:58] [PASSED] coalesce-same-reg
[22:03:58] [PASSED] no-match-no-add
[22:03:58] [PASSED] match-or
[22:03:58] [PASSED] match-or-xfail
[22:03:58] [PASSED] no-match-no-add-multiple-rules
[22:03:58] [PASSED] two-regs-two-entries
[22:03:58] [PASSED] clr-one-set-other
[22:03:58] [PASSED] set-field
[22:03:58] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[22:03:58] [PASSED] conflict-not-disjoint
[22:03:58] [PASSED] conflict-reg-type
[22:03:58] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[22:03:58] ================== xe_rtp_process_tests ===================
[22:03:58] [PASSED] active1
[22:03:58] [PASSED] active2
[22:03:58] [PASSED] active-inactive
[22:03:58] [PASSED] inactive-active
[22:03:58] [PASSED] inactive-1st_or_active-inactive
[22:03:58] [PASSED] inactive-2nd_or_active-inactive
[22:03:58] [PASSED] inactive-last_or_active-inactive
[22:03:58] [PASSED] inactive-no_or_active-inactive
[22:03:58] ============== [PASSED] xe_rtp_process_tests ===============
[22:03:58] ===================== [PASSED] xe_rtp ======================
[22:03:58] ==================== xe_wa (1 subtest) =====================
[22:03:58] ======================== xe_wa_gt =========================
[22:03:58] [PASSED] TIGERLAKE B0
[22:03:58] [PASSED] DG1 A0
[22:03:58] [PASSED] DG1 B0
[22:03:58] [PASSED] ALDERLAKE_S A0
[22:03:58] [PASSED] ALDERLAKE_S B0
[22:03:58] [PASSED] ALDERLAKE_S C0
[22:03:58] [PASSED] ALDERLAKE_S D0
[22:03:58] [PASSED] ALDERLAKE_P A0
[22:03:58] [PASSED] ALDERLAKE_P B0
[22:03:58] [PASSED] ALDERLAKE_P C0
[22:03:58] [PASSED] ALDERLAKE_S RPLS D0
[22:03:58] [PASSED] ALDERLAKE_P RPLU E0
[22:03:58] [PASSED] DG2 G10 C0
[22:03:58] [PASSED] DG2 G11 B1
[22:03:58] [PASSED] DG2 G12 A1
[22:03:58] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:03:58] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:03:58] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[22:03:58] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[22:03:58] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[22:03:58] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[22:03:58] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[22:03:58] ==================== [PASSED] xe_wa_gt =====================
[22:03:58] ====================== [PASSED] xe_wa ======================
[22:03:58] ============================================================
[22:03:58] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[22:03:58] Elapsed time: 35.577s total, 4.212s configuring, 30.699s building, 0.620s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[22:03:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:04:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:04:24] Starting KUnit Kernel (1/1)...
[22:04:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:04:24] ============ drm_test_pick_cmdline (2 subtests) ============
[22:04:24] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[22:04:24] =============== drm_test_pick_cmdline_named ===============
[22:04:24] [PASSED] NTSC
[22:04:24] [PASSED] NTSC-J
[22:04:24] [PASSED] PAL
[22:04:24] [PASSED] PAL-M
[22:04:24] =========== [PASSED] drm_test_pick_cmdline_named ===========
[22:04:24] ============== [PASSED] drm_test_pick_cmdline ==============
[22:04:24] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[22:04:24] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[22:04:24] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[22:04:24] =========== drm_validate_clone_mode (2 subtests) ===========
[22:04:24] ============== drm_test_check_in_clone_mode ===============
[22:04:24] [PASSED] in_clone_mode
[22:04:24] [PASSED] not_in_clone_mode
[22:04:24] ========== [PASSED] drm_test_check_in_clone_mode ===========
[22:04:24] =============== drm_test_check_valid_clones ===============
[22:04:24] [PASSED] not_in_clone_mode
[22:04:24] [PASSED] valid_clone
[22:04:24] [PASSED] invalid_clone
[22:04:24] =========== [PASSED] drm_test_check_valid_clones ===========
[22:04:24] ============= [PASSED] drm_validate_clone_mode =============
[22:04:24] ============= drm_validate_modeset (1 subtest) =============
[22:04:24] [PASSED] drm_test_check_connector_changed_modeset
[22:04:24] ============== [PASSED] drm_validate_modeset ===============
[22:04:24] ====== drm_test_bridge_get_current_state (2 subtests) ======
[22:04:24] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[22:04:24] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[22:04:24] ======== [PASSED] drm_test_bridge_get_current_state ========
[22:04:24] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[22:04:24] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[22:04:24] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[22:04:24] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[22:04:24] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[22:04:24] ============== drm_bridge_alloc (2 subtests) ===============
[22:04:24] [PASSED] drm_test_drm_bridge_alloc_basic
[22:04:24] [PASSED] drm_test_drm_bridge_alloc_get_put
[22:04:24] ================ [PASSED] drm_bridge_alloc =================
[22:04:24] ============= drm_cmdline_parser (40 subtests) =============
[22:04:24] [PASSED] drm_test_cmdline_force_d_only
[22:04:24] [PASSED] drm_test_cmdline_force_D_only_dvi
[22:04:24] [PASSED] drm_test_cmdline_force_D_only_hdmi
[22:04:24] [PASSED] drm_test_cmdline_force_D_only_not_digital
[22:04:24] [PASSED] drm_test_cmdline_force_e_only
[22:04:24] [PASSED] drm_test_cmdline_res
[22:04:24] [PASSED] drm_test_cmdline_res_vesa
[22:04:24] [PASSED] drm_test_cmdline_res_vesa_rblank
[22:04:24] [PASSED] drm_test_cmdline_res_rblank
[22:04:24] [PASSED] drm_test_cmdline_res_bpp
[22:04:24] [PASSED] drm_test_cmdline_res_refresh
[22:04:24] [PASSED] drm_test_cmdline_res_bpp_refresh
[22:04:24] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[22:04:24] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[22:04:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[22:04:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[22:04:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[22:04:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[22:04:24] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[22:04:24] [PASSED] drm_test_cmdline_res_margins_force_on
[22:04:24] [PASSED] drm_test_cmdline_res_vesa_margins
[22:04:24] [PASSED] drm_test_cmdline_name
[22:04:24] [PASSED] drm_test_cmdline_name_bpp
[22:04:24] [PASSED] drm_test_cmdline_name_option
[22:04:24] [PASSED] drm_test_cmdline_name_bpp_option
[22:04:24] [PASSED] drm_test_cmdline_rotate_0
[22:04:24] [PASSED] drm_test_cmdline_rotate_90
[22:04:24] [PASSED] drm_test_cmdline_rotate_180
[22:04:24] [PASSED] drm_test_cmdline_rotate_270
[22:04:24] [PASSED] drm_test_cmdline_hmirror
[22:04:24] [PASSED] drm_test_cmdline_vmirror
[22:04:24] [PASSED] drm_test_cmdline_margin_options
[22:04:24] [PASSED] drm_test_cmdline_multiple_options
[22:04:24] [PASSED] drm_test_cmdline_bpp_extra_and_option
[22:04:24] [PASSED] drm_test_cmdline_extra_and_option
[22:04:24] [PASSED] drm_test_cmdline_freestanding_options
[22:04:24] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[22:04:24] [PASSED] drm_test_cmdline_panel_orientation
[22:04:24] ================ drm_test_cmdline_invalid =================
[22:04:24] [PASSED] margin_only
[22:04:24] [PASSED] interlace_only
[22:04:24] [PASSED] res_missing_x
[22:04:24] [PASSED] res_missing_y
[22:04:24] [PASSED] res_bad_y
[22:04:24] [PASSED] res_missing_y_bpp
[22:04:24] [PASSED] res_bad_bpp
[22:04:24] [PASSED] res_bad_refresh
[22:04:24] [PASSED] res_bpp_refresh_force_on_off
[22:04:24] [PASSED] res_invalid_mode
[22:04:24] [PASSED] res_bpp_wrong_place_mode
[22:04:24] [PASSED] name_bpp_refresh
[22:04:24] [PASSED] name_refresh
[22:04:24] [PASSED] name_refresh_wrong_mode
[22:04:24] [PASSED] name_refresh_invalid_mode
[22:04:24] [PASSED] rotate_multiple
[22:04:24] [PASSED] rotate_invalid_val
[22:04:24] [PASSED] rotate_truncated
[22:04:24] [PASSED] invalid_option
[22:04:24] [PASSED] invalid_tv_option
[22:04:24] [PASSED] truncated_tv_option
[22:04:24] ============ [PASSED] drm_test_cmdline_invalid =============
[22:04:24] =============== drm_test_cmdline_tv_options ===============
[22:04:24] [PASSED] NTSC
[22:04:24] [PASSED] NTSC_443
[22:04:24] [PASSED] NTSC_J
[22:04:24] [PASSED] PAL
[22:04:24] [PASSED] PAL_M
[22:04:24] [PASSED] PAL_N
[22:04:24] [PASSED] SECAM
[22:04:24] [PASSED] MONO_525
[22:04:24] [PASSED] MONO_625
[22:04:24] =========== [PASSED] drm_test_cmdline_tv_options ===========
[22:04:24] =============== [PASSED] drm_cmdline_parser ================
[22:04:24] ========== drmm_connector_hdmi_init (20 subtests) ==========
[22:04:24] [PASSED] drm_test_connector_hdmi_init_valid
[22:04:24] [PASSED] drm_test_connector_hdmi_init_bpc_8
[22:04:24] [PASSED] drm_test_connector_hdmi_init_bpc_10
[22:04:24] [PASSED] drm_test_connector_hdmi_init_bpc_12
[22:04:24] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[22:04:24] [PASSED] drm_test_connector_hdmi_init_bpc_null
[22:04:24] [PASSED] drm_test_connector_hdmi_init_formats_empty
[22:04:24] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[22:04:24] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[22:04:24] [PASSED] supported_formats=0x9 yuv420_allowed=1
[22:04:24] [PASSED] supported_formats=0x9 yuv420_allowed=0
[22:04:24] [PASSED] supported_formats=0x3 yuv420_allowed=1
[22:04:24] [PASSED] supported_formats=0x3 yuv420_allowed=0
[22:04:24] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[22:04:24] [PASSED] drm_test_connector_hdmi_init_null_ddc
[22:04:24] [PASSED] drm_test_connector_hdmi_init_null_product
[22:04:24] [PASSED] drm_test_connector_hdmi_init_null_vendor
[22:04:24] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[22:04:24] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[22:04:24] [PASSED] drm_test_connector_hdmi_init_product_valid
[22:04:24] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[22:04:24] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[22:04:24] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[22:04:24] ========= drm_test_connector_hdmi_init_type_valid =========
[22:04:24] [PASSED] HDMI-A
[22:04:24] [PASSED] HDMI-B
[22:04:24] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[22:04:24] ======== drm_test_connector_hdmi_init_type_invalid ========
[22:04:24] [PASSED] Unknown
[22:04:24] [PASSED] VGA
[22:04:24] [PASSED] DVI-I
[22:04:24] [PASSED] DVI-D
[22:04:24] [PASSED] DVI-A
[22:04:24] [PASSED] Composite
[22:04:24] [PASSED] SVIDEO
[22:04:24] [PASSED] LVDS
[22:04:24] [PASSED] Component
[22:04:24] [PASSED] DIN
[22:04:24] [PASSED] DP
[22:04:24] [PASSED] TV
[22:04:24] [PASSED] eDP
[22:04:24] [PASSED] Virtual
[22:04:24] [PASSED] DSI
[22:04:24] [PASSED] DPI
[22:04:24] [PASSED] Writeback
[22:04:24] [PASSED] SPI
[22:04:24] [PASSED] USB
[22:04:24] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[22:04:24] ============ [PASSED] drmm_connector_hdmi_init =============
[22:04:24] ============= drmm_connector_init (3 subtests) =============
[22:04:24] [PASSED] drm_test_drmm_connector_init
[22:04:24] [PASSED] drm_test_drmm_connector_init_null_ddc
[22:04:24] ========= drm_test_drmm_connector_init_type_valid =========
[22:04:24] [PASSED] Unknown
[22:04:24] [PASSED] VGA
[22:04:24] [PASSED] DVI-I
[22:04:24] [PASSED] DVI-D
[22:04:24] [PASSED] DVI-A
[22:04:24] [PASSED] Composite
[22:04:24] [PASSED] SVIDEO
[22:04:24] [PASSED] LVDS
[22:04:24] [PASSED] Component
[22:04:24] [PASSED] DIN
[22:04:24] [PASSED] DP
[22:04:24] [PASSED] HDMI-A
[22:04:24] [PASSED] HDMI-B
[22:04:24] [PASSED] TV
[22:04:24] [PASSED] eDP
[22:04:24] [PASSED] Virtual
[22:04:24] [PASSED] DSI
[22:04:24] [PASSED] DPI
[22:04:24] [PASSED] Writeback
[22:04:24] [PASSED] SPI
[22:04:24] [PASSED] USB
[22:04:24] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[22:04:24] =============== [PASSED] drmm_connector_init ===============
[22:04:24] ========= drm_connector_dynamic_init (6 subtests) ==========
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_init
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_init_properties
[22:04:24] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[22:04:24] [PASSED] Unknown
[22:04:24] [PASSED] VGA
[22:04:24] [PASSED] DVI-I
[22:04:24] [PASSED] DVI-D
[22:04:24] [PASSED] DVI-A
[22:04:24] [PASSED] Composite
[22:04:24] [PASSED] SVIDEO
[22:04:24] [PASSED] LVDS
[22:04:24] [PASSED] Component
[22:04:24] [PASSED] DIN
[22:04:24] [PASSED] DP
[22:04:24] [PASSED] HDMI-A
[22:04:24] [PASSED] HDMI-B
[22:04:24] [PASSED] TV
[22:04:24] [PASSED] eDP
[22:04:24] [PASSED] Virtual
[22:04:24] [PASSED] DSI
[22:04:24] [PASSED] DPI
[22:04:24] [PASSED] Writeback
[22:04:24] [PASSED] SPI
[22:04:24] [PASSED] USB
[22:04:24] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[22:04:24] ======== drm_test_drm_connector_dynamic_init_name =========
[22:04:24] [PASSED] Unknown
[22:04:24] [PASSED] VGA
[22:04:24] [PASSED] DVI-I
[22:04:24] [PASSED] DVI-D
[22:04:24] [PASSED] DVI-A
[22:04:24] [PASSED] Composite
[22:04:24] [PASSED] SVIDEO
[22:04:24] [PASSED] LVDS
[22:04:24] [PASSED] Component
[22:04:24] [PASSED] DIN
[22:04:24] [PASSED] DP
[22:04:24] [PASSED] HDMI-A
[22:04:24] [PASSED] HDMI-B
[22:04:24] [PASSED] TV
[22:04:24] [PASSED] eDP
[22:04:24] [PASSED] Virtual
[22:04:24] [PASSED] DSI
[22:04:24] [PASSED] DPI
[22:04:24] [PASSED] Writeback
[22:04:24] [PASSED] SPI
[22:04:24] [PASSED] USB
[22:04:24] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[22:04:24] =========== [PASSED] drm_connector_dynamic_init ============
[22:04:24] ==== drm_connector_dynamic_register_early (4 subtests) =====
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[22:04:24] ====== [PASSED] drm_connector_dynamic_register_early =======
[22:04:24] ======= drm_connector_dynamic_register (7 subtests) ========
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[22:04:24] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[22:04:24] ========= [PASSED] drm_connector_dynamic_register ==========
[22:04:24] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[22:04:24] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[22:04:24] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[22:04:24] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[22:04:24] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[22:04:24] ========== drm_test_get_tv_mode_from_name_valid ===========
[22:04:24] [PASSED] NTSC
[22:04:24] [PASSED] NTSC-443
[22:04:24] [PASSED] NTSC-J
[22:04:24] [PASSED] PAL
[22:04:24] [PASSED] PAL-M
[22:04:24] [PASSED] PAL-N
[22:04:24] [PASSED] SECAM
[22:04:24] [PASSED] Mono
[22:04:24] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[22:04:24] [PASSED] drm_test_get_tv_mode_from_name_truncated
[22:04:24] ============ [PASSED] drm_get_tv_mode_from_name ============
[22:04:24] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[22:04:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[22:04:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[22:04:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[22:04:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[22:04:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[22:04:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[22:04:24] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[22:04:24] [PASSED] VIC 96
[22:04:24] [PASSED] VIC 97
[22:04:24] [PASSED] VIC 101
[22:04:24] [PASSED] VIC 102
[22:04:24] [PASSED] VIC 106
[22:04:24] [PASSED] VIC 107
[22:04:24] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[22:04:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[22:04:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[22:04:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[22:04:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[22:04:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[22:04:24] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[22:04:24] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[22:04:24] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[22:04:24] [PASSED] Automatic
[22:04:24] [PASSED] Full
[22:04:24] [PASSED] Limited 16:235
[22:04:24] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[22:04:24] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[22:04:24] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[22:04:24] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[22:04:24] === drm_test_drm_hdmi_connector_get_output_format_name ====
[22:04:24] [PASSED] RGB
[22:04:24] [PASSED] YUV 4:2:0
[22:04:24] [PASSED] YUV 4:2:2
[22:04:24] [PASSED] YUV 4:4:4
[22:04:24] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[22:04:24] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[22:04:24] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[22:04:24] ============= drm_damage_helper (21 subtests) ==============
[22:04:24] [PASSED] drm_test_damage_iter_no_damage
[22:04:24] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[22:04:24] [PASSED] drm_test_damage_iter_no_damage_src_moved
[22:04:24] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[22:04:24] [PASSED] drm_test_damage_iter_no_damage_not_visible
[22:04:24] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[22:04:24] [PASSED] drm_test_damage_iter_no_damage_no_fb
[22:04:24] [PASSED] drm_test_damage_iter_simple_damage
[22:04:24] [PASSED] drm_test_damage_iter_single_damage
[22:04:24] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[22:04:24] [PASSED] drm_test_damage_iter_single_damage_outside_src
[22:04:24] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[22:04:24] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[22:04:24] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[22:04:24] [PASSED] drm_test_damage_iter_single_damage_src_moved
[22:04:24] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[22:04:24] [PASSED] drm_test_damage_iter_damage
[22:04:24] [PASSED] drm_test_damage_iter_damage_one_intersect
[22:04:24] [PASSED] drm_test_damage_iter_damage_one_outside
[22:04:24] [PASSED] drm_test_damage_iter_damage_src_moved
[22:04:24] [PASSED] drm_test_damage_iter_damage_not_visible
[22:04:24] ================ [PASSED] drm_damage_helper ================
[22:04:24] ============== drm_dp_mst_helper (3 subtests) ==============
[22:04:24] ============== drm_test_dp_mst_calc_pbn_mode ==============
[22:04:24] [PASSED] Clock 154000 BPP 30 DSC disabled
[22:04:24] [PASSED] Clock 234000 BPP 30 DSC disabled
[22:04:24] [PASSED] Clock 297000 BPP 24 DSC disabled
[22:04:24] [PASSED] Clock 332880 BPP 24 DSC enabled
[22:04:24] [PASSED] Clock 324540 BPP 24 DSC enabled
[22:04:24] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[22:04:24] ============== drm_test_dp_mst_calc_pbn_div ===============
[22:04:24] [PASSED] Link rate 2000000 lane count 4
[22:04:24] [PASSED] Link rate 2000000 lane count 2
[22:04:24] [PASSED] Link rate 2000000 lane count 1
[22:04:24] [PASSED] Link rate 1350000 lane count 4
[22:04:24] [PASSED] Link rate 1350000 lane count 2
[22:04:24] [PASSED] Link rate 1350000 lane count 1
[22:04:24] [PASSED] Link rate 1000000 lane count 4
[22:04:24] [PASSED] Link rate 1000000 lane count 2
[22:04:24] [PASSED] Link rate 1000000 lane count 1
[22:04:24] [PASSED] Link rate 810000 lane count 4
[22:04:24] [PASSED] Link rate 810000 lane count 2
[22:04:24] [PASSED] Link rate 810000 lane count 1
[22:04:24] [PASSED] Link rate 540000 lane count 4
[22:04:24] [PASSED] Link rate 540000 lane count 2
[22:04:24] [PASSED] Link rate 540000 lane count 1
[22:04:24] [PASSED] Link rate 270000 lane count 4
[22:04:24] [PASSED] Link rate 270000 lane count 2
[22:04:24] [PASSED] Link rate 270000 lane count 1
[22:04:24] [PASSED] Link rate 162000 lane count 4
[22:04:24] [PASSED] Link rate 162000 lane count 2
[22:04:24] [PASSED] Link rate 162000 lane count 1
[22:04:24] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[22:04:24] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[22:04:24] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[22:04:24] [PASSED] DP_POWER_UP_PHY with port number
[22:04:24] [PASSED] DP_POWER_DOWN_PHY with port number
[22:04:24] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[22:04:24] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[22:04:24] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[22:04:24] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[22:04:24] [PASSED] DP_QUERY_PAYLOAD with port number
[22:04:24] [PASSED] DP_QUERY_PAYLOAD with VCPI
[22:04:24] [PASSED] DP_REMOTE_DPCD_READ with port number
[22:04:24] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[22:04:24] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[22:04:24] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[22:04:24] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[22:04:24] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[22:04:24] [PASSED] DP_REMOTE_I2C_READ with port number
[22:04:24] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[22:04:24] [PASSED] DP_REMOTE_I2C_READ with transactions array
[22:04:24] [PASSED] DP_REMOTE_I2C_WRITE with port number
[22:04:24] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[22:04:24] [PASSED] DP_REMOTE_I2C_WRITE with data array
[22:04:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[22:04:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[22:04:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[22:04:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[22:04:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[22:04:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[22:04:24] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[22:04:24] ================ [PASSED] drm_dp_mst_helper ================
[22:04:24] ================== drm_exec (7 subtests) ===================
[22:04:24] [PASSED] sanitycheck
[22:04:24] [PASSED] test_lock
[22:04:24] [PASSED] test_lock_unlock
[22:04:24] [PASSED] test_duplicates
[22:04:24] [PASSED] test_prepare
[22:04:24] [PASSED] test_prepare_array
[22:04:24] [PASSED] test_multiple_loops
[22:04:24] ==================== [PASSED] drm_exec =====================
[22:04:24] =========== drm_format_helper_test (17 subtests) ===========
[22:04:24] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[22:04:24] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[22:04:24] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[22:04:24] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[22:04:24] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[22:04:24] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[22:04:24] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[22:04:24] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[22:04:24] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[22:04:24] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[22:04:24] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[22:04:24] ============== drm_test_fb_xrgb8888_to_mono ===============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[22:04:24] ==================== drm_test_fb_swab =====================
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ================ [PASSED] drm_test_fb_swab =================
[22:04:24] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[22:04:24] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[22:04:24] [PASSED] single_pixel_source_buffer
[22:04:24] [PASSED] single_pixel_clip_rectangle
[22:04:24] [PASSED] well_known_colors
[22:04:24] [PASSED] destination_pitch
[22:04:24] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[22:04:24] ================= drm_test_fb_clip_offset =================
[22:04:24] [PASSED] pass through
[22:04:24] [PASSED] horizontal offset
[22:04:24] [PASSED] vertical offset
[22:04:24] [PASSED] horizontal and vertical offset
[22:04:24] [PASSED] horizontal offset (custom pitch)
[22:04:24] [PASSED] vertical offset (custom pitch)
[22:04:24] [PASSED] horizontal and vertical offset (custom pitch)
[22:04:24] ============= [PASSED] drm_test_fb_clip_offset =============
[22:04:24] =================== drm_test_fb_memcpy ====================
[22:04:24] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[22:04:24] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[22:04:24] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[22:04:24] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[22:04:24] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[22:04:24] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[22:04:24] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[22:04:24] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[22:04:24] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[22:04:24] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[22:04:24] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[22:04:24] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[22:04:24] =============== [PASSED] drm_test_fb_memcpy ================
[22:04:24] ============= [PASSED] drm_format_helper_test ==============
[22:04:24] ================= drm_format (18 subtests) =================
[22:04:24] [PASSED] drm_test_format_block_width_invalid
[22:04:24] [PASSED] drm_test_format_block_width_one_plane
[22:04:24] [PASSED] drm_test_format_block_width_two_plane
[22:04:24] [PASSED] drm_test_format_block_width_three_plane
[22:04:24] [PASSED] drm_test_format_block_width_tiled
[22:04:24] [PASSED] drm_test_format_block_height_invalid
[22:04:24] [PASSED] drm_test_format_block_height_one_plane
[22:04:24] [PASSED] drm_test_format_block_height_two_plane
[22:04:24] [PASSED] drm_test_format_block_height_three_plane
[22:04:24] [PASSED] drm_test_format_block_height_tiled
[22:04:24] [PASSED] drm_test_format_min_pitch_invalid
[22:04:24] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[22:04:24] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[22:04:24] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[22:04:24] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[22:04:24] [PASSED] drm_test_format_min_pitch_two_plane
[22:04:24] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[22:04:24] [PASSED] drm_test_format_min_pitch_tiled
[22:04:24] =================== [PASSED] drm_format ====================
[22:04:24] ============== drm_framebuffer (10 subtests) ===============
[22:04:24] ========== drm_test_framebuffer_check_src_coords ==========
[22:04:24] [PASSED] Success: source fits into fb
[22:04:24] [PASSED] Fail: overflowing fb with x-axis coordinate
[22:04:24] [PASSED] Fail: overflowing fb with y-axis coordinate
[22:04:24] [PASSED] Fail: overflowing fb with source width
[22:04:24] [PASSED] Fail: overflowing fb with source height
[22:04:24] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[22:04:24] [PASSED] drm_test_framebuffer_cleanup
[22:04:24] =============== drm_test_framebuffer_create ===============
[22:04:24] [PASSED] ABGR8888 normal sizes
[22:04:24] [PASSED] ABGR8888 max sizes
[22:04:24] [PASSED] ABGR8888 pitch greater than min required
[22:04:24] [PASSED] ABGR8888 pitch less than min required
[22:04:24] [PASSED] ABGR8888 Invalid width
[22:04:24] [PASSED] ABGR8888 Invalid buffer handle
[22:04:24] [PASSED] No pixel format
[22:04:24] [PASSED] ABGR8888 Width 0
[22:04:24] [PASSED] ABGR8888 Height 0
[22:04:24] [PASSED] ABGR8888 Out of bound height * pitch combination
[22:04:24] [PASSED] ABGR8888 Large buffer offset
[22:04:24] [PASSED] ABGR8888 Buffer offset for inexistent plane
[22:04:24] [PASSED] ABGR8888 Invalid flag
[22:04:24] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[22:04:24] [PASSED] ABGR8888 Valid buffer modifier
[22:04:24] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[22:04:24] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[22:04:24] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[22:04:24] [PASSED] NV12 Normal sizes
[22:04:24] [PASSED] NV12 Max sizes
[22:04:24] [PASSED] NV12 Invalid pitch
[22:04:24] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[22:04:24] [PASSED] NV12 different modifier per-plane
[22:04:24] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[22:04:24] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[22:04:24] [PASSED] NV12 Modifier for inexistent plane
[22:04:24] [PASSED] NV12 Handle for inexistent plane
[22:04:24] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[22:04:24] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[22:04:24] [PASSED] YVU420 Normal sizes
[22:04:24] [PASSED] YVU420 Max sizes
[22:04:24] [PASSED] YVU420 Invalid pitch
[22:04:24] [PASSED] YVU420 Different pitches
[22:04:24] [PASSED] YVU420 Different buffer offsets/pitches
[22:04:24] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[22:04:24] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[22:04:24] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[22:04:24] [PASSED] YVU420 Valid modifier
[22:04:24] [PASSED] YVU420 Different modifiers per plane
[22:04:24] [PASSED] YVU420 Modifier for inexistent plane
[22:04:24] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[22:04:24] [PASSED] X0L2 Normal sizes
[22:04:24] [PASSED] X0L2 Max sizes
[22:04:24] [PASSED] X0L2 Invalid pitch
[22:04:24] [PASSED] X0L2 Pitch greater than minimum required
[22:04:24] [PASSED] X0L2 Handle for inexistent plane
[22:04:24] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[22:04:24] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[22:04:24] [PASSED] X0L2 Valid modifier
[22:04:24] [PASSED] X0L2 Modifier for inexistent plane
[22:04:24] =========== [PASSED] drm_test_framebuffer_create ===========
[22:04:24] [PASSED] drm_test_framebuffer_free
[22:04:24] [PASSED] drm_test_framebuffer_init
[22:04:24] [PASSED] drm_test_framebuffer_init_bad_format
[22:04:24] [PASSED] drm_test_framebuffer_init_dev_mismatch
[22:04:24] [PASSED] drm_test_framebuffer_lookup
[22:04:24] [PASSED] drm_test_framebuffer_lookup_inexistent
[22:04:24] [PASSED] drm_test_framebuffer_modifiers_not_supported
[22:04:24] ================= [PASSED] drm_framebuffer =================
[22:04:24] ================ drm_gem_shmem (8 subtests) ================
[22:04:24] [PASSED] drm_gem_shmem_test_obj_create
[22:04:24] [PASSED] drm_gem_shmem_test_obj_create_private
[22:04:24] [PASSED] drm_gem_shmem_test_pin_pages
[22:04:24] [PASSED] drm_gem_shmem_test_vmap
[22:04:24] [PASSED] drm_gem_shmem_test_get_sg_table
[22:04:24] [PASSED] drm_gem_shmem_test_get_pages_sgt
[22:04:24] [PASSED] drm_gem_shmem_test_madvise
[22:04:24] [PASSED] drm_gem_shmem_test_purge
[22:04:24] ================== [PASSED] drm_gem_shmem ==================
[22:04:24] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[22:04:24] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[22:04:24] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[22:04:24] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[22:04:24] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[22:04:24] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[22:04:24] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[22:04:24] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[22:04:24] [PASSED] Automatic
[22:04:24] [PASSED] Full
[22:04:24] [PASSED] Limited 16:235
[22:04:24] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[22:04:24] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[22:04:24] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[22:04:24] [PASSED] drm_test_check_disable_connector
[22:04:24] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[22:04:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[22:04:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[22:04:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[22:04:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[22:04:24] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[22:04:24] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[22:04:24] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[22:04:24] [PASSED] drm_test_check_output_bpc_dvi
[22:04:24] [PASSED] drm_test_check_output_bpc_format_vic_1
[22:04:24] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[22:04:24] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[22:04:24] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[22:04:24] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[22:04:24] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[22:04:24] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[22:04:24] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[22:04:24] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[22:04:24] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[22:04:24] [PASSED] drm_test_check_broadcast_rgb_value
[22:04:24] [PASSED] drm_test_check_bpc_8_value
[22:04:24] [PASSED] drm_test_check_bpc_10_value
[22:04:24] [PASSED] drm_test_check_bpc_12_value
[22:04:24] [PASSED] drm_test_check_format_value
[22:04:24] [PASSED] drm_test_check_tmds_char_value
[22:04:24] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[22:04:24] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[22:04:24] [PASSED] drm_test_check_mode_valid
[22:04:24] [PASSED] drm_test_check_mode_valid_reject
[22:04:24] [PASSED] drm_test_check_mode_valid_reject_rate
[22:04:24] [PASSED] drm_test_check_mode_valid_reject_max_clock
[22:04:24] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[22:04:24] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[22:04:24] [PASSED] drm_test_check_infoframes
[22:04:24] [PASSED] drm_test_check_reject_avi_infoframe
[22:04:24] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[22:04:24] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[22:04:24] [PASSED] drm_test_check_reject_audio_infoframe
[22:04:24] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[22:04:24] ================= drm_managed (2 subtests) =================
[22:04:24] [PASSED] drm_test_managed_release_action
[22:04:24] [PASSED] drm_test_managed_run_action
[22:04:24] =================== [PASSED] drm_managed ===================
[22:04:24] =================== drm_mm (6 subtests) ====================
[22:04:24] [PASSED] drm_test_mm_init
[22:04:24] [PASSED] drm_test_mm_debug
[22:04:24] [PASSED] drm_test_mm_align32
[22:04:24] [PASSED] drm_test_mm_align64
[22:04:24] [PASSED] drm_test_mm_lowest
[22:04:24] [PASSED] drm_test_mm_highest
[22:04:24] ===================== [PASSED] drm_mm ======================
[22:04:24] ============= drm_modes_analog_tv (5 subtests) =============
[22:04:24] [PASSED] drm_test_modes_analog_tv_mono_576i
[22:04:24] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[22:04:24] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[22:04:24] [PASSED] drm_test_modes_analog_tv_pal_576i
[22:04:24] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[22:04:24] =============== [PASSED] drm_modes_analog_tv ===============
[22:04:24] ============== drm_plane_helper (2 subtests) ===============
[22:04:24] =============== drm_test_check_plane_state ================
[22:04:24] [PASSED] clipping_simple
[22:04:24] [PASSED] clipping_rotate_reflect
[22:04:24] [PASSED] positioning_simple
[22:04:24] [PASSED] upscaling
[22:04:24] [PASSED] downscaling
[22:04:24] [PASSED] rounding1
[22:04:24] [PASSED] rounding2
[22:04:24] [PASSED] rounding3
[22:04:24] [PASSED] rounding4
[22:04:24] =========== [PASSED] drm_test_check_plane_state ============
[22:04:24] =========== drm_test_check_invalid_plane_state ============
[22:04:24] [PASSED] positioning_invalid
[22:04:24] [PASSED] upscaling_invalid
[22:04:24] [PASSED] downscaling_invalid
[22:04:24] ======= [PASSED] drm_test_check_invalid_plane_state ========
[22:04:24] ================ [PASSED] drm_plane_helper =================
[22:04:24] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[22:04:24] ====== drm_test_connector_helper_tv_get_modes_check =======
[22:04:24] [PASSED] None
[22:04:24] [PASSED] PAL
[22:04:24] [PASSED] NTSC
[22:04:24] [PASSED] Both, NTSC Default
[22:04:24] [PASSED] Both, PAL Default
[22:04:24] [PASSED] Both, NTSC Default, with PAL on command-line
[22:04:24] [PASSED] Both, PAL Default, with NTSC on command-line
[22:04:24] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[22:04:24] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[22:04:24] ================== drm_rect (9 subtests) ===================
[22:04:24] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[22:04:24] [PASSED] drm_test_rect_clip_scaled_not_clipped
[22:04:24] [PASSED] drm_test_rect_clip_scaled_clipped
[22:04:24] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[22:04:24] ================= drm_test_rect_intersect =================
[22:04:24] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[22:04:24] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[22:04:24] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[22:04:24] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[22:04:24] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[22:04:24] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[22:04:24] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[22:04:24] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[22:04:24] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[22:04:24] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[22:04:24] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[22:04:24] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[22:04:24] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[22:04:24] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[22:04:24] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[22:04:24] ============= [PASSED] drm_test_rect_intersect =============
[22:04:24] ================ drm_test_rect_calc_hscale ================
[22:04:24] [PASSED] normal use
[22:04:24] [PASSED] out of max range
[22:04:24] [PASSED] out of min range
[22:04:24] [PASSED] zero dst
[22:04:24] [PASSED] negative src
[22:04:24] [PASSED] negative dst
[22:04:24] ============ [PASSED] drm_test_rect_calc_hscale ============
[22:04:24] ================ drm_test_rect_calc_vscale ================
[22:04:24] [PASSED] normal use
[22:04:24] [PASSED] out of max range
[22:04:24] [PASSED] out of min range
[22:04:24] [PASSED] zero dst
[22:04:24] [PASSED] negative src
[22:04:24] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[22:04:24] ============ [PASSED] drm_test_rect_calc_vscale ============
[22:04:24] ================== drm_test_rect_rotate ===================
[22:04:24] [PASSED] reflect-x
[22:04:24] [PASSED] reflect-y
[22:04:24] [PASSED] rotate-0
[22:04:24] [PASSED] rotate-90
[22:04:24] [PASSED] rotate-180
[22:04:24] [PASSED] rotate-270
[22:04:24] ============== [PASSED] drm_test_rect_rotate ===============
[22:04:24] ================ drm_test_rect_rotate_inv =================
[22:04:24] [PASSED] reflect-x
[22:04:24] [PASSED] reflect-y
[22:04:24] [PASSED] rotate-0
[22:04:24] [PASSED] rotate-90
[22:04:24] [PASSED] rotate-180
[22:04:24] [PASSED] rotate-270
[22:04:24] ============ [PASSED] drm_test_rect_rotate_inv =============
[22:04:24] ==================== [PASSED] drm_rect =====================
[22:04:24] ============ drm_sysfb_modeset_test (1 subtest) ============
[22:04:24] ============ drm_test_sysfb_build_fourcc_list =============
[22:04:24] [PASSED] no native formats
[22:04:24] [PASSED] XRGB8888 as native format
[22:04:24] [PASSED] remove duplicates
[22:04:24] [PASSED] convert alpha formats
[22:04:24] [PASSED] random formats
[22:04:24] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[22:04:24] ============= [PASSED] drm_sysfb_modeset_test ==============
[22:04:24] ================== drm_fixp (2 subtests) ===================
[22:04:24] [PASSED] drm_test_int2fixp
[22:04:24] [PASSED] drm_test_sm2fixp
[22:04:24] ==================== [PASSED] drm_fixp =====================
[22:04:24] ============================================================
[22:04:24] Testing complete. Ran 621 tests: passed: 621
[22:04:24] Elapsed time: 26.096s total, 1.769s configuring, 24.161s building, 0.114s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[22:04:25] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:04:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:04:36] Starting KUnit Kernel (1/1)...
[22:04:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:04:36] ================= ttm_device (5 subtests) ==================
[22:04:36] [PASSED] ttm_device_init_basic
[22:04:36] [PASSED] ttm_device_init_multiple
[22:04:36] [PASSED] ttm_device_fini_basic
[22:04:36] [PASSED] ttm_device_init_no_vma_man
[22:04:36] ================== ttm_device_init_pools ==================
[22:04:36] [PASSED] No DMA allocations, no DMA32 required
[22:04:36] [PASSED] DMA allocations, DMA32 required
[22:04:36] [PASSED] No DMA allocations, DMA32 required
[22:04:36] [PASSED] DMA allocations, no DMA32 required
[22:04:36] ============== [PASSED] ttm_device_init_pools ==============
[22:04:36] =================== [PASSED] ttm_device ====================
[22:04:36] ================== ttm_pool (8 subtests) ===================
[22:04:36] ================== ttm_pool_alloc_basic ===================
[22:04:36] [PASSED] One page
[22:04:36] [PASSED] More than one page
[22:04:36] [PASSED] Above the allocation limit
[22:04:36] [PASSED] One page, with coherent DMA mappings enabled
[22:04:36] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:04:36] ============== [PASSED] ttm_pool_alloc_basic ===============
[22:04:36] ============== ttm_pool_alloc_basic_dma_addr ==============
[22:04:36] [PASSED] One page
[22:04:36] [PASSED] More than one page
[22:04:36] [PASSED] Above the allocation limit
[22:04:36] [PASSED] One page, with coherent DMA mappings enabled
[22:04:36] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:04:36] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[22:04:36] [PASSED] ttm_pool_alloc_order_caching_match
[22:04:36] [PASSED] ttm_pool_alloc_caching_mismatch
[22:04:36] [PASSED] ttm_pool_alloc_order_mismatch
[22:04:36] [PASSED] ttm_pool_free_dma_alloc
[22:04:36] [PASSED] ttm_pool_free_no_dma_alloc
[22:04:36] [PASSED] ttm_pool_fini_basic
[22:04:36] ==================== [PASSED] ttm_pool =====================
[22:04:36] ================ ttm_resource (8 subtests) =================
[22:04:36] ================= ttm_resource_init_basic =================
[22:04:36] [PASSED] Init resource in TTM_PL_SYSTEM
[22:04:36] [PASSED] Init resource in TTM_PL_VRAM
[22:04:36] [PASSED] Init resource in a private placement
[22:04:36] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[22:04:36] ============= [PASSED] ttm_resource_init_basic =============
[22:04:36] [PASSED] ttm_resource_init_pinned
[22:04:36] [PASSED] ttm_resource_fini_basic
[22:04:36] [PASSED] ttm_resource_manager_init_basic
[22:04:36] [PASSED] ttm_resource_manager_usage_basic
[22:04:36] [PASSED] ttm_resource_manager_set_used_basic
[22:04:36] [PASSED] ttm_sys_man_alloc_basic
[22:04:36] [PASSED] ttm_sys_man_free_basic
[22:04:36] ================== [PASSED] ttm_resource ===================
[22:04:36] =================== ttm_tt (15 subtests) ===================
[22:04:36] ==================== ttm_tt_init_basic ====================
[22:04:36] [PASSED] Page-aligned size
[22:04:36] [PASSED] Extra pages requested
[22:04:36] ================ [PASSED] ttm_tt_init_basic ================
[22:04:36] [PASSED] ttm_tt_init_misaligned
[22:04:36] [PASSED] ttm_tt_fini_basic
[22:04:36] [PASSED] ttm_tt_fini_sg
[22:04:36] [PASSED] ttm_tt_fini_shmem
[22:04:36] [PASSED] ttm_tt_create_basic
[22:04:36] [PASSED] ttm_tt_create_invalid_bo_type
[22:04:36] [PASSED] ttm_tt_create_ttm_exists
[22:04:36] [PASSED] ttm_tt_create_failed
[22:04:36] [PASSED] ttm_tt_destroy_basic
[22:04:36] [PASSED] ttm_tt_populate_null_ttm
[22:04:36] [PASSED] ttm_tt_populate_populated_ttm
[22:04:36] [PASSED] ttm_tt_unpopulate_basic
[22:04:36] [PASSED] ttm_tt_unpopulate_empty_ttm
[22:04:36] [PASSED] ttm_tt_swapin_basic
[22:04:36] ===================== [PASSED] ttm_tt ======================
[22:04:36] =================== ttm_bo (14 subtests) ===================
[22:04:36] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[22:04:36] [PASSED] Cannot be interrupted and sleeps
[22:04:36] [PASSED] Cannot be interrupted, locks straight away
[22:04:36] [PASSED] Can be interrupted, sleeps
[22:04:36] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[22:04:36] [PASSED] ttm_bo_reserve_locked_no_sleep
[22:04:36] [PASSED] ttm_bo_reserve_no_wait_ticket
[22:04:36] [PASSED] ttm_bo_reserve_double_resv
[22:04:36] [PASSED] ttm_bo_reserve_interrupted
[22:04:36] [PASSED] ttm_bo_reserve_deadlock
[22:04:36] [PASSED] ttm_bo_unreserve_basic
[22:04:36] [PASSED] ttm_bo_unreserve_pinned
[22:04:36] [PASSED] ttm_bo_unreserve_bulk
[22:04:36] [PASSED] ttm_bo_fini_basic
[22:04:36] [PASSED] ttm_bo_fini_shared_resv
[22:04:36] [PASSED] ttm_bo_pin_basic
[22:04:36] [PASSED] ttm_bo_pin_unpin_resource
[22:04:36] [PASSED] ttm_bo_multiple_pin_one_unpin
[22:04:36] ===================== [PASSED] ttm_bo ======================
[22:04:36] ============== ttm_bo_validate (22 subtests) ===============
[22:04:36] ============== ttm_bo_init_reserved_sys_man ===============
[22:04:36] [PASSED] Buffer object for userspace
[22:04:36] [PASSED] Kernel buffer object
[22:04:36] [PASSED] Shared buffer object
[22:04:36] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[22:04:36] ============== ttm_bo_init_reserved_mock_man ==============
[22:04:36] [PASSED] Buffer object for userspace
[22:04:36] [PASSED] Kernel buffer object
[22:04:36] [PASSED] Shared buffer object
[22:04:36] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[22:04:36] [PASSED] ttm_bo_init_reserved_resv
[22:04:36] ================== ttm_bo_validate_basic ==================
[22:04:36] [PASSED] Buffer object for userspace
[22:04:36] [PASSED] Kernel buffer object
[22:04:36] [PASSED] Shared buffer object
[22:04:36] ============== [PASSED] ttm_bo_validate_basic ==============
[22:04:36] [PASSED] ttm_bo_validate_invalid_placement
[22:04:36] ============= ttm_bo_validate_same_placement ==============
[22:04:36] [PASSED] System manager
[22:04:36] [PASSED] VRAM manager
[22:04:36] ========= [PASSED] ttm_bo_validate_same_placement ==========
[22:04:36] [PASSED] ttm_bo_validate_failed_alloc
[22:04:36] [PASSED] ttm_bo_validate_pinned
[22:04:36] [PASSED] ttm_bo_validate_busy_placement
[22:04:36] ================ ttm_bo_validate_multihop =================
[22:04:36] [PASSED] Buffer object for userspace
[22:04:36] [PASSED] Kernel buffer object
[22:04:36] [PASSED] Shared buffer object
[22:04:36] ============ [PASSED] ttm_bo_validate_multihop =============
[22:04:36] ========== ttm_bo_validate_no_placement_signaled ==========
[22:04:36] [PASSED] Buffer object in system domain, no page vector
[22:04:36] [PASSED] Buffer object in system domain with an existing page vector
[22:04:36] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[22:04:36] ======== ttm_bo_validate_no_placement_not_signaled ========
[22:04:36] [PASSED] Buffer object for userspace
[22:04:36] [PASSED] Kernel buffer object
[22:04:36] [PASSED] Shared buffer object
[22:04:36] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[22:04:36] [PASSED] ttm_bo_validate_move_fence_signaled
[22:04:36] ========= ttm_bo_validate_move_fence_not_signaled =========
[22:04:36] [PASSED] Waits for GPU
[22:04:36] [PASSED] Tries to lock straight away
[22:04:36] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[22:04:36] [PASSED] ttm_bo_validate_swapout
[22:04:36] [PASSED] ttm_bo_validate_happy_evict
[22:04:36] [PASSED] ttm_bo_validate_all_pinned_evict
[22:04:36] [PASSED] ttm_bo_validate_allowed_only_evict
[22:04:36] [PASSED] ttm_bo_validate_deleted_evict
[22:04:36] [PASSED] ttm_bo_validate_busy_domain_evict
[22:04:36] [PASSED] ttm_bo_validate_evict_gutting
[22:04:36] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[22:04:36] ================= [PASSED] ttm_bo_validate =================
[22:04:36] ============================================================
[22:04:36] Testing complete. Ran 102 tests: passed: 102
[22:04:36] Elapsed time: 11.409s total, 1.667s configuring, 9.526s building, 0.182s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Xe.CI.BAT: success for series starting with [v2,1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-16 17:58 [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset Harish Chegondi
2026-03-16 22:04 ` ✓ CI.KUnit: success for series starting with [v2,1/1] " Patchwork
@ 2026-03-16 22:51 ` Patchwork
2026-03-17 23:24 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-18 6:57 ` [PATCH v2 1/1] " Dixit, Ashutosh
3 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-03-16 22:51 UTC (permalink / raw)
To: Harish Chegondi; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2425 bytes --]
== Series Details ==
Series: series starting with [v2,1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
URL : https://patchwork.freedesktop.org/series/163306/
State : success
== Summary ==
CI Bug Log - changes from xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820_BAT -> xe-pw-163306v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 14)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-163306v1_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- bat-adlp-7: [PASS][1] -> [DMESG-WARN][2] ([Intel XE#7483])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
* igt@xe_waitfence@reltime:
- bat-bmg-1: [PASS][3] -> [FAIL][4] ([Intel XE#6520])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/bat-bmg-1/igt@xe_waitfence@reltime.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/bat-bmg-1/igt@xe_waitfence@reltime.html
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1:
- bat-adlp-7: [DMESG-WARN][5] ([Intel XE#7483]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
[Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520
[Intel XE#7483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7483
Build changes
-------------
* IGT: IGT_8805 -> IGT_8806
* Linux: xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820 -> xe-pw-163306v1
IGT_8805: 8805
IGT_8806: 8806
xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820: a25d8c583e1e52bde77d371081a7c3fcd0a2e820
xe-pw-163306v1: 163306v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/index.html
[-- Attachment #2: Type: text/html, Size: 3136 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Xe.CI.FULL: failure for series starting with [v2,1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-16 17:58 [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset Harish Chegondi
2026-03-16 22:04 ` ✓ CI.KUnit: success for series starting with [v2,1/1] " Patchwork
2026-03-16 22:51 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-03-17 23:24 ` Patchwork
2026-03-18 6:57 ` [PATCH v2 1/1] " Dixit, Ashutosh
3 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2026-03-17 23:24 UTC (permalink / raw)
To: Harish Chegondi; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 57633 bytes --]
== Series Details ==
Series: series starting with [v2,1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
URL : https://patchwork.freedesktop.org/series/163306/
State : failure
== Summary ==
CI Bug Log - changes from xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820_FULL -> xe-pw-163306v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-163306v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-163306v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-163306v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
- shard-bmg: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-7/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
#### Warnings ####
* igt@kms_vrr@lobf@pipe-a-edp-1:
- shard-lnl: [FAIL][3] ([Intel XE#6390] / [Intel XE#7461]) -> [SKIP][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-lnl-3/igt@kms_vrr@lobf@pipe-a-edp-1.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-2/igt@kms_vrr@lobf@pipe-a-edp-1.html
Known issues
------------
Here are the changes found in xe-pw-163306v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
- shard-bmg: NOTRUN -> [SKIP][5] ([Intel XE#7059] / [Intel XE#7085])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#1124]) +2 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180.html
- shard-lnl: NOTRUN -> [SKIP][7] ([Intel XE#1124])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#607] / [Intel XE#7361])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#2314] / [Intel XE#2894] / [Intel XE#7373])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-1-displays-3840x2160p:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#367] / [Intel XE#7354])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2:
- shard-bmg: NOTRUN -> [INCOMPLETE][11] ([Intel XE#7084])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#2887]) +4 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
- shard-lnl: NOTRUN -> [SKIP][13] ([Intel XE#2887])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-a-hdmi-a-3:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2652]) +11 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-a-hdmi-a-3.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2325] / [Intel XE#7358])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@kms_chamelium_color@ctm-0-25.html
- shard-lnl: NOTRUN -> [SKIP][16] ([Intel XE#306] / [Intel XE#7358])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-4/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
- shard-bmg: NOTRUN -> [SKIP][17] ([Intel XE#2252]) +4 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html
* igt@kms_chamelium_hpd@hdmi-hpd:
- shard-lnl: NOTRUN -> [SKIP][18] ([Intel XE#373]) +1 other test skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-3/igt@kms_chamelium_hpd@hdmi-hpd.html
* igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][19] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2.html
* igt@kms_content_protection@srm:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#2341])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-onscreen-64x21:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2320])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-7/igt@kms_cursor_crc@cursor-onscreen-64x21.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2291] / [Intel XE#7343])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2286] / [Intel XE#6035])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
- shard-bmg: [PASS][24] -> [SKIP][25] ([Intel XE#2316]) +4 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-lnl: NOTRUN -> [SKIP][26] ([Intel XE#1421])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-3/igt@kms_flip@2x-plain-flip-ts-check.html
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#2316])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-lnl: [PASS][28] -> [FAIL][29] ([Intel XE#301])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-lnl: [PASS][30] -> [FAIL][31] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling:
- shard-lnl: NOTRUN -> [SKIP][33] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-4/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#1397] / [Intel XE#7385])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-4/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2311]) +9 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#4141]) +3 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][37] ([Intel XE#656]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#2312])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#6312] / [Intel XE#651]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#2313]) +11 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#2352] / [Intel XE#7399])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#7061] / [Intel XE#7356])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc.html
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#7061] / [Intel XE#7356])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-3/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc.html
* igt@kms_hdr@static-toggle-dpms:
- shard-bmg: [PASS][44] -> [SKIP][45] ([Intel XE#1503])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-4/igt@kms_hdr@static-toggle-dpms.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier:
- shard-lnl: NOTRUN -> [SKIP][46] ([Intel XE#7283])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-3/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier.html
* igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#7283]) +1 other test skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-bmg: [PASS][48] -> [SKIP][49] ([Intel XE#4596])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-10/igt@kms_plane_multiple@2x-tiling-x.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c:
- shard-bmg: NOTRUN -> [SKIP][50] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c.html
* igt@kms_pm_dc@dc5-psr:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#2392] / [Intel XE#6927])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf:
- shard-bmg: NOTRUN -> [SKIP][53] ([Intel XE#1489]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#1128] / [Intel XE#7413])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-6/igt@kms_psr2_su@page_flip-nv12.html
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#2387] / [Intel XE#7429])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-psr-sprite-plane-move:
- shard-bmg: NOTRUN -> [SKIP][56] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@kms_psr@fbc-psr-sprite-plane-move.html
* igt@kms_setmode@basic:
- shard-bmg: [PASS][57] -> [FAIL][58] ([Intel XE#6361]) +2 other tests fail
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-7/igt@kms_setmode@basic.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-10/igt@kms_setmode@basic.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-bmg: [PASS][59] -> [SKIP][60] ([Intel XE#1435])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-4/igt@kms_setmode@clone-exclusive-crtc.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_sharpness_filter@filter-basic:
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#6503]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-7/igt@kms_sharpness_filter@filter-basic.html
* igt@kms_vrr@max-min@pipe-a-edp-1:
- shard-lnl: [PASS][62] -> [FAIL][63] ([Intel XE#4227]) +1 other test fail
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-lnl-8/igt@kms_vrr@max-min@pipe-a-edp-1.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-3/igt@kms_vrr@max-min@pipe-a-edp-1.html
* igt@xe_eudebug@basic-vm-access-parameters:
- shard-bmg: NOTRUN -> [SKIP][64] ([Intel XE#4837]) +2 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@xe_eudebug@basic-vm-access-parameters.html
* igt@xe_eudebug@multiple-sessions:
- shard-lnl: NOTRUN -> [SKIP][65] ([Intel XE#4837])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-5/igt@xe_eudebug@multiple-sessions.html
* igt@xe_eudebug_online@set-breakpoint-faultable:
- shard-bmg: NOTRUN -> [SKIP][66] ([Intel XE#4837] / [Intel XE#6665]) +2 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@xe_eudebug_online@set-breakpoint-faultable.html
* igt@xe_evict@evict-beng-cm-threads-small-multi-vm:
- shard-lnl: NOTRUN -> [SKIP][67] ([Intel XE#6540] / [Intel XE#688]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-8/igt@xe_evict@evict-beng-cm-threads-small-multi-vm.html
* igt@xe_evict@evict-cm-threads-small-multi-queue:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#7140])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@xe_evict@evict-cm-threads-small-multi-queue.html
* igt@xe_exec_balancer@once-cm-parallel-userptr-rebind:
- shard-lnl: NOTRUN -> [SKIP][69] ([Intel XE#7482])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-6/igt@xe_exec_balancer@once-cm-parallel-userptr-rebind.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind:
- shard-bmg: NOTRUN -> [SKIP][70] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
- shard-lnl: NOTRUN -> [SKIP][71] ([Intel XE#1392])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind-prefetch:
- shard-lnl: NOTRUN -> [SKIP][72] ([Intel XE#7136]) +1 other test skip
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-5/igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind-prefetch.html
* igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind-prefetch:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#7136]) +4 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@xe_exec_fault_mode@twice-multi-queue-userptr-rebind-prefetch.html
* igt@xe_exec_multi_queue@exec-sanity:
- shard-lnl: NOTRUN -> [SKIP][74] ([Intel XE#6874]) +3 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-8/igt@xe_exec_multi_queue@exec-sanity.html
* igt@xe_exec_multi_queue@two-queues-priority:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#6874]) +15 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-2/igt@xe_exec_multi_queue@two-queues-priority.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
- shard-lnl: [PASS][76] -> [FAIL][77] ([Intel XE#5625])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-4/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
* igt@xe_exec_threads@threads-multi-queue-fd-userptr-invalidate-race:
- shard-bmg: NOTRUN -> [SKIP][78] ([Intel XE#7138]) +4 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-fd-userptr-invalidate-race.html
* igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-rebind:
- shard-lnl: NOTRUN -> [SKIP][79] ([Intel XE#7138])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-3/igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-rebind.html
* igt@xe_multigpu_svm@mgpu-atomic-op-prefetch:
- shard-bmg: NOTRUN -> [SKIP][80] ([Intel XE#6964])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@xe_multigpu_svm@mgpu-atomic-op-prefetch.html
- shard-lnl: NOTRUN -> [SKIP][81] ([Intel XE#6964])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-8/igt@xe_multigpu_svm@mgpu-atomic-op-prefetch.html
* igt@xe_sriov_admin@bulk-preempt-timeout-vfs-disabled:
- shard-lnl: NOTRUN -> [SKIP][82] ([Intel XE#7174])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-6/igt@xe_sriov_admin@bulk-preempt-timeout-vfs-disabled.html
* igt@xe_sriov_flr@flr-vf1-clear:
- shard-bmg: [PASS][83] -> [FAIL][84] ([Intel XE#6569]) +1 other test fail
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-9/igt@xe_sriov_flr@flr-vf1-clear.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@xe_sriov_flr@flr-vf1-clear.html
* igt@xe_survivability@i2c-functionality:
- shard-lnl: NOTRUN -> [SKIP][85] ([Intel XE#6529] / [Intel XE#7331] / [Intel XE#7388])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-6/igt@xe_survivability@i2c-functionality.html
* igt@xe_vm@out-of-memory:
- shard-lnl: NOTRUN -> [SKIP][86] ([Intel XE#5745])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-4/igt@xe_vm@out-of-memory.html
* igt@xe_waitfence@engine:
- shard-bmg: [PASS][87] -> [FAIL][88] ([Intel XE#6519])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-10/igt@xe_waitfence@engine.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@xe_waitfence@engine.html
#### Possible fixes ####
* igt@core_setmaster@master-drop-set-root:
- shard-bmg: [FAIL][89] -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@core_setmaster@master-drop-set-root.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@core_setmaster@master-drop-set-root.html
* igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
- shard-bmg: [SKIP][91] ([Intel XE#2314] / [Intel XE#2894] / [Intel XE#7373]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
* igt@kms_cursor_crc@cursor-suspend:
- shard-bmg: [INCOMPLETE][93] -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-5/igt@kms_cursor_crc@cursor-suspend.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-10/igt@kms_cursor_crc@cursor-suspend.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-bmg: [SKIP][95] ([Intel XE#2291]) -> [PASS][96] +2 other tests pass
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-5/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-2/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-bmg: [SKIP][97] ([Intel XE#2316]) -> [PASS][98] +2 other tests pass
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-5/igt@kms_flip@2x-flip-vs-panning.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@a-dp2:
- shard-bmg: [FAIL][99] ([Intel XE#3098]) -> [PASS][100] +1 other test pass
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-10/igt@kms_flip@flip-vs-absolute-wf_vblank@a-dp2.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@kms_flip@flip-vs-absolute-wf_vblank@a-dp2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-lnl: [FAIL][101] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a3:
- shard-bmg: [INCOMPLETE][103] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][104] +1 other test pass
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-10/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-bmg: [SKIP][105] ([Intel XE#1435]) -> [PASS][106] +1 other test pass
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-5/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
- shard-lnl: [FAIL][107] ([Intel XE#2142]) -> [PASS][108] +1 other test pass
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-lnl-7/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][109] ([Intel XE#6321]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-8/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_evict@evict-cm-threads-small:
- shard-bmg: [INCOMPLETE][111] ([Intel XE#2594]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-4/igt@xe_evict@evict-cm-threads-small.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-10/igt@xe_evict@evict-cm-threads-small.html
* igt@xe_exec_balancer@many-execqueues-cm-virtual-userptr-rebind:
- shard-bmg: [SKIP][113] ([Intel XE#6703]) -> [PASS][114] +118 other tests pass
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@xe_exec_balancer@many-execqueues-cm-virtual-userptr-rebind.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-2/igt@xe_exec_balancer@many-execqueues-cm-virtual-userptr-rebind.html
* igt@xe_exec_system_allocator@process-many-large-new-nomemset:
- shard-bmg: [SKIP][115] ([Intel XE#6557] / [Intel XE#6703]) -> [PASS][116] +1 other test pass
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@xe_exec_system_allocator@process-many-large-new-nomemset.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@xe_exec_system_allocator@process-many-large-new-nomemset.html
#### Warnings ####
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-bmg: [SKIP][117] ([Intel XE#6703]) -> [SKIP][118] ([Intel XE#2327]) +1 other test skip
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_big_fb@linear-8bpp-rotate-90.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-bmg: [SKIP][119] ([Intel XE#6703]) -> [SKIP][120] ([Intel XE#1124]) +2 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_ccs@bad-pixel-format-y-tiled-ccs:
- shard-bmg: [SKIP][121] ([Intel XE#6703]) -> [SKIP][122] ([Intel XE#2887])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_ccs@bad-pixel-format-y-tiled-ccs.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@kms_ccs@bad-pixel-format-y-tiled-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [SKIP][123] ([Intel XE#6703]) -> [INCOMPLETE][124] ([Intel XE#7084])
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-bmg: [SKIP][125] ([Intel XE#6703]) -> [SKIP][126] ([Intel XE#2652]) +1 other test skip
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-2/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-bmg: [SKIP][127] ([Intel XE#6703]) -> [SKIP][128] ([Intel XE#2252])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_chamelium_frames@hdmi-crc-fast.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_content_protection@legacy-hdcp14:
- shard-bmg: [FAIL][129] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) -> [SKIP][130] ([Intel XE#7194])
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-7/igt@kms_content_protection@legacy-hdcp14.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_content_protection@legacy-hdcp14.html
* igt@kms_content_protection@lic-type-0-hdcp14:
- shard-bmg: [SKIP][131] ([Intel XE#7194]) -> [FAIL][132] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-5/igt@kms_content_protection@lic-type-0-hdcp14.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_content_protection@lic-type-0-hdcp14.html
* igt@kms_feature_discovery@psr2:
- shard-bmg: [SKIP][133] ([Intel XE#6703]) -> [SKIP][134] ([Intel XE#2374] / [Intel XE#6128])
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_feature_discovery@psr2.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-9/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [FAIL][135] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][136] ([Intel XE#301])
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x:
- shard-bmg: [SKIP][137] ([Intel XE#6703]) -> [SKIP][138] ([Intel XE#7179])
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_flip_scaled_crc@flip-p016-linear-to-p016-linear-reflect-x.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][139] ([Intel XE#6703]) -> [SKIP][140] ([Intel XE#2311]) +2 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][141] ([Intel XE#6703]) -> [SKIP][142] ([Intel XE#4141]) +1 other test skip
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][143] ([Intel XE#4141]) -> [SKIP][144] ([Intel XE#2312]) +1 other test skip
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][145] ([Intel XE#2312]) -> [SKIP][146] ([Intel XE#4141]) +1 other test skip
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][147] ([Intel XE#6703]) -> [SKIP][148] ([Intel XE#2312]) +1 other test skip
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
- shard-bmg: [SKIP][149] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][150] ([Intel XE#4141])
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][151] ([Intel XE#2311]) -> [SKIP][152] ([Intel XE#2312]) +7 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt:
- shard-bmg: [SKIP][153] ([Intel XE#2312]) -> [SKIP][154] ([Intel XE#2311]) +5 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][155] ([Intel XE#2313]) -> [SKIP][156] ([Intel XE#2312]) +6 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][157] ([Intel XE#6703]) -> [SKIP][158] ([Intel XE#2313]) +5 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][159] ([Intel XE#2312]) -> [SKIP][160] ([Intel XE#2313]) +5 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-mmap-wc:
- shard-bmg: [SKIP][161] ([Intel XE#6703]) -> [SKIP][162] ([Intel XE#7061] / [Intel XE#7356])
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-mmap-wc.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-mmap-wc.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-bmg: [SKIP][163] ([Intel XE#6703]) -> [SKIP][164] ([Intel XE#6911] / [Intel XE#7378])
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_joiner@invalid-modeset-ultra-joiner.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier-source-clamping:
- shard-bmg: [SKIP][165] ([Intel XE#6703]) -> [SKIP][166] ([Intel XE#7283])
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier-source-clamping.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier-source-clamping.html
* igt@kms_pm_dc@dc6-psr:
- shard-bmg: [SKIP][167] ([Intel XE#6703]) -> [SKIP][168] ([Intel XE#2392] / [Intel XE#6927])
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_pm_dc@dc6-psr.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_pm_dc@dc6-psr.html
* igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
- shard-bmg: [SKIP][169] ([Intel XE#6703]) -> [SKIP][170] ([Intel XE#1489])
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr@fbc-pr-sprite-blt:
- shard-bmg: [SKIP][171] ([Intel XE#6703]) -> [SKIP][172] ([Intel XE#2234] / [Intel XE#2850])
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_psr@fbc-pr-sprite-blt.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@kms_psr@fbc-pr-sprite-blt.html
* igt@kms_psr@psr2-primary-render:
- shard-bmg: [SKIP][173] ([Intel XE#6703]) -> [SKIP][174] ([Intel XE#2234])
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_psr@psr2-primary-render.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-4/igt@kms_psr@psr2-primary-render.html
* igt@kms_sharpness_filter@filter-toggle:
- shard-bmg: [SKIP][175] ([Intel XE#6703]) -> [SKIP][176] ([Intel XE#6503])
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_sharpness_filter@filter-toggle.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_sharpness_filter@filter-toggle.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][177] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][178] ([Intel XE#1729] / [Intel XE#7424])
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tv_load_detect@load-detect:
- shard-bmg: [SKIP][179] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][180] ([Intel XE#2450] / [Intel XE#5857])
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@kms_tv_load_detect@load-detect.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-8/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vrr@lobf:
- shard-lnl: [FAIL][181] ([Intel XE#6390] / [Intel XE#7461]) -> [SKIP][182] ([Intel XE#1499])
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-lnl-3/igt@kms_vrr@lobf.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-lnl-2/igt@kms_vrr@lobf.html
* igt@xe_eudebug@basic-vm-bind-ufence-delay-ack:
- shard-bmg: [SKIP][183] ([Intel XE#6703]) -> [SKIP][184] ([Intel XE#4837]) +1 other test skip
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@xe_eudebug@basic-vm-bind-ufence-delay-ack.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-7/igt@xe_eudebug@basic-vm-bind-ufence-delay-ack.html
* igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram:
- shard-bmg: [SKIP][185] ([Intel XE#6703]) -> [SKIP][186] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate:
- shard-bmg: [SKIP][187] ([Intel XE#6703]) -> [SKIP][188] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate.html
* igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind:
- shard-bmg: [SKIP][189] ([Intel XE#6703]) -> [SKIP][190] ([Intel XE#7136]) +1 other test skip
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind.html
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind.html
* igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd-smem:
- shard-bmg: [SKIP][191] ([Intel XE#6703]) -> [SKIP][192] ([Intel XE#6874]) +6 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd-smem.html
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-9/igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd-smem.html
* igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr:
- shard-bmg: [SKIP][193] ([Intel XE#6703]) -> [SKIP][194] ([Intel XE#7138]) +2 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr.html
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr.html
* igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq:
- shard-bmg: [SKIP][195] ([Intel XE#6703]) -> [SKIP][196] ([Intel XE#4733] / [Intel XE#7417])
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-5/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html
* igt@xe_query@multigpu-query-uc-fw-version-guc:
- shard-bmg: [SKIP][197] ([Intel XE#6703]) -> [SKIP][198] ([Intel XE#944])
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820/shard-bmg-2/igt@xe_query@multigpu-query-uc-fw-version-guc.html
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/shard-bmg-9/igt@xe_query@multigpu-query-uc-fw-version-guc.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
[Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
[Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
[Intel XE#5745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5745
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#5857]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5857
[Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6128
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6361
[Intel XE#6390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6390
[Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
[Intel XE#6529]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6529
[Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
[Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
[Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
[Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
[Intel XE#6927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6927
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
[Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
[Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
[Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
[Intel XE#7194]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7194
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7331
[Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7373
[Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
[Intel XE#7378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7378
[Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
[Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
[Intel XE#7388]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7388
[Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
[Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
[Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
[Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
[Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
[Intel XE#7461]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7461
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_8805 -> IGT_8806
* Linux: xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820 -> xe-pw-163306v1
IGT_8805: 8805
IGT_8806: 8806
xe-4731-a25d8c583e1e52bde77d371081a7c3fcd0a2e820: a25d8c583e1e52bde77d371081a7c3fcd0a2e820
xe-pw-163306v1: 163306v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163306v1/index.html
[-- Attachment #2: Type: text/html, Size: 68252 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-16 17:58 [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset Harish Chegondi
` (2 preceding siblings ...)
2026-03-17 23:24 ` ✗ Xe.CI.FULL: failure " Patchwork
@ 2026-03-18 6:57 ` Dixit, Ashutosh
2026-03-18 16:59 ` Cabral, Matias A
2026-03-18 21:30 ` Harish Chegondi
3 siblings, 2 replies; 13+ messages in thread
From: Dixit, Ashutosh @ 2026-03-18 6:57 UTC (permalink / raw)
To: Harish Chegondi
Cc: intel-xe, felix.j.degrood, matias.a.cabral, joshua.santosh.ranjan
On Mon, 16 Mar 2026 10:58:56 -0700, Harish Chegondi wrote:
>
> If a reset (GT or engine) happens during EU stall data sampling, all the
> EU stall registers can get reset to 0. This will result in EU stall data
> buffers' read and write pointer register values to be out of sync with
> the cached values. This will result in read() returning invalid data. To
> prevent this, check the value of a EU stall base register. If it is zero,
> it indicates a reset may have happened that wiped the register to zero.
> If this happens, return EBADFD from read() upon which the user space
> should close the fd and open a new fd for a new EU stall data
> collection session.
>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> ---
> v2: Move base register check from read to the poll function
>
> drivers/gpu/drm/xe/xe_eu_stall.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
> index c34408cfd292..7e14de73a2c9 100644
> --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> @@ -44,6 +44,7 @@ struct per_xecore_buf {
> struct xe_eu_stall_data_stream {
> bool pollin;
> bool enabled;
> + bool reset_detected;
> int wait_num_reports;
> int sampling_rate_mult;
> wait_queue_head_t poll_wq;
> @@ -428,6 +429,17 @@ static bool eu_stall_data_buf_poll(struct xe_eu_stall_data_stream *stream)
> set_bit(xecore, stream->data_drop.mask);
> xecore_buf->write = write_ptr;
> }
> + /* If a GT or engine reset happens during EU stall sampling,
> + * all EU stall registers get reset to 0 and the cached values of
> + * the EU stall data buffers' read pointers are out of sync with
> + * the register values. This causes invalid data to be returned
> + * from read(). To prevent this, check the value of a EU stall base
> + * register. If it is zero, there has been a reset.
> + */
As previously discussed, the best way would have been to not have to do
this. We would just plug into the handler for the reset message from GuC,
rather than to implement a reset detection here (and in other places such
as OA). But looks like if we do that, because of the way EUSS registers are
reset, we can return bad EUSS data. So looks like there is no way around
doing this "reset detection" here and a solution with the GuC reset handler
would always be racy. Just for the record.
> + if (unlikely(!xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE))) {
> + stream->reset_detected = true;
> + min_data_present = true;
I don't believe we need to set 'min_data_present = true' if we are setting
'stream->reset_detected = true', correct? See if statement at the bottom.
Also, since the write pointer itself gets reset during reset, didn't we
want to do this register read only when the write pointer is 0 (to avoid an
extra register read every 5 ms)?
> + }
> mutex_unlock(&stream->xecore_buf_lock);
>
> return min_data_present;
> @@ -554,6 +566,15 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
> }
> stream->data_drop.reported_to_user = false;
> }
> + /* If EU stall registers got reset due to a GT/engine reset,
> + * continuing with the read() will return invalid data to
> + * the user space. Just return -EBADFD instead.
> + */
> + if (unlikely(stream->reset_detected)) {
> + xe_gt_dbg(gt, "EU stall base register has been reset\n");
> + mutex_unlock(&stream->xecore_buf_lock);
> + return -EBADFD;
The other option is to return -EIO here and implement
DRM_XE_OBSERVATION_IOCTL_STATUS and return status from that. Let me think
some more about this.
> + }
>
> for_each_dss_steering(xecore, gt, group, instance) {
> ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size,
> @@ -692,6 +713,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> xecore_buf->write = write_ptr;
> xecore_buf->read = write_ptr;
> }
> + stream->reset_detected = false;
So after reset, if a stream is disabled and re-enabled, we expect things to
work again and EUSS data to be correct (without re-opening a new stream)?
> stream->data_drop.reported_to_user = false;
> bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
>
> @@ -717,7 +739,7 @@ static void eu_stall_data_buf_poll_work_fn(struct work_struct *work)
> container_of(work, typeof(*stream), buf_poll_work.work);
> struct xe_gt *gt = stream->gt;
>
> - if (eu_stall_data_buf_poll(stream)) {
> + if (stream->reset_detected || eu_stall_data_buf_poll(stream)) {
> stream->pollin = true;
> wake_up(&stream->poll_wq);
> }
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-18 6:57 ` [PATCH v2 1/1] " Dixit, Ashutosh
@ 2026-03-18 16:59 ` Cabral, Matias A
2026-03-18 18:38 ` Cabral, Matias A
2026-03-18 21:36 ` Harish Chegondi
2026-03-18 21:30 ` Harish Chegondi
1 sibling, 2 replies; 13+ messages in thread
From: Cabral, Matias A @ 2026-03-18 16:59 UTC (permalink / raw)
To: Dixit, Ashutosh, Chegondi, Harish
Cc: intel-xe@lists.freedesktop.org, Degrood, Felix J,
Ranjan, Joshua Santhosh
Hi Harish,
> return -EBADFD;
Is this making the read() syscall return -EBADFD or setting erno to EBADFD ? would like to clearly understand how to detect this condition in the UMD.
Thanks,
_Matias
-----Original Message-----
From: Dixit, Ashutosh <ashutosh.dixit@intel.com>
Sent: Tuesday, March 17, 2026 11:58 PM
To: Chegondi, Harish <harish.chegondi@intel.com>
Cc: intel-xe@lists.freedesktop.org; Degrood, Felix J <felix.j.degrood@intel.com>; Cabral, Matias A <matias.a.cabral@intel.com>; Ranjan, Joshua Santhosh <joshua.santosh.ranjan@intel.com>
Subject: Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
On Mon, 16 Mar 2026 10:58:56 -0700, Harish Chegondi wrote:
>
> If a reset (GT or engine) happens during EU stall data sampling, all
> the EU stall registers can get reset to 0. This will result in EU
> stall data buffers' read and write pointer register values to be out
> of sync with the cached values. This will result in read() returning
> invalid data. To prevent this, check the value of a EU stall base
> register. If it is zero, it indicates a reset may have happened that wiped the register to zero.
> If this happens, return EBADFD from read() upon which the user space
> should close the fd and open a new fd for a new EU stall data
> collection session.
>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> ---
> v2: Move base register check from read to the poll function
>
> drivers/gpu/drm/xe/xe_eu_stall.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c
> b/drivers/gpu/drm/xe/xe_eu_stall.c
> index c34408cfd292..7e14de73a2c9 100644
> --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> @@ -44,6 +44,7 @@ struct per_xecore_buf {
> struct xe_eu_stall_data_stream {
> bool pollin;
> bool enabled;
> + bool reset_detected;
> int wait_num_reports;
> int sampling_rate_mult;
> wait_queue_head_t poll_wq;
> @@ -428,6 +429,17 @@ static bool eu_stall_data_buf_poll(struct xe_eu_stall_data_stream *stream)
> set_bit(xecore, stream->data_drop.mask);
> xecore_buf->write = write_ptr;
> }
> + /* If a GT or engine reset happens during EU stall sampling,
> + * all EU stall registers get reset to 0 and the cached values of
> + * the EU stall data buffers' read pointers are out of sync with
> + * the register values. This causes invalid data to be returned
> + * from read(). To prevent this, check the value of a EU stall base
> + * register. If it is zero, there has been a reset.
> + */
As previously discussed, the best way would have been to not have to do this. We would just plug into the handler for the reset message from GuC, rather than to implement a reset detection here (and in other places such as OA). But looks like if we do that, because of the way EUSS registers are reset, we can return bad EUSS data. So looks like there is no way around doing this "reset detection" here and a solution with the GuC reset handler would always be racy. Just for the record.
> + if (unlikely(!xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE))) {
> + stream->reset_detected = true;
> + min_data_present = true;
I don't believe we need to set 'min_data_present = true' if we are setting 'stream->reset_detected = true', correct? See if statement at the bottom.
Also, since the write pointer itself gets reset during reset, didn't we want to do this register read only when the write pointer is 0 (to avoid an extra register read every 5 ms)?
> + }
> mutex_unlock(&stream->xecore_buf_lock);
>
> return min_data_present;
> @@ -554,6 +566,15 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
> }
> stream->data_drop.reported_to_user = false;
> }
> + /* If EU stall registers got reset due to a GT/engine reset,
> + * continuing with the read() will return invalid data to
> + * the user space. Just return -EBADFD instead.
> + */
> + if (unlikely(stream->reset_detected)) {
> + xe_gt_dbg(gt, "EU stall base register has been reset\n");
> + mutex_unlock(&stream->xecore_buf_lock);
> + return -EBADFD;
The other option is to return -EIO here and implement DRM_XE_OBSERVATION_IOCTL_STATUS and return status from that. Let me think some more about this.
> + }
>
> for_each_dss_steering(xecore, gt, group, instance) {
> ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size, @@
>-692,6 +713,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> xecore_buf->write = write_ptr;
> xecore_buf->read = write_ptr;
> }
> + stream->reset_detected = false;
So after reset, if a stream is disabled and re-enabled, we expect things to work again and EUSS data to be correct (without re-opening a new stream)?
> stream->data_drop.reported_to_user = false;
> bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
>
> @@ -717,7 +739,7 @@ static void eu_stall_data_buf_poll_work_fn(struct work_struct *work)
> container_of(work, typeof(*stream), buf_poll_work.work);
> struct xe_gt *gt = stream->gt;
>
> - if (eu_stall_data_buf_poll(stream)) {
> + if (stream->reset_detected || eu_stall_data_buf_poll(stream)) {
> stream->pollin = true;
> wake_up(&stream->poll_wq);
> }
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-18 16:59 ` Cabral, Matias A
@ 2026-03-18 18:38 ` Cabral, Matias A
2026-03-20 18:35 ` Harish Chegondi
2026-03-18 21:36 ` Harish Chegondi
1 sibling, 1 reply; 13+ messages in thread
From: Cabral, Matias A @ 2026-03-18 18:38 UTC (permalink / raw)
To: Dixit, Ashutosh, Chegondi, Harish
Cc: intel-xe@lists.freedesktop.org, Degrood, Felix J,
Ranjan, Joshua Santhosh
Second question: in this condition would require a new return error from the UMD read() API telling the consumer a catastrophic error happened and the streamer must be closed, right ?
Thanks,
_Matias
-----Original Message-----
From: Cabral, Matias A
Sent: Wednesday, March 18, 2026 9:59 AM
To: Dixit, Ashutosh <ashutosh.dixit@intel.com>; Chegondi, Harish <harish.chegondi@intel.com>
Cc: intel-xe@lists.freedesktop.org; Degrood, Felix J <felix.j.degrood@intel.com>; Ranjan, Joshua Santhosh <joshua.santosh.ranjan@intel.com>
Subject: RE: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
Hi Harish,
> return -EBADFD;
Is this making the read() syscall return -EBADFD or setting erno to EBADFD ? would like to clearly understand how to detect this condition in the UMD.
Thanks,
_Matias
-----Original Message-----
From: Dixit, Ashutosh <ashutosh.dixit@intel.com>
Sent: Tuesday, March 17, 2026 11:58 PM
To: Chegondi, Harish <harish.chegondi@intel.com>
Cc: intel-xe@lists.freedesktop.org; Degrood, Felix J <felix.j.degrood@intel.com>; Cabral, Matias A <matias.a.cabral@intel.com>; Ranjan, Joshua Santhosh <joshua.santosh.ranjan@intel.com>
Subject: Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
On Mon, 16 Mar 2026 10:58:56 -0700, Harish Chegondi wrote:
>
> If a reset (GT or engine) happens during EU stall data sampling, all
> the EU stall registers can get reset to 0. This will result in EU
> stall data buffers' read and write pointer register values to be out
> of sync with the cached values. This will result in read() returning
> invalid data. To prevent this, check the value of a EU stall base
> register. If it is zero, it indicates a reset may have happened that wiped the register to zero.
> If this happens, return EBADFD from read() upon which the user space
> should close the fd and open a new fd for a new EU stall data
> collection session.
>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> ---
> v2: Move base register check from read to the poll function
>
> drivers/gpu/drm/xe/xe_eu_stall.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c
> b/drivers/gpu/drm/xe/xe_eu_stall.c
> index c34408cfd292..7e14de73a2c9 100644
> --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> @@ -44,6 +44,7 @@ struct per_xecore_buf {
> struct xe_eu_stall_data_stream {
> bool pollin;
> bool enabled;
> + bool reset_detected;
> int wait_num_reports;
> int sampling_rate_mult;
> wait_queue_head_t poll_wq;
> @@ -428,6 +429,17 @@ static bool eu_stall_data_buf_poll(struct xe_eu_stall_data_stream *stream)
> set_bit(xecore, stream->data_drop.mask);
> xecore_buf->write = write_ptr;
> }
> + /* If a GT or engine reset happens during EU stall sampling,
> + * all EU stall registers get reset to 0 and the cached values of
> + * the EU stall data buffers' read pointers are out of sync with
> + * the register values. This causes invalid data to be returned
> + * from read(). To prevent this, check the value of a EU stall base
> + * register. If it is zero, there has been a reset.
> + */
As previously discussed, the best way would have been to not have to do this. We would just plug into the handler for the reset message from GuC, rather than to implement a reset detection here (and in other places such as OA). But looks like if we do that, because of the way EUSS registers are reset, we can return bad EUSS data. So looks like there is no way around doing this "reset detection" here and a solution with the GuC reset handler would always be racy. Just for the record.
> + if (unlikely(!xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE))) {
> + stream->reset_detected = true;
> + min_data_present = true;
I don't believe we need to set 'min_data_present = true' if we are setting 'stream->reset_detected = true', correct? See if statement at the bottom.
Also, since the write pointer itself gets reset during reset, didn't we want to do this register read only when the write pointer is 0 (to avoid an extra register read every 5 ms)?
> + }
> mutex_unlock(&stream->xecore_buf_lock);
>
> return min_data_present;
> @@ -554,6 +566,15 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
> }
> stream->data_drop.reported_to_user = false;
> }
> + /* If EU stall registers got reset due to a GT/engine reset,
> + * continuing with the read() will return invalid data to
> + * the user space. Just return -EBADFD instead.
> + */
> + if (unlikely(stream->reset_detected)) {
> + xe_gt_dbg(gt, "EU stall base register has been reset\n");
> + mutex_unlock(&stream->xecore_buf_lock);
> + return -EBADFD;
The other option is to return -EIO here and implement DRM_XE_OBSERVATION_IOCTL_STATUS and return status from that. Let me think some more about this.
> + }
>
> for_each_dss_steering(xecore, gt, group, instance) {
> ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size, @@
>-692,6 +713,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> xecore_buf->write = write_ptr;
> xecore_buf->read = write_ptr;
> }
> + stream->reset_detected = false;
So after reset, if a stream is disabled and re-enabled, we expect things to work again and EUSS data to be correct (without re-opening a new stream)?
> stream->data_drop.reported_to_user = false;
> bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
>
> @@ -717,7 +739,7 @@ static void eu_stall_data_buf_poll_work_fn(struct work_struct *work)
> container_of(work, typeof(*stream), buf_poll_work.work);
> struct xe_gt *gt = stream->gt;
>
> - if (eu_stall_data_buf_poll(stream)) {
> + if (stream->reset_detected || eu_stall_data_buf_poll(stream)) {
> stream->pollin = true;
> wake_up(&stream->poll_wq);
> }
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-18 6:57 ` [PATCH v2 1/1] " Dixit, Ashutosh
2026-03-18 16:59 ` Cabral, Matias A
@ 2026-03-18 21:30 ` Harish Chegondi
2026-03-19 3:55 ` Dixit, Ashutosh
1 sibling, 1 reply; 13+ messages in thread
From: Harish Chegondi @ 2026-03-18 21:30 UTC (permalink / raw)
To: Dixit, Ashutosh
Cc: intel-xe, felix.j.degrood, matias.a.cabral, joshua.santosh.ranjan
On Tue, Mar 17, 2026 at 11:57:32PM -0700, Dixit, Ashutosh wrote:
> On Mon, 16 Mar 2026 10:58:56 -0700, Harish Chegondi wrote:
> >
> > If a reset (GT or engine) happens during EU stall data sampling, all the
> > EU stall registers can get reset to 0. This will result in EU stall data
> > buffers' read and write pointer register values to be out of sync with
> > the cached values. This will result in read() returning invalid data. To
> > prevent this, check the value of a EU stall base register. If it is zero,
> > it indicates a reset may have happened that wiped the register to zero.
> > If this happens, return EBADFD from read() upon which the user space
> > should close the fd and open a new fd for a new EU stall data
> > collection session.
> >
> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> > ---
> > v2: Move base register check from read to the poll function
> >
> > drivers/gpu/drm/xe/xe_eu_stall.c | 24 +++++++++++++++++++++++-
> > 1 file changed, 23 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
> > index c34408cfd292..7e14de73a2c9 100644
> > --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> > +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> > @@ -44,6 +44,7 @@ struct per_xecore_buf {
> > struct xe_eu_stall_data_stream {
> > bool pollin;
> > bool enabled;
> > + bool reset_detected;
> > int wait_num_reports;
> > int sampling_rate_mult;
> > wait_queue_head_t poll_wq;
> > @@ -428,6 +429,17 @@ static bool eu_stall_data_buf_poll(struct xe_eu_stall_data_stream *stream)
> > set_bit(xecore, stream->data_drop.mask);
> > xecore_buf->write = write_ptr;
> > }
> > + /* If a GT or engine reset happens during EU stall sampling,
> > + * all EU stall registers get reset to 0 and the cached values of
> > + * the EU stall data buffers' read pointers are out of sync with
> > + * the register values. This causes invalid data to be returned
> > + * from read(). To prevent this, check the value of a EU stall base
> > + * register. If it is zero, there has been a reset.
> > + */
>
> As previously discussed, the best way would have been to not have to do
> this. We would just plug into the handler for the reset message from GuC,
> rather than to implement a reset detection here (and in other places such
> as OA). But looks like if we do that, because of the way EUSS registers are
> reset, we can return bad EUSS data. So looks like there is no way around
> doing this "reset detection" here and a solution with the GuC reset handler
> would always be racy. Just for the record.
Thanks for the summary of the previous discussion. Yes, hooking into the
GUc reset notification handler will be racy and bad EUSS data will be
returned to the user space if read() happens after the reset but before
the GuC reset notification message is processed. That's the reason for
not taking that approach.
>
> > + if (unlikely(!xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE))) {
> > + stream->reset_detected = true;
> > + min_data_present = true;
>
> I don't believe we need to set 'min_data_present = true' if we are setting
> 'stream->reset_detected = true', correct? See if statement at the bottom.
Agree. The only difference is that the if statement at the bottom will
evaluate true in the current execution of eu_stall_data_buf_poll_work_fn
if min_data_present is set to true. If min_data_present is not set to
true, the if statement will evaluate to true in the subsequent execution
of eu_stall_data_buf_poll_work_fn() which is still okay. So, yes, we
don't have to set min_data_present to true here. Will fix in the next
version.
>
> Also, since the write pointer itself gets reset during reset, didn't we
> want to do this register read only when the write pointer is 0 (to avoid an
> extra register read every 5 ms)?
Good point. I have thought about reducing the number of this register
reads. The poll function reads the write pointers of all the xecores.
A reset can happen anytime the poll function is reading the write
pointers of the xecores. If the reset happens before the poll function
started reading the write pointers, all write pointers are zeros.
If the reset happens during the poll function, several write pointers
read so far can be non-zero while the rest of the pointers after reset
are all zeros. The if reset happens right after the poll function, the
write pointers can be a mix of zeros and non-zeros.
I think the only time this register read can be skipped is if the
LAST write pointer read is non-zero which means a reset did not happen
before or during the poll function. Do you agree? I thought of adding a
check to the if statement to check if the last write pointer is
non-zero, but to keep the code clean, I didn't. Also, if there are
n xecores, there will be n write pointer register reads plus one
additional base register read, which isn't too bad? Also, hoping the use
of unlikely macro would not impact the performance too much.
>
> > + }
> > mutex_unlock(&stream->xecore_buf_lock);
> >
> > return min_data_present;
> > @@ -554,6 +566,15 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
> > }
> > stream->data_drop.reported_to_user = false;
> > }
> > + /* If EU stall registers got reset due to a GT/engine reset,
> > + * continuing with the read() will return invalid data to
> > + * the user space. Just return -EBADFD instead.
> > + */
> > + if (unlikely(stream->reset_detected)) {
> > + xe_gt_dbg(gt, "EU stall base register has been reset\n");
> > + mutex_unlock(&stream->xecore_buf_lock);
> > + return -EBADFD;
>
> The other option is to return -EIO here and implement
> DRM_XE_OBSERVATION_IOCTL_STATUS and return status from that. Let me think
> some more about this.
I think EBADFD is more appropriate errno than EIO in this case since the
fd is in a corrupted state and user has to close and re-open the fd.
Currently, the -EIO is used to indicate drop data in which case, the
user space can continue to read the data (faster) without closing the fd.
>
> > + }
> >
> > for_each_dss_steering(xecore, gt, group, instance) {
> > ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size,
> > @@ -692,6 +713,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> > xecore_buf->write = write_ptr;
> > xecore_buf->read = write_ptr;
> > }
> > + stream->reset_detected = false;
>
> So after reset, if a stream is disabled and re-enabled, we expect things to
> work again and EUSS data to be correct (without re-opening a new stream)?
Technically, yes, since the EU stall registers programming is done in
enable, things will work again if the stream is disabled and re-enabled.
But if the EUSS registers programming is moved into open() in the
future, things may not work by disabling and re-enabling the stream. So,
I think we suggest to the UMDs to close the stream and open a new
stream.
Thank You
Harish.
>
> > stream->data_drop.reported_to_user = false;
> > bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
> >
> > @@ -717,7 +739,7 @@ static void eu_stall_data_buf_poll_work_fn(struct work_struct *work)
> > container_of(work, typeof(*stream), buf_poll_work.work);
> > struct xe_gt *gt = stream->gt;
> >
> > - if (eu_stall_data_buf_poll(stream)) {
> > + if (stream->reset_detected || eu_stall_data_buf_poll(stream)) {
> > stream->pollin = true;
> > wake_up(&stream->poll_wq);
> > }
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-18 16:59 ` Cabral, Matias A
2026-03-18 18:38 ` Cabral, Matias A
@ 2026-03-18 21:36 ` Harish Chegondi
1 sibling, 0 replies; 13+ messages in thread
From: Harish Chegondi @ 2026-03-18 21:36 UTC (permalink / raw)
To: Cabral, Matias A
Cc: Dixit, Ashutosh, intel-xe@lists.freedesktop.org, Degrood, Felix J,
Ranjan, Joshua Santhosh
On Wed, Mar 18, 2026 at 09:59:04AM -0700, Cabral, Matias A wrote:
Hi Matias,
For UMD, read() of EU stall stream would return -1 and errno will be EBADFD.
Thanks
Harish.
> Hi Harish,
>
> > return -EBADFD;
>
> Is this making the read() syscall return -EBADFD or setting erno to EBADFD ? would like to clearly understand how to detect this condition in the UMD.
>
> Thanks,
> _Matias
>
> -----Original Message-----
> From: Dixit, Ashutosh <ashutosh.dixit@intel.com>
> Sent: Tuesday, March 17, 2026 11:58 PM
> To: Chegondi, Harish <harish.chegondi@intel.com>
> Cc: intel-xe@lists.freedesktop.org; Degrood, Felix J <felix.j.degrood@intel.com>; Cabral, Matias A <matias.a.cabral@intel.com>; Ranjan, Joshua Santhosh <joshua.santosh.ranjan@intel.com>
> Subject: Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
>
> On Mon, 16 Mar 2026 10:58:56 -0700, Harish Chegondi wrote:
> >
> > If a reset (GT or engine) happens during EU stall data sampling, all
> > the EU stall registers can get reset to 0. This will result in EU
> > stall data buffers' read and write pointer register values to be out
> > of sync with the cached values. This will result in read() returning
> > invalid data. To prevent this, check the value of a EU stall base
> > register. If it is zero, it indicates a reset may have happened that wiped the register to zero.
> > If this happens, return EBADFD from read() upon which the user space
> > should close the fd and open a new fd for a new EU stall data
> > collection session.
> >
> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> > ---
> > v2: Move base register check from read to the poll function
> >
> > drivers/gpu/drm/xe/xe_eu_stall.c | 24 +++++++++++++++++++++++-
> > 1 file changed, 23 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c
> > b/drivers/gpu/drm/xe/xe_eu_stall.c
> > index c34408cfd292..7e14de73a2c9 100644
> > --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> > +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> > @@ -44,6 +44,7 @@ struct per_xecore_buf {
> > struct xe_eu_stall_data_stream {
> > bool pollin;
> > bool enabled;
> > + bool reset_detected;
> > int wait_num_reports;
> > int sampling_rate_mult;
> > wait_queue_head_t poll_wq;
> > @@ -428,6 +429,17 @@ static bool eu_stall_data_buf_poll(struct xe_eu_stall_data_stream *stream)
> > set_bit(xecore, stream->data_drop.mask);
> > xecore_buf->write = write_ptr;
> > }
> > + /* If a GT or engine reset happens during EU stall sampling,
> > + * all EU stall registers get reset to 0 and the cached values of
> > + * the EU stall data buffers' read pointers are out of sync with
> > + * the register values. This causes invalid data to be returned
> > + * from read(). To prevent this, check the value of a EU stall base
> > + * register. If it is zero, there has been a reset.
> > + */
>
> As previously discussed, the best way would have been to not have to do this. We would just plug into the handler for the reset message from GuC, rather than to implement a reset detection here (and in other places such as OA). But looks like if we do that, because of the way EUSS registers are reset, we can return bad EUSS data. So looks like there is no way around doing this "reset detection" here and a solution with the GuC reset handler would always be racy. Just for the record.
>
> > + if (unlikely(!xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE))) {
> > + stream->reset_detected = true;
> > + min_data_present = true;
>
> I don't believe we need to set 'min_data_present = true' if we are setting 'stream->reset_detected = true', correct? See if statement at the bottom.
>
> Also, since the write pointer itself gets reset during reset, didn't we want to do this register read only when the write pointer is 0 (to avoid an extra register read every 5 ms)?
>
> > + }
> > mutex_unlock(&stream->xecore_buf_lock);
> >
> > return min_data_present;
> > @@ -554,6 +566,15 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
> > }
> > stream->data_drop.reported_to_user = false;
> > }
> > + /* If EU stall registers got reset due to a GT/engine reset,
> > + * continuing with the read() will return invalid data to
> > + * the user space. Just return -EBADFD instead.
> > + */
> > + if (unlikely(stream->reset_detected)) {
> > + xe_gt_dbg(gt, "EU stall base register has been reset\n");
> > + mutex_unlock(&stream->xecore_buf_lock);
> > + return -EBADFD;
>
> The other option is to return -EIO here and implement DRM_XE_OBSERVATION_IOCTL_STATUS and return status from that. Let me think some more about this.
>
> > + }
> >
> > for_each_dss_steering(xecore, gt, group, instance) {
> > ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size, @@
> >-692,6 +713,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> > xecore_buf->write = write_ptr;
> > xecore_buf->read = write_ptr;
> > }
> > + stream->reset_detected = false;
>
> So after reset, if a stream is disabled and re-enabled, we expect things to work again and EUSS data to be correct (without re-opening a new stream)?
>
> > stream->data_drop.reported_to_user = false;
> > bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
> >
> > @@ -717,7 +739,7 @@ static void eu_stall_data_buf_poll_work_fn(struct work_struct *work)
> > container_of(work, typeof(*stream), buf_poll_work.work);
> > struct xe_gt *gt = stream->gt;
> >
> > - if (eu_stall_data_buf_poll(stream)) {
> > + if (stream->reset_detected || eu_stall_data_buf_poll(stream)) {
> > stream->pollin = true;
> > wake_up(&stream->poll_wq);
> > }
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-18 21:30 ` Harish Chegondi
@ 2026-03-19 3:55 ` Dixit, Ashutosh
2026-03-20 20:59 ` Harish Chegondi
0 siblings, 1 reply; 13+ messages in thread
From: Dixit, Ashutosh @ 2026-03-19 3:55 UTC (permalink / raw)
To: Harish Chegondi
Cc: intel-xe, felix.j.degrood, matias.a.cabral, joshua.santosh.ranjan
On Wed, 18 Mar 2026 14:30:06 -0700, Harish Chegondi wrote:
>
> On Tue, Mar 17, 2026 at 11:57:32PM -0700, Dixit, Ashutosh wrote:
> > On Mon, 16 Mar 2026 10:58:56 -0700, Harish Chegondi wrote:
> > >
> > > If a reset (GT or engine) happens during EU stall data sampling, all the
> > > EU stall registers can get reset to 0. This will result in EU stall data
> > > buffers' read and write pointer register values to be out of sync with
> > > the cached values. This will result in read() returning invalid data. To
> > > prevent this, check the value of a EU stall base register. If it is zero,
> > > it indicates a reset may have happened that wiped the register to zero.
> > > If this happens, return EBADFD from read() upon which the user space
> > > should close the fd and open a new fd for a new EU stall data
> > > collection session.
> > >
> > > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> > > ---
> > > v2: Move base register check from read to the poll function
> > >
> > > drivers/gpu/drm/xe/xe_eu_stall.c | 24 +++++++++++++++++++++++-
> > > 1 file changed, 23 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
> > > index c34408cfd292..7e14de73a2c9 100644
> > > --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> > > +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> > > @@ -44,6 +44,7 @@ struct per_xecore_buf {
> > > struct xe_eu_stall_data_stream {
> > > bool pollin;
> > > bool enabled;
> > > + bool reset_detected;
> > > int wait_num_reports;
> > > int sampling_rate_mult;
> > > wait_queue_head_t poll_wq;
> > > @@ -428,6 +429,17 @@ static bool eu_stall_data_buf_poll(struct xe_eu_stall_data_stream *stream)
> > > set_bit(xecore, stream->data_drop.mask);
> > > xecore_buf->write = write_ptr;
> > > }
> > > + /* If a GT or engine reset happens during EU stall sampling,
> > > + * all EU stall registers get reset to 0 and the cached values of
> > > + * the EU stall data buffers' read pointers are out of sync with
> > > + * the register values. This causes invalid data to be returned
> > > + * from read(). To prevent this, check the value of a EU stall base
> > > + * register. If it is zero, there has been a reset.
> > > + */
> >
> > As previously discussed, the best way would have been to not have to do
> > this. We would just plug into the handler for the reset message from GuC,
> > rather than to implement a reset detection here (and in other places such
> > as OA). But looks like if we do that, because of the way EUSS registers are
> > reset, we can return bad EUSS data. So looks like there is no way around
> > doing this "reset detection" here and a solution with the GuC reset handler
> > would always be racy. Just for the record.
>
> Thanks for the summary of the previous discussion. Yes, hooking into the
> GUc reset notification handler will be racy and bad EUSS data will be
> returned to the user space if read() happens after the reset but before
> the GuC reset notification message is processed. That's the reason for
> not taking that approach.
>
> >
> > > + if (unlikely(!xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE))) {
> > > + stream->reset_detected = true;
> > > + min_data_present = true;
> >
> > I don't believe we need to set 'min_data_present = true' if we are setting
> > 'stream->reset_detected = true', correct? See if statement at the bottom.
>
> Agree. The only difference is that the if statement at the bottom will
> evaluate true in the current execution of eu_stall_data_buf_poll_work_fn
> if min_data_present is set to true. If min_data_present is not set to
> true, the if statement will evaluate to true in the subsequent execution
> of eu_stall_data_buf_poll_work_fn() which is still okay. So, yes, we
> don't have to set min_data_present to true here. Will fix in the next
> version.
Just switch the order of the two OR operands and you don't have that issue?
> >
> > Also, since the write pointer itself gets reset during reset, didn't we
> > want to do this register read only when the write pointer is 0 (to avoid an
> > extra register read every 5 ms)?
>
> Good point. I have thought about reducing the number of this register
> reads. The poll function reads the write pointers of all the xecores.
> A reset can happen anytime the poll function is reading the write
> pointers of the xecores. If the reset happens before the poll function
> started reading the write pointers, all write pointers are zeros.
> If the reset happens during the poll function, several write pointers
> read so far can be non-zero while the rest of the pointers after reset
> are all zeros. The if reset happens right after the poll function, the
> write pointers can be a mix of zeros and non-zeros.
> I think the only time this register read can be skipped is if the
> LAST write pointer read is non-zero which means a reset did not happen
> before or during the poll function. Do you agree? I thought of adding a
> check to the if statement to check if the last write pointer is
> non-zero, but to keep the code clean, I didn't. Also, if there are
> n xecores, there will be n write pointer register reads plus one
> additional base register read, which isn't too bad? Also, hoping the use
> of unlikely macro would not impact the performance too much.
OK, leave this as is I think. Otherwise we'll need to read the base
register each time we see a zero write pointer. So it's ok, leave as is.
> >
> > > + }
> > > mutex_unlock(&stream->xecore_buf_lock);
> > >
> > > return min_data_present;
> > > @@ -554,6 +566,15 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
> > > }
> > > stream->data_drop.reported_to_user = false;
> > > }
> > > + /* If EU stall registers got reset due to a GT/engine reset,
> > > + * continuing with the read() will return invalid data to
> > > + * the user space. Just return -EBADFD instead.
> > > + */
> > > + if (unlikely(stream->reset_detected)) {
> > > + xe_gt_dbg(gt, "EU stall base register has been reset\n");
> > > + mutex_unlock(&stream->xecore_buf_lock);
> > > + return -EBADFD;
> >
> > The other option is to return -EIO here and implement
> > DRM_XE_OBSERVATION_IOCTL_STATUS and return status from that. Let me think
> > some more about this.
>
> I think EBADFD is more appropriate errno than EIO in this case since the
> fd is in a corrupted state and user has to close and re-open the fd.
> Currently, the -EIO is used to indicate drop data in which case, the
> user space can continue to read the data (faster) without closing the fd.
OK, we can go with -EBADFD, though still thinking about it.
> >
> > > + }
> > >
> > > for_each_dss_steering(xecore, gt, group, instance) {
> > > ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size,
> > > @@ -692,6 +713,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> > > xecore_buf->write = write_ptr;
> > > xecore_buf->read = write_ptr;
> > > }
> > > + stream->reset_detected = false;
> >
> > So after reset, if a stream is disabled and re-enabled, we expect things to
> > work again and EUSS data to be correct (without re-opening a new
> > stream)?
>
> Technically, yes, since the EU stall registers programming is done in
> enable, things will work again if the stream is disabled and re-enabled.
> But if the EUSS registers programming is moved into open() in the
> future, things may not work by disabling and re-enabling the stream. So,
> I think we suggest to the UMDs to close the stream and open a new
> stream.
No we don't suggest anything to UMD's. We decide what we want to do,
implement and enforce it that way and then maintain that uapi.
OK, then let us make sure after disable/enable, the reset_detected flag
remains set.
> >
> > > stream->data_drop.reported_to_user = false;
> > > bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
> > >
> > > @@ -717,7 +739,7 @@ static void eu_stall_data_buf_poll_work_fn(struct work_struct *work)
> > > container_of(work, typeof(*stream), buf_poll_work.work);
> > > struct xe_gt *gt = stream->gt;
> > >
> > > - if (eu_stall_data_buf_poll(stream)) {
> > > + if (stream->reset_detected || eu_stall_data_buf_poll(stream)) {
> > > stream->pollin = true;
> > > wake_up(&stream->poll_wq);
> > > }
> > > --
> > > 2.43.0
> > >
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-18 18:38 ` Cabral, Matias A
@ 2026-03-20 18:35 ` Harish Chegondi
0 siblings, 0 replies; 13+ messages in thread
From: Harish Chegondi @ 2026-03-20 18:35 UTC (permalink / raw)
To: Cabral, Matias A
Cc: Dixit, Ashutosh, intel-xe@lists.freedesktop.org, Degrood, Felix J,
Ranjan, Joshua Santhosh
Hi Matias,
On Wed, Mar 18, 2026 at 11:38:29AM -0700, Cabral, Matias A wrote:
> Second question: in this condition would require a new return error from the UMD read() API telling the consumer a catastrophic error happened and the streamer must be closed, right ?
>
Yes the consumer of the UMD read() needs to know that an error has
occurred that requires the streamer be closed. The engine/GT reset must
have happened due to an issue in the profiling application. I think if a
reset happens, the profiling application would quit with an error and
therefore the consumer of the UMD read() would discard any data
collected so far, fix the cause of the reset in the application and
rerun the application and collect the EU stall data again.
Thank You
Harish.
> Thanks,
> _Matias
>
> -----Original Message-----
> From: Cabral, Matias A
> Sent: Wednesday, March 18, 2026 9:59 AM
> To: Dixit, Ashutosh <ashutosh.dixit@intel.com>; Chegondi, Harish <harish.chegondi@intel.com>
> Cc: intel-xe@lists.freedesktop.org; Degrood, Felix J <felix.j.degrood@intel.com>; Ranjan, Joshua Santhosh <joshua.santosh.ranjan@intel.com>
> Subject: RE: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
>
> Hi Harish,
>
> > return -EBADFD;
>
> Is this making the read() syscall return -EBADFD or setting erno to EBADFD ? would like to clearly understand how to detect this condition in the UMD.
>
> Thanks,
> _Matias
>
> -----Original Message-----
> From: Dixit, Ashutosh <ashutosh.dixit@intel.com>
> Sent: Tuesday, March 17, 2026 11:58 PM
> To: Chegondi, Harish <harish.chegondi@intel.com>
> Cc: intel-xe@lists.freedesktop.org; Degrood, Felix J <felix.j.degrood@intel.com>; Cabral, Matias A <matias.a.cabral@intel.com>; Ranjan, Joshua Santhosh <joshua.santosh.ranjan@intel.com>
> Subject: Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
>
> On Mon, 16 Mar 2026 10:58:56 -0700, Harish Chegondi wrote:
> >
> > If a reset (GT or engine) happens during EU stall data sampling, all
> > the EU stall registers can get reset to 0. This will result in EU
> > stall data buffers' read and write pointer register values to be out
> > of sync with the cached values. This will result in read() returning
> > invalid data. To prevent this, check the value of a EU stall base
> > register. If it is zero, it indicates a reset may have happened that wiped the register to zero.
> > If this happens, return EBADFD from read() upon which the user space
> > should close the fd and open a new fd for a new EU stall data
> > collection session.
> >
> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> > ---
> > v2: Move base register check from read to the poll function
> >
> > drivers/gpu/drm/xe/xe_eu_stall.c | 24 +++++++++++++++++++++++-
> > 1 file changed, 23 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c
> > b/drivers/gpu/drm/xe/xe_eu_stall.c
> > index c34408cfd292..7e14de73a2c9 100644
> > --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> > +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> > @@ -44,6 +44,7 @@ struct per_xecore_buf {
> > struct xe_eu_stall_data_stream {
> > bool pollin;
> > bool enabled;
> > + bool reset_detected;
> > int wait_num_reports;
> > int sampling_rate_mult;
> > wait_queue_head_t poll_wq;
> > @@ -428,6 +429,17 @@ static bool eu_stall_data_buf_poll(struct xe_eu_stall_data_stream *stream)
> > set_bit(xecore, stream->data_drop.mask);
> > xecore_buf->write = write_ptr;
> > }
> > + /* If a GT or engine reset happens during EU stall sampling,
> > + * all EU stall registers get reset to 0 and the cached values of
> > + * the EU stall data buffers' read pointers are out of sync with
> > + * the register values. This causes invalid data to be returned
> > + * from read(). To prevent this, check the value of a EU stall base
> > + * register. If it is zero, there has been a reset.
> > + */
>
> As previously discussed, the best way would have been to not have to do this. We would just plug into the handler for the reset message from GuC, rather than to implement a reset detection here (and in other places such as OA). But looks like if we do that, because of the way EUSS registers are reset, we can return bad EUSS data. So looks like there is no way around doing this "reset detection" here and a solution with the GuC reset handler would always be racy. Just for the record.
>
> > + if (unlikely(!xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE))) {
> > + stream->reset_detected = true;
> > + min_data_present = true;
>
> I don't believe we need to set 'min_data_present = true' if we are setting 'stream->reset_detected = true', correct? See if statement at the bottom.
>
> Also, since the write pointer itself gets reset during reset, didn't we want to do this register read only when the write pointer is 0 (to avoid an extra register read every 5 ms)?
>
> > + }
> > mutex_unlock(&stream->xecore_buf_lock);
> >
> > return min_data_present;
> > @@ -554,6 +566,15 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
> > }
> > stream->data_drop.reported_to_user = false;
> > }
> > + /* If EU stall registers got reset due to a GT/engine reset,
> > + * continuing with the read() will return invalid data to
> > + * the user space. Just return -EBADFD instead.
> > + */
> > + if (unlikely(stream->reset_detected)) {
> > + xe_gt_dbg(gt, "EU stall base register has been reset\n");
> > + mutex_unlock(&stream->xecore_buf_lock);
> > + return -EBADFD;
>
> The other option is to return -EIO here and implement DRM_XE_OBSERVATION_IOCTL_STATUS and return status from that. Let me think some more about this.
>
> > + }
> >
> > for_each_dss_steering(xecore, gt, group, instance) {
> > ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size, @@
> >-692,6 +713,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> > xecore_buf->write = write_ptr;
> > xecore_buf->read = write_ptr;
> > }
> > + stream->reset_detected = false;
>
> So after reset, if a stream is disabled and re-enabled, we expect things to work again and EUSS data to be correct (without re-opening a new stream)?
>
> > stream->data_drop.reported_to_user = false;
> > bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
> >
> > @@ -717,7 +739,7 @@ static void eu_stall_data_buf_poll_work_fn(struct work_struct *work)
> > container_of(work, typeof(*stream), buf_poll_work.work);
> > struct xe_gt *gt = stream->gt;
> >
> > - if (eu_stall_data_buf_poll(stream)) {
> > + if (stream->reset_detected || eu_stall_data_buf_poll(stream)) {
> > stream->pollin = true;
> > wake_up(&stream->poll_wq);
> > }
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-19 3:55 ` Dixit, Ashutosh
@ 2026-03-20 20:59 ` Harish Chegondi
2026-03-23 20:17 ` Dixit, Ashutosh
0 siblings, 1 reply; 13+ messages in thread
From: Harish Chegondi @ 2026-03-20 20:59 UTC (permalink / raw)
To: Dixit, Ashutosh
Cc: intel-xe, felix.j.degrood, matias.a.cabral, joshua.santosh.ranjan
On Wed, Mar 18, 2026 at 08:55:42PM -0700, Dixit, Ashutosh wrote:
> On Wed, 18 Mar 2026 14:30:06 -0700, Harish Chegondi wrote:
> >
> > On Tue, Mar 17, 2026 at 11:57:32PM -0700, Dixit, Ashutosh wrote:
> > > On Mon, 16 Mar 2026 10:58:56 -0700, Harish Chegondi wrote:
> > > >
> > > > If a reset (GT or engine) happens during EU stall data sampling, all the
> > > > EU stall registers can get reset to 0. This will result in EU stall data
> > > > buffers' read and write pointer register values to be out of sync with
> > > > the cached values. This will result in read() returning invalid data. To
> > > > prevent this, check the value of a EU stall base register. If it is zero,
> > > > it indicates a reset may have happened that wiped the register to zero.
> > > > If this happens, return EBADFD from read() upon which the user space
> > > > should close the fd and open a new fd for a new EU stall data
> > > > collection session.
> > > >
> > > > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > > Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> > > > ---
> > > > v2: Move base register check from read to the poll function
> > > >
> > > > drivers/gpu/drm/xe/xe_eu_stall.c | 24 +++++++++++++++++++++++-
> > > > 1 file changed, 23 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
> > > > index c34408cfd292..7e14de73a2c9 100644
> > > > --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> > > > +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> > > > @@ -44,6 +44,7 @@ struct per_xecore_buf {
> > > > struct xe_eu_stall_data_stream {
> > > > bool pollin;
> > > > bool enabled;
> > > > + bool reset_detected;
> > > > int wait_num_reports;
> > > > int sampling_rate_mult;
> > > > wait_queue_head_t poll_wq;
> > > > @@ -428,6 +429,17 @@ static bool eu_stall_data_buf_poll(struct xe_eu_stall_data_stream *stream)
> > > > set_bit(xecore, stream->data_drop.mask);
> > > > xecore_buf->write = write_ptr;
> > > > }
> > > > + /* If a GT or engine reset happens during EU stall sampling,
> > > > + * all EU stall registers get reset to 0 and the cached values of
> > > > + * the EU stall data buffers' read pointers are out of sync with
> > > > + * the register values. This causes invalid data to be returned
> > > > + * from read(). To prevent this, check the value of a EU stall base
> > > > + * register. If it is zero, there has been a reset.
> > > > + */
> > >
> > > As previously discussed, the best way would have been to not have to do
> > > this. We would just plug into the handler for the reset message from GuC,
> > > rather than to implement a reset detection here (and in other places such
> > > as OA). But looks like if we do that, because of the way EUSS registers are
> > > reset, we can return bad EUSS data. So looks like there is no way around
> > > doing this "reset detection" here and a solution with the GuC reset handler
> > > would always be racy. Just for the record.
> >
> > Thanks for the summary of the previous discussion. Yes, hooking into the
> > GUc reset notification handler will be racy and bad EUSS data will be
> > returned to the user space if read() happens after the reset but before
> > the GuC reset notification message is processed. That's the reason for
> > not taking that approach.
> >
> > >
> > > > + if (unlikely(!xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE))) {
> > > > + stream->reset_detected = true;
> > > > + min_data_present = true;
> > >
> > > I don't believe we need to set 'min_data_present = true' if we are setting
> > > 'stream->reset_detected = true', correct? See if statement at the bottom.
> >
> > Agree. The only difference is that the if statement at the bottom will
> > evaluate true in the current execution of eu_stall_data_buf_poll_work_fn
> > if min_data_present is set to true. If min_data_present is not set to
> > true, the if statement will evaluate to true in the subsequent execution
> > of eu_stall_data_buf_poll_work_fn() which is still okay. So, yes, we
> > don't have to set min_data_present to true here. Will fix in the next
> > version.
>
> Just switch the order of the two OR operands and you don't have that issue?
But switching the order of the two OR operands would cause the function
eu_stall_data_buf_poll() to be unnecessarily called even after a reset
is detected.
>
> > >
> > > Also, since the write pointer itself gets reset during reset, didn't we
> > > want to do this register read only when the write pointer is 0 (to avoid an
> > > extra register read every 5 ms)?
> >
> > Good point. I have thought about reducing the number of this register
> > reads. The poll function reads the write pointers of all the xecores.
> > A reset can happen anytime the poll function is reading the write
> > pointers of the xecores. If the reset happens before the poll function
> > started reading the write pointers, all write pointers are zeros.
> > If the reset happens during the poll function, several write pointers
> > read so far can be non-zero while the rest of the pointers after reset
> > are all zeros. The if reset happens right after the poll function, the
> > write pointers can be a mix of zeros and non-zeros.
> > I think the only time this register read can be skipped is if the
> > LAST write pointer read is non-zero which means a reset did not happen
> > before or during the poll function. Do you agree? I thought of adding a
> > check to the if statement to check if the last write pointer is
> > non-zero, but to keep the code clean, I didn't. Also, if there are
> > n xecores, there will be n write pointer register reads plus one
> > additional base register read, which isn't too bad? Also, hoping the use
> > of unlikely macro would not impact the performance too much.
>
> OK, leave this as is I think. Otherwise we'll need to read the base
> register each time we see a zero write pointer. So it's ok, leave as is.
>
> > >
> > > > + }
> > > > mutex_unlock(&stream->xecore_buf_lock);
> > > >
> > > > return min_data_present;
> > > > @@ -554,6 +566,15 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
> > > > }
> > > > stream->data_drop.reported_to_user = false;
> > > > }
> > > > + /* If EU stall registers got reset due to a GT/engine reset,
> > > > + * continuing with the read() will return invalid data to
> > > > + * the user space. Just return -EBADFD instead.
> > > > + */
> > > > + if (unlikely(stream->reset_detected)) {
> > > > + xe_gt_dbg(gt, "EU stall base register has been reset\n");
> > > > + mutex_unlock(&stream->xecore_buf_lock);
> > > > + return -EBADFD;
> > >
> > > The other option is to return -EIO here and implement
> > > DRM_XE_OBSERVATION_IOCTL_STATUS and return status from that. Let me think
> > > some more about this.
> >
> > I think EBADFD is more appropriate errno than EIO in this case since the
> > fd is in a corrupted state and user has to close and re-open the fd.
> > Currently, the -EIO is used to indicate drop data in which case, the
> > user space can continue to read the data (faster) without closing the fd.
>
> OK, we can go with -EBADFD, though still thinking about it.
>
> > >
> > > > + }
> > > >
> > > > for_each_dss_steering(xecore, gt, group, instance) {
> > > > ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size,
> > > > @@ -692,6 +713,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> > > > xecore_buf->write = write_ptr;
> > > > xecore_buf->read = write_ptr;
> > > > }
> > > > + stream->reset_detected = false;
> > >
> > > So after reset, if a stream is disabled and re-enabled, we expect things to
> > > work again and EUSS data to be correct (without re-opening a new
> > > stream)?
> >
> > Technically, yes, since the EU stall registers programming is done in
> > enable, things will work again if the stream is disabled and re-enabled.
> > But if the EUSS registers programming is moved into open() in the
> > future, things may not work by disabling and re-enabling the stream. So,
> > I think we suggest to the UMDs to close the stream and open a new
> > stream.
>
> No we don't suggest anything to UMD's. We decide what we want to do,
> implement and enforce it that way and then maintain that uapi.
>
> OK, then let us make sure after disable/enable, the reset_detected flag
> remains set.
Okay, I will make sure the reset_detected flag remains set even after a
disable and an enable.
Thank you
Harish.
>
> > >
> > > > stream->data_drop.reported_to_user = false;
> > > > bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
> > > >
> > > > @@ -717,7 +739,7 @@ static void eu_stall_data_buf_poll_work_fn(struct work_struct *work)
> > > > container_of(work, typeof(*stream), buf_poll_work.work);
> > > > struct xe_gt *gt = stream->gt;
> > > >
> > > > - if (eu_stall_data_buf_poll(stream)) {
> > > > + if (stream->reset_detected || eu_stall_data_buf_poll(stream)) {
> > > > stream->pollin = true;
> > > > wake_up(&stream->poll_wq);
> > > > }
> > > > --
> > > > 2.43.0
> > > >
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset
2026-03-20 20:59 ` Harish Chegondi
@ 2026-03-23 20:17 ` Dixit, Ashutosh
0 siblings, 0 replies; 13+ messages in thread
From: Dixit, Ashutosh @ 2026-03-23 20:17 UTC (permalink / raw)
To: Harish Chegondi
Cc: intel-xe, felix.j.degrood, matias.a.cabral, joshua.santosh.ranjan
On Fri, 20 Mar 2026 13:59:18 -0700, Harish Chegondi wrote:
>
> On Wed, Mar 18, 2026 at 08:55:42PM -0700, Dixit, Ashutosh wrote:
> > On Wed, 18 Mar 2026 14:30:06 -0700, Harish Chegondi wrote:
> > >
> > > On Tue, Mar 17, 2026 at 11:57:32PM -0700, Dixit, Ashutosh wrote:
> > > > On Mon, 16 Mar 2026 10:58:56 -0700, Harish Chegondi wrote:
> > > > >
> > > > > If a reset (GT or engine) happens during EU stall data sampling, all the
> > > > > EU stall registers can get reset to 0. This will result in EU stall data
> > > > > buffers' read and write pointer register values to be out of sync with
> > > > > the cached values. This will result in read() returning invalid data. To
> > > > > prevent this, check the value of a EU stall base register. If it is zero,
> > > > > it indicates a reset may have happened that wiped the register to zero.
> > > > > If this happens, return EBADFD from read() upon which the user space
> > > > > should close the fd and open a new fd for a new EU stall data
> > > > > collection session.
> > > > >
> > > > > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > > > > Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> > > > > ---
> > > > > v2: Move base register check from read to the poll function
> > > > >
> > > > > drivers/gpu/drm/xe/xe_eu_stall.c | 24 +++++++++++++++++++++++-
> > > > > 1 file changed, 23 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
> > > > > index c34408cfd292..7e14de73a2c9 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_eu_stall.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_eu_stall.c
> > > > > @@ -44,6 +44,7 @@ struct per_xecore_buf {
> > > > > struct xe_eu_stall_data_stream {
> > > > > bool pollin;
> > > > > bool enabled;
> > > > > + bool reset_detected;
> > > > > int wait_num_reports;
> > > > > int sampling_rate_mult;
> > > > > wait_queue_head_t poll_wq;
> > > > > @@ -428,6 +429,17 @@ static bool eu_stall_data_buf_poll(struct xe_eu_stall_data_stream *stream)
> > > > > set_bit(xecore, stream->data_drop.mask);
> > > > > xecore_buf->write = write_ptr;
> > > > > }
> > > > > + /* If a GT or engine reset happens during EU stall sampling,
> > > > > + * all EU stall registers get reset to 0 and the cached values of
> > > > > + * the EU stall data buffers' read pointers are out of sync with
> > > > > + * the register values. This causes invalid data to be returned
> > > > > + * from read(). To prevent this, check the value of a EU stall base
> > > > > + * register. If it is zero, there has been a reset.
> > > > > + */
> > > >
> > > > As previously discussed, the best way would have been to not have to do
> > > > this. We would just plug into the handler for the reset message from GuC,
> > > > rather than to implement a reset detection here (and in other places such
> > > > as OA). But looks like if we do that, because of the way EUSS registers are
> > > > reset, we can return bad EUSS data. So looks like there is no way around
> > > > doing this "reset detection" here and a solution with the GuC reset handler
> > > > would always be racy. Just for the record.
> > >
> > > Thanks for the summary of the previous discussion. Yes, hooking into the
> > > GUc reset notification handler will be racy and bad EUSS data will be
> > > returned to the user space if read() happens after the reset but before
> > > the GuC reset notification message is processed. That's the reason for
> > > not taking that approach.
> > >
> > > >
> > > > > + if (unlikely(!xe_gt_mcr_unicast_read_any(gt, XEHPC_EUSTALL_BASE))) {
> > > > > + stream->reset_detected = true;
> > > > > + min_data_present = true;
> > > >
> > > > I don't believe we need to set 'min_data_present = true' if we are setting
> > > > 'stream->reset_detected = true', correct? See if statement at the bottom.
> > >
> > > Agree. The only difference is that the if statement at the bottom will
> > > evaluate true in the current execution of eu_stall_data_buf_poll_work_fn
> > > if min_data_present is set to true. If min_data_present is not set to
> > > true, the if statement will evaluate to true in the subsequent execution
> > > of eu_stall_data_buf_poll_work_fn() which is still okay. So, yes, we
> > > don't have to set min_data_present to true here. Will fix in the next
> > > version.
> >
> > Just switch the order of the two OR operands and you don't have that issue?
> But switching the order of the two OR operands would cause the function
> eu_stall_data_buf_poll() to be unnecessarily called even after a reset
> is detected.
Hmm, in that case why even keep rescheduling the work? I took a swipe at
doing this a little bit differently and have sent a patch v3. Can you take
a look at that and see what you think. The patch is only compile tested.
I also have a different idea now, which is, should we just call release()
and close the fd in the kernel itself, if reset is detected. Will check
with Umesh about this, I think there was something in perf_pmu which was
doing it. The kernel will automatically return -EBADFD to user land when
user land tries to use the closed fd. I am not sure if we'll eventually do
this, but at least it's good to understand if doing this is feasible.
> >
> > > >
> > > > Also, since the write pointer itself gets reset during reset, didn't we
> > > > want to do this register read only when the write pointer is 0 (to avoid an
> > > > extra register read every 5 ms)?
> > >
> > > Good point. I have thought about reducing the number of this register
> > > reads. The poll function reads the write pointers of all the xecores.
> > > A reset can happen anytime the poll function is reading the write
> > > pointers of the xecores. If the reset happens before the poll function
> > > started reading the write pointers, all write pointers are zeros.
> > > If the reset happens during the poll function, several write pointers
> > > read so far can be non-zero while the rest of the pointers after reset
> > > are all zeros. The if reset happens right after the poll function, the
> > > write pointers can be a mix of zeros and non-zeros.
> > > I think the only time this register read can be skipped is if the
> > > LAST write pointer read is non-zero which means a reset did not happen
> > > before or during the poll function. Do you agree? I thought of adding a
> > > check to the if statement to check if the last write pointer is
> > > non-zero, but to keep the code clean, I didn't. Also, if there are
> > > n xecores, there will be n write pointer register reads plus one
> > > additional base register read, which isn't too bad? Also, hoping the use
> > > of unlikely macro would not impact the performance too much.
> >
> > OK, leave this as is I think. Otherwise we'll need to read the base
> > register each time we see a zero write pointer. So it's ok, leave as is.
> >
> > > >
> > > > > + }
> > > > > mutex_unlock(&stream->xecore_buf_lock);
> > > > >
> > > > > return min_data_present;
> > > > > @@ -554,6 +566,15 @@ static ssize_t xe_eu_stall_stream_read_locked(struct xe_eu_stall_data_stream *st
> > > > > }
> > > > > stream->data_drop.reported_to_user = false;
> > > > > }
> > > > > + /* If EU stall registers got reset due to a GT/engine reset,
> > > > > + * continuing with the read() will return invalid data to
> > > > > + * the user space. Just return -EBADFD instead.
> > > > > + */
> > > > > + if (unlikely(stream->reset_detected)) {
> > > > > + xe_gt_dbg(gt, "EU stall base register has been reset\n");
> > > > > + mutex_unlock(&stream->xecore_buf_lock);
> > > > > + return -EBADFD;
> > > >
> > > > The other option is to return -EIO here and implement
> > > > DRM_XE_OBSERVATION_IOCTL_STATUS and return status from that. Let me think
> > > > some more about this.
> > >
> > > I think EBADFD is more appropriate errno than EIO in this case since the
> > > fd is in a corrupted state and user has to close and re-open the fd.
> > > Currently, the -EIO is used to indicate drop data in which case, the
> > > user space can continue to read the data (faster) without closing the fd.
> >
> > OK, we can go with -EBADFD, though still thinking about it.
> >
> > > >
> > > > > + }
> > > > >
> > > > > for_each_dss_steering(xecore, gt, group, instance) {
> > > > > ret = xe_eu_stall_data_buf_read(stream, buf, count, &total_size,
> > > > > @@ -692,6 +713,7 @@ static int xe_eu_stall_stream_enable(struct xe_eu_stall_data_stream *stream)
> > > > > xecore_buf->write = write_ptr;
> > > > > xecore_buf->read = write_ptr;
> > > > > }
> > > > > + stream->reset_detected = false;
> > > >
> > > > So after reset, if a stream is disabled and re-enabled, we expect things to
> > > > work again and EUSS data to be correct (without re-opening a new
> > > > stream)?
> > >
> > > Technically, yes, since the EU stall registers programming is done in
> > > enable, things will work again if the stream is disabled and re-enabled.
> > > But if the EUSS registers programming is moved into open() in the
> > > future, things may not work by disabling and re-enabling the stream. So,
> > > I think we suggest to the UMDs to close the stream and open a new
> > > stream.
> >
> > No we don't suggest anything to UMD's. We decide what we want to do,
> > implement and enforce it that way and then maintain that uapi.
> >
> > OK, then let us make sure after disable/enable, the reset_detected flag
> > remains set.
> Okay, I will make sure the reset_detected flag remains set even after a
> disable and an enable.
I think we just need to not to reset it to false here. I took out this line
in v3 I sent.
> > > >
> > > > > stream->data_drop.reported_to_user = false;
> > > > > bitmap_zero(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS);
> > > > >
> > > > > @@ -717,7 +739,7 @@ static void eu_stall_data_buf_poll_work_fn(struct work_struct *work)
> > > > > container_of(work, typeof(*stream), buf_poll_work.work);
> > > > > struct xe_gt *gt = stream->gt;
> > > > >
> > > > > - if (eu_stall_data_buf_poll(stream)) {
> > > > > + if (stream->reset_detected || eu_stall_data_buf_poll(stream)) {
> > > > > stream->pollin = true;
> > > > > wake_up(&stream->poll_wq);
> > > > > }
> > > > > --
> > > > > 2.43.0
> > > > >
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2026-03-23 20:17 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
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2026-03-16 17:58 [PATCH v2 1/1] drm/xe/eustall: Return EBADFD from read if EU stall registers get reset Harish Chegondi
2026-03-16 22:04 ` ✓ CI.KUnit: success for series starting with [v2,1/1] " Patchwork
2026-03-16 22:51 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-17 23:24 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-18 6:57 ` [PATCH v2 1/1] " Dixit, Ashutosh
2026-03-18 16:59 ` Cabral, Matias A
2026-03-18 18:38 ` Cabral, Matias A
2026-03-20 18:35 ` Harish Chegondi
2026-03-18 21:36 ` Harish Chegondi
2026-03-18 21:30 ` Harish Chegondi
2026-03-19 3:55 ` Dixit, Ashutosh
2026-03-20 20:59 ` Harish Chegondi
2026-03-23 20:17 ` Dixit, Ashutosh
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