From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4616BEB64DD for ; Wed, 9 Aug 2023 05:19:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA4B610E232; Wed, 9 Aug 2023 05:19:19 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A1A310E232 for ; Wed, 9 Aug 2023 05:19:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691558358; x=1723094358; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=tQl9Z7M5y9QuX20fd0nqL9tCQbFFPZ2yJ1QxQSN2Tl0=; b=YjryVgDj3+zZ5t+PFqT/vS8iCVqyfCGoHQmUnS8BkqTptkFg++0FUyss cR298KiZSNLnpf15LjotwX7b8TB1FcveyqeEQhJ+JHSrc7RxFbe5dwba3 NhbD435wECxA7AI4eVETVFZ97NS4ftZ+NHChyDx2KSjkWLn9yy/HJGtbA 5PBEKBgiRnIJYaxs7vjHxzaagILr0h0qmHiVUKjpduu7oZKIhc0rwcQgX GiRnbpeZm4y/XNB/JsEH9bZSGq+153IbX3JsdX2dhzDqWGvsanycDr2Qg OE7PfO7iBbYEGbuqVMic8QQjXeOW3Fg3KQTFOkRe8SqCbEMWdw17qi+/z w==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="350614001" X-IronPort-AV: E=Sophos;i="6.01,158,1684825200"; d="scan'208";a="350614001" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 22:19:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="708563966" X-IronPort-AV: E=Sophos;i="6.01,158,1684825200"; d="scan'208";a="708563966" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.147.231]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 22:19:16 -0700 Date: Tue, 08 Aug 2023 22:08:08 -0700 Message-ID: <878rakyf9j.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Aravind Iddamsetty In-Reply-To: <20230808115436.400611-2-aravind.iddamsetty@intel.com> References: <20230808115436.400611-1-aravind.iddamsetty@intel.com> <20230808115436.400611-2-aravind.iddamsetty@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-xe] [PATCH v3 1/2] drm/xe: Get GT clock to nanosecs X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-xe@lists.freedesktop.org Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Tue, 08 Aug 2023 04:54:35 -0700, Aravind Iddamsetty wrote: > > Helpers to get GT clock to nanosecs Helper to convert GT clock cycles to nanoseconds. > v2: Use DIV_ROUND_CLOSEST_ULL helper(Ashutosh) > > Reviewed-by: Tejas Upadhyay > Signed-off-by: Aravind Iddamsetty > --- > drivers/gpu/drm/xe/xe_gt_clock.c | 5 +++++ > drivers/gpu/drm/xe/xe_gt_clock.h | 4 +++- > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c > index 2f77b8bbcf53..88c29ad84146 100644 > --- a/drivers/gpu/drm/xe/xe_gt_clock.c > +++ b/drivers/gpu/drm/xe/xe_gt_clock.c > @@ -78,3 +78,8 @@ int xe_gt_clock_init(struct xe_gt *gt) > gt->info.clock_freq = freq; > return 0; > } > + > +u64 xe_gt_clock_interval_to_ns(const struct xe_gt *gt, u64 count) I know this name is used in i915 but my 2 cents on this is that a better name is 'xe_gt_clock_cycles_to_ns', since count is the number of clock cycles. So optional but you may consider this name. > +{ > + return DIV_ROUND_CLOSEST_ULL(count * NSEC_PER_SEC, gt->info.clock_freq); > +} > diff --git a/drivers/gpu/drm/xe/xe_gt_clock.h b/drivers/gpu/drm/xe/xe_gt_clock.h > index 511923afd224..91fc9b7e83f5 100644 > --- a/drivers/gpu/drm/xe/xe_gt_clock.h > +++ b/drivers/gpu/drm/xe/xe_gt_clock.h > @@ -6,8 +6,10 @@ > #ifndef _XE_GT_CLOCK_H_ > #define _XE_GT_CLOCK_H_ > > +#include This is for HDRTEST I guess? > + > struct xe_gt; > > int xe_gt_clock_init(struct xe_gt *gt); > - > +u64 xe_gt_clock_interval_to_ns(const struct xe_gt *gt, u64 count); > #endif > -- > 2.25.1 > Also not sure if this merits a patch on its own so can be merged into the giant PMU patch if you wish. In any case, with the optional tweaks above, this is: Reviewed-by: Ashutosh Dixit