Re: [PATCH 3/3] drm/i915/pps: Use intel_pps_is_pipe_instance() instead of open-coding it

[Jani Nikula <jani.nikula@linux.intel.com>]

On Fri, 21 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Fri, Mar 21, 2025 at 08:03:01PM +0200, Ville Syrjälä wrote:
>> On Fri, Mar 21, 2025 at 04:56:26PM +0200, Imre Deak wrote:
>> > Use intel_pps_is_pipe_instance() instead of open-coding the same for all
>> > conditional PPS programming required for a pipe instance PPS.
>> > 
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/g4x_dp.c    |  6 +++---
>> >  drivers/gpu/drm/i915/display/intel_dp.c  |  2 +-
>> >  drivers/gpu/drm/i915/display/intel_pps.c | 18 +++++++++---------
>> >  drivers/gpu/drm/i915/display/intel_pps.h |  2 ++
>> >  4 files changed, 15 insertions(+), 13 deletions(-)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
>> > index 55b9e9bfcc4d0..f527b455ce904 100644
>> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
>> > @@ -474,7 +474,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>> >  
>> >  	msleep(intel_dp->pps.panel_power_down_delay);
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview)
>> > +	if (intel_pps_is_pipe_instance(display))
>> >  		vlv_pps_port_disable(encoder, old_crtc_state);
>> 
>> Most of these are of this form
>> 
>> if (intel_pps_is_pipe_instance())
>> 	vlv_something();
>> 
>> so using an abstract name for intel_pps_is_pipe_instance()
>> feels a bit confusing. Maybe it should just be
>> intel_pps_is_vlv() or somehing?
>
> Ok. Imo it makes sense to also indicate that the PPS is not port
> specific (which would be the logical way), so how about
> intel_pps_is_vlv_pipe_instance() ?

That makes it feel like you could *not* have a pipe based PPS on
vlv/chv, and you'd have to check.

I wanted to hide all those details from the callers by moving it inside
intel_pps.c i.e. this is just a thing you do on vlv/chv.

I'd probably be more receptive to a patch that just moved all the checks
inside intel_pps.c without an additional function.

BR,
Jani.

>
>> >  }
>> >  
>> > @@ -685,7 +685,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
>> >  		return;
>> >  
>> >  	with_intel_pps_lock(intel_dp, wakeref) {
>> > -		if (display->platform.valleyview || display->platform.cherryview)
>> > +		if (intel_pps_is_pipe_instance(display))
>> >  			vlv_pps_port_enable_unlocked(encoder, pipe_config);
>> >  
>> >  		intel_dp_enable_port(intel_dp, pipe_config);
>> > @@ -1265,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
>> >  	intel_dp->reset_link_params = true;
>> >  	intel_dp_invalidate_source_oui(intel_dp);
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview)
>> > +	if (intel_pps_is_pipe_instance(display))
>> >  		vlv_pps_pipe_reset(intel_dp);
>> >  
>> >  	intel_pps_encoder_reset(intel_dp);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index e3821ccfabe30..b4a0e3775b7b4 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -6518,7 +6518,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>> >  	intel_dp_set_default_sink_rates(intel_dp);
>> >  	intel_dp_set_default_max_sink_lane_count(intel_dp);
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview)
>> > +	if (intel_pps_is_pipe_instance(display))
>> >  		vlv_pps_pipe_init(intel_dp);
>> >  
>> >  	intel_dp_aux_init(intel_dp);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
>> > index 7d7157983f25e..7b47346d4d559 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
>> > @@ -26,7 +26,7 @@ static void vlv_steal_power_sequencer(struct intel_display *display,
>> >  static void pps_init_delays(struct intel_dp *intel_dp);
>> >  static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
>> >  
>> > -static bool intel_pps_is_pipe_instance(struct intel_display *display)
>> > +bool intel_pps_is_pipe_instance(struct intel_display *display)
>> >  {
>> >  	return display->platform.valleyview || display->platform.cherryview;
>> >  }
>> > @@ -36,7 +36,7 @@ static const char *pps_name(struct intel_dp *intel_dp)
>> >  	struct intel_display *display = to_intel_display(intel_dp);
>> >  	struct intel_pps *pps = &intel_dp->pps;
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview) {
>> > +	if (intel_pps_is_pipe_instance(display)) {
>> >  		switch (pps->vlv_pps_pipe) {
>> >  		case INVALID_PIPE:
>> >  			/*
>> > @@ -411,7 +411,7 @@ pps_initial_setup(struct intel_dp *intel_dp)
>> >  
>> >  	lockdep_assert_held(&display->pps.mutex);
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview) {
>> > +	if (intel_pps_is_pipe_instance(display)) {
>> >  		vlv_initial_power_sequencer_setup(intel_dp);
>> >  		return true;
>> >  	}
>> > @@ -510,7 +510,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
>> >  
>> >  	memset(regs, 0, sizeof(*regs));
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview)
>> > +	if (intel_pps_is_pipe_instance(display))
>> >  		pps_idx = vlv_power_sequencer_pipe(intel_dp);
>> >  	else if (display->platform.geminilake || display->platform.broxton)
>> >  		pps_idx = bxt_power_sequencer_idx(intel_dp);
>> > @@ -556,7 +556,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>> >  
>> >  	lockdep_assert_held(&display->pps.mutex);
>> >  
>> > -	if ((display->platform.valleyview || display->platform.cherryview) &&
>> > +	if (intel_pps_is_pipe_instance(display) &&
>> >  	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
>> >  		return false;
>> >  
>> > @@ -569,7 +569,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>> >  
>> >  	lockdep_assert_held(&display->pps.mutex);
>> >  
>> > -	if ((display->platform.valleyview || display->platform.cherryview) &&
>> > +	if (intel_pps_is_pipe_instance(display) &&
>> >  	    intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
>> >  		return false;
>> >  
>> > @@ -1758,7 +1758,7 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp)
>> >  		 * Reinit the power sequencer also on the resume path, in case
>> >  		 * BIOS did something nasty with it.
>> >  		 */
>> > -		if (display->platform.valleyview || display->platform.cherryview)
>> > +		if (intel_pps_is_pipe_instance(display))
>> >  			vlv_initial_power_sequencer_setup(intel_dp);
>> >  
>> >  		pps_init_delays(intel_dp);
>> > @@ -1797,7 +1797,7 @@ static void pps_init_late(struct intel_dp *intel_dp)
>> >  	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>> >  	struct intel_connector *connector = intel_dp->attached_connector;
>> >  
>> > -	if (display->platform.valleyview || display->platform.cherryview)
>> > +	if (intel_pps_is_pipe_instance(display))
>> >  		return;
>> >  
>> >  	if (intel_num_pps(display) < 2)
>> > @@ -1931,7 +1931,7 @@ void assert_pps_unlocked(struct intel_display *display, enum pipe pipe)
>> >  			MISSING_CASE(port_sel);
>> >  			break;
>> >  		}
>> > -	} else if (display->platform.valleyview || display->platform.cherryview) {
>> > +	} else if (intel_pps_is_pipe_instance(display)) {
>> >  		/* presumably write lock depends on pipe, not port select */
>> >  		pp_reg = PP_CONTROL(display, pipe);
>> >  		panel_pipe = pipe;
>> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
>> > index 4390d05892325..1f4eed5fc55b8 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_pps.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_pps.h
>> > @@ -17,6 +17,8 @@ struct intel_display;
>> >  struct intel_dp;
>> >  struct intel_encoder;
>> >  
>> > +bool intel_pps_is_pipe_instance(struct intel_display *display);
>> > +
>> >  intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp);
>> >  intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref);
>> >  
>> > -- 
>> > 2.44.2
>> 
>> -- 
>> Ville Syrjälä
>> Intel

-- 
Jani Nikula, Intel