From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 4/5] drm/i915/pll_algorithm: Compute C10 HDMI PLLs with algorithm
Date: Tue, 06 Aug 2024 16:59:06 +0300 [thread overview]
Message-ID: <87bk2569cl.fsf@intel.com> (raw)
In-Reply-To: <20240806125827.2183899-5-ankit.k.nautiyal@intel.com>
On Tue, 06 Aug 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h
> index 9f60bd9bacbe..288289ec593f 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h
> +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h
> @@ -8,8 +8,10 @@
>
> #include <linux/types.h>
>
> +struct intel_c10pll_state;
> struct intel_mpllb_state;
>
> void intel_snps_phy_compute_hdmi_tmds_pll(struct intel_mpllb_state *pll_state, u64 pixel_clock);
> +void intel_c10_phy_compute_hdmi_tmds_pll(struct intel_c10pll_state *pll_state, u64 pixel_clock);
If you have a file intel_snps_hdmi_pll.[ch], the functions should be
named intel_snps_hdmi_pll_*().
Or you need to rename the file.
BR,
Jani.
>
> #endif /* __INTEL_SNPS_HDMI_PLL_H__ */
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-08-06 13:59 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-06 12:58 [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY Ankit Nautiyal
2024-08-06 12:58 ` [PATCH 1/5] drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2 Ankit Nautiyal
2024-08-06 12:58 ` [PATCH 2/5] drm/i915/snps_phy: Use " Ankit Nautiyal
2024-08-06 12:58 ` [PATCH 3/5] drm/i915/cx0_phy_regs: Add C10 registers bits Ankit Nautiyal
2024-08-06 12:58 ` [PATCH 4/5] drm/i915/pll_algorithm: Compute C10 HDMI PLLs with algorithm Ankit Nautiyal
2024-08-06 13:59 ` Jani Nikula [this message]
2024-08-07 3:05 ` Nautiyal, Ankit K
2024-08-06 12:58 ` [PATCH 5/5] drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY Ankit Nautiyal
2024-08-06 13:02 ` ✓ CI.Patch_applied: success for Add HDMI PLL Algorithm for SNPS/C10PHY (rev2) Patchwork
2024-08-06 13:03 ` ✗ CI.checkpatch: warning " Patchwork
2024-08-06 13:04 ` ✓ CI.KUnit: success " Patchwork
2024-08-06 13:16 ` ✓ CI.Build: " Patchwork
2024-08-06 13:18 ` ✓ CI.Hooks: " Patchwork
2024-08-06 13:21 ` ✗ CI.checksparse: warning " Patchwork
2024-08-06 14:21 ` ✓ CI.BAT: success " Patchwork
2024-08-06 15:06 ` ✗ CI.FULL: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2024-06-26 5:00 [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY Ankit Nautiyal
2024-06-26 5:00 ` [PATCH 4/5] drm/i915/pll_algorithm: Compute C10 HDMI PLLs with algorithm Ankit Nautiyal
2024-06-26 10:10 ` Jani Nikula
2024-06-27 17:08 ` Nautiyal, Ankit K
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