From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5F93CFC50B for ; Fri, 21 Nov 2025 22:25:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 50D2310E90E; Fri, 21 Nov 2025 22:25:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ih5qRmDa"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 38D1510E90E for ; Fri, 21 Nov 2025 22:25:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763763914; x=1795299914; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=XfUZFQM2r6OY1FGbZdXFslsrNkVmpFufVeBO+XCxdB4=; b=ih5qRmDatUeDOBoXhiLzWgl0+p3003iFaFZBhDS0N+dCUNmjmBBTX3mQ pjCe7a/OFJe2zmPMcgMKNYWbqT1pPcZa40eRUNA6oVRg5sjiP7MxtruEW ljbGEgOaBWU9lirgiLI1rECIsZbSWx0zlmvnCVYWn72qBKEsSk+zumulk PdwRvh884FDqpBGyXP4ecHDirByYuOMdg5MDNrRbV16tHvBfi2J2cPlcr lmE5Q7PcFx9LmEbIinJBnym38oeqsP9YN1UgglA5UrSIedCthJyzu/38B Prz0heuK9O9iStfadlzO+Xh4Bo8DkGuloeJrE047sVpjmAN5GYNhnd1lw g==; X-CSE-ConnectionGUID: BwFuVK/mTtep7N5GKEFK6A== X-CSE-MsgGUID: BSo3QL6GThCUMWuPsAqD5A== X-IronPort-AV: E=McAfee;i="6800,10657,11620"; a="65814771" X-IronPort-AV: E=Sophos;i="6.20,216,1758610800"; d="scan'208";a="65814771" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2025 14:25:13 -0800 X-CSE-ConnectionGUID: k/gytCWiRp63WelhbG3fQQ== X-CSE-MsgGUID: 4v9O7YkoRXyl0LtsbQmmAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,216,1758610800"; d="scan'208";a="196943843" Received: from juarezfx-mobl.amr.corp.intel.com (HELO adixit-MOBL3.intel.com) ([10.246.168.235]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2025 14:25:12 -0800 Date: Fri, 21 Nov 2025 14:25:10 -0800 Message-ID: <87cy5buipl.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Harish Chegondi Cc: , Umesh Nerlige Ramappa Subject: Re: [PATCH 1/1] drm/xe: Fix conversion from clock ticks to milliseconds In-Reply-To: <1562f1b62d5be3fbaee100f09107f3cc49e40dd1.1763408584.git.harish.chegondi@intel.com> References: <1562f1b62d5be3fbaee100f09107f3cc49e40dd1.1763408584.git.harish.chegondi@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Mon, 17 Nov 2025 11:48:43 -0800, Harish Chegondi wrote: > > When tick counts are large and multiplication by MSEC_PER_SEC is larger > than 64 bits, the conversion from clock ticks to milliseconds can go bad. > > Use mul_u64_u32_div() instead. > > Cc: Ashutosh Dixit > Signed-off-by: Harish Chegondi > Suggested-by: Umesh Nerlige Ramappa With: Fixes: 49cc215aad7f ("drm/xe: Add xe_gt_clock_interval_to_ms helper" Reviewed-by: Ashutosh Dixit > --- > drivers/gpu/drm/xe/xe_gt_clock.c | 7 +------ > 1 file changed, 1 insertion(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c > index 00f5972c14dc..bfc25c46f798 100644 > --- a/drivers/gpu/drm/xe/xe_gt_clock.c > +++ b/drivers/gpu/drm/xe/xe_gt_clock.c > @@ -74,11 +74,6 @@ int xe_gt_clock_init(struct xe_gt *gt) > return 0; > } > > -static u64 div_u64_roundup(u64 n, u32 d) > -{ > - return div_u64(n + d - 1, d); > -} > - > /** > * xe_gt_clock_interval_to_ms - Convert sampled GT clock ticks to msec > * > @@ -89,5 +84,5 @@ static u64 div_u64_roundup(u64 n, u32 d) > */ > u64 xe_gt_clock_interval_to_ms(struct xe_gt *gt, u64 count) > { > - return div_u64_roundup(count * MSEC_PER_SEC, gt->info.reference_clock); > + return mul_u64_u32_div(count, MSEC_PER_SEC, gt->info.reference_clock); > } > -- > 2.43.0 >