From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A45FCC43458 for ; Mon, 29 Jun 2026 16:33:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6096810E98F; Mon, 29 Jun 2026 16:33:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="KTdO4Y5t"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4D92A10E9A0 for ; Mon, 29 Jun 2026 16:33:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782750836; x=1814286836; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=juoANnnu5Fy+j88aBAZtpjliHBSJTsmg2vhjvlv7uQo=; b=KTdO4Y5tjtRN1bwOwiDKXDbWS9zqxw6Ysc0RVz01P5jXNZbz2L+wpOFF EhGmAE7xj+Ka9RgX6lyOGF7FivIujHl8SiuiKOrahc0jruEVOUGR/dL4o DNWpvPN2TUWXglgruTD6yI8HO0/MI9A8RAhC6rQJyRXGjeFikYKFHiRTZ DgHmnMwDKlpisbPHugQGPOy81NbOCAnHg+2CHzyo3VEoYQGMBYO4h13C4 Rqv7WXbpZr8cibhTQHbnXaqINNeZbTmU62CFd8wp1jIfFSxP5+bppEPC5 ai8DKmC7FDeZrHr5tbbKH7FU9VhQBdVJmVj/D+TPn/HXH1Wyq2aIUVBJ5 w==; X-CSE-ConnectionGUID: 3x0zYLsOSuqEuYb+y8RwJQ== X-CSE-MsgGUID: rcrZLbcCR8KCw/1KuFx6qw== X-IronPort-AV: E=McAfee;i="6800,10657,11832"; a="100879596" X-IronPort-AV: E=Sophos;i="6.24,232,1774335600"; d="scan'208";a="100879596" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2026 09:33:56 -0700 X-CSE-ConnectionGUID: lugdGN8nSZGU9vMqloG0Ag== X-CSE-MsgGUID: af0kdlDZROSGQGhkbmKRHQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,232,1774335600"; d="scan'208";a="255951885" Received: from rchalla-mobl1.amr.corp.intel.com (HELO adixit-MOBL3.intel.com) ([10.125.128.110]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2026 09:33:56 -0700 Date: Mon, 29 Jun 2026 09:33:55 -0700 Message-ID: <87echpjogc.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa Cc: Subject: Re: [PATCH v2 1/4] drm/xe/oa: Rename last argument of WHITELIST_OA_MMIO_TRG In-Reply-To: References: <20260617015422.226177-1-ashutosh.dixit@intel.com> <20260617015422.226177-2-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Thu, 25 Jun 2026 16:06:23 -0700, Umesh Nerlige Ramappa wrote: > > On Tue, Jun 16, 2026 at 06:54:19PM -0700, Ashutosh Dixit wrote: > > OA head pointer registers are not used by UMD's and do not need to be > > whitelisted, the last argument of WHITELIST_OA_MMIO_TRG is actually used > > for whitelisting tail pointer and OA buffer registers. Rename the argument > > to tail_buf to reflect this. OA head pointer is sometimes provided to the > > WHITELIST_OA_MMIO_TRG to have the correct register offset alignment (16) > > for RING_FORCE_TO_NONPRIV_RANGE_4. > > > > Fixes: ed455775c5a6 ("drm/xe/rtp: Refactor OAG MMIO trigger register whitelisting") > > Signed-off-by: Ashutosh Dixit > > I don't see a real bug that this patch is fixing in ed455775c5a6. It just > renames the last field of the macro. I agree we should drop the 'Fixes:' tag from this patch. The purpose of this patch is only to *document* that what we really want to whitelist is the tailptr and oa_buffer registers, not the head pointer itself. In case registers move around in future products and code needs to be changed e.g. > > I think you can safely drop this patch. The whitelisting alignment breaks > only for MERTOA. Patch 2 in this series is fixing that and it has the right > Fixes tag. > > If you plan to remove HEADPTR from OAM and OAG as well in future, you could > use this patch. Yeah, HEADPTR is not intended to be whitelisted for any of the OA units (it is just provided sometimes for alignment, as mentioned in the commit message). That is why I was thinking we should retain this patch for the sake of documenting, as mentioned above. Thanks. -- Ashutosh > > > --- > > drivers/gpu/drm/xe/xe_reg_whitelist.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c > > index 2e84b1c49f374..a17ebacc1455b 100644 > > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c > > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c > > @@ -104,10 +104,10 @@ static const struct xe_rtp_table_sr register_whitelist = XE_RTP_TABLE_SR( > > RING_FORCE_TO_NONPRIV_ACCESS_RW)) > > }, > > > > -#define WHITELIST_OA_MMIO_TRG(trg, status, head) \ > > +#define WHITELIST_OA_MMIO_TRG(trg, status, tail_buf) \ > > WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \ > > WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \ > > - WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4) > > + WHITELIST(tail_buf, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4) > > > > #define WHITELIST_OAG_MMIO_TRG \ > > WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR) > > -- > > 2.54.0 > >