From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DC91CCD193 for ; Wed, 15 Oct 2025 23:58:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CAE7A10E108; Wed, 15 Oct 2025 23:58:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nMZELzv5"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0A90310E108 for ; Wed, 15 Oct 2025 23:58:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1760572734; x=1792108734; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=W3vZ0wiXtmMg4b3PfZ3i9sVkyMOVQ9aILjBDalsq1Bo=; b=nMZELzv5tg+sjfupC6DhoxAK+DnBAC+8C3XAD3bz6fVmgp2v17a9LltX q7YVjuI9J0ZMWZ0MYNiauemBKRIIZOzjLujoZFyxsPjYvmthjESZORhrI GFcNnD9S98yF4ZeX84u2JmXXqJvZtcMZUGeFhKD1Qt8TTM+ZmQBVIqGoU wjZrdzBg08a2nb+fkUU60ijyBmaWaYz1T+UlovtoWHH3lInTnvlVezTy+ xu22QPpgNBJCVS4RXaTAbIMKgAoG3fiVTNzPADGk4CFgGcnhe1jaWRy6+ Qq7CHwrTjz8Bo6NkaivNkI2rugPsr6cVtQg7YuDO+LLnr49/K9d+3gjFA A==; X-CSE-ConnectionGUID: 2fiSXk6vT56y92mL/no4jA== X-CSE-MsgGUID: KHkikU80Quqe4hJd/2Uotg== X-IronPort-AV: E=McAfee;i="6800,10657,11583"; a="50324986" X-IronPort-AV: E=Sophos;i="6.19,232,1754982000"; d="scan'208";a="50324986" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2025 16:58:53 -0700 X-CSE-ConnectionGUID: xAccTEVQR327pvlNz1I1bw== X-CSE-MsgGUID: mAJBsyNuRXCDwnvyMbzr6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,232,1754982000"; d="scan'208";a="212911731" Received: from iprasad-mobl.amr.corp.intel.com (HELO adixit-MOBL3.intel.com) ([10.125.52.66]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2025 16:58:53 -0700 Date: Wed, 15 Oct 2025 16:58:52 -0700 Message-ID: <87ecr3iuo3.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Lucas De Marchi Cc: , Shekhar Chauhan , Balasubramani Vivekanandan , Matt Roper , Tejas Upadhyay , Harish Chegondi Subject: Re: [PATCH v2 22/22] drm/xe/xe3p: Add xe3p EU stall data format In-Reply-To: <20251015-xe3p-v2-22-b9189b3056a2@intel.com> References: <20251015-xe3p-v2-0-b9189b3056a2@intel.com> <20251015-xe3p-v2-22-b9189b3056a2@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 15 Oct 2025 15:06:37 -0700, Lucas De Marchi wrote: > > From: Harish Chegondi > > Starting with Xe3p, IP address in EU stall data increases to 61 bits. > While at it, re-order the if-else ladder so the officially supported > platforms come before PVC. > > Cc: Ashutosh Dixit > Signed-off-by: Harish Chegondi > Signed-off-by: Lucas De Marchi > --- > v2: reorder the if-else ladder so PVC is the last (Lucas) Don't we want to commit the version log as part of the patch? In any case, this is: Reviewed-by: Ashutosh Dixit > > TODO: double check data format as it's missing from bspec > --- > drivers/gpu/drm/xe/xe_eu_stall.c | 28 ++++++++++++++++++++++++++-- > 1 file changed, 26 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c > index f5cfdf29fde34..650e45f6a7c7e 100644 > --- a/drivers/gpu/drm/xe/xe_eu_stall.c > +++ b/drivers/gpu/drm/xe/xe_eu_stall.c > @@ -124,6 +124,27 @@ struct xe_eu_stall_data_xe2 { > __u64 unused[6]; > } __packed; > > +/* > + * EU stall data format for Xe3p arch GPUs. > + */ > +struct xe_eu_stall_data_xe3p { > + __u64 ip_addr:61; /* Bits 0 to 60 */ > + __u64 tdr_count:8; /* Bits 61 to 68 */ > + __u64 other_count:8; /* Bits 69 to 76 */ > + __u64 control_count:8; /* Bits 77 to 84 */ > + __u64 pipestall_count:8; /* Bits 85 to 92 */ > + __u64 send_count:8; /* Bits 93 to 100 */ > + __u64 dist_acc_count:8; /* Bits 101 to 108 */ > + __u64 sbid_count:8; /* Bits 109 to 116 */ > + __u64 sync_count:8; /* Bits 117 to 124 */ > + __u64 inst_fetch_count:8; /* Bits 125 to 132 */ > + __u64 active_count:8; /* Bits 133 to 140 */ > + __u64 ex_id:3; /* Bits 141 to 143 */ > + __u64 end_flag:1; /* Bit 144 */ > + __u64 unused_bits:47; > + __u64 unused[5]; > +} __packed; > + > const u64 eu_stall_sampling_rates[] = {251, 251 * 2, 251 * 3, 251 * 4, 251 * 5, 251 * 6, 251 * 7}; > > /** > @@ -167,10 +188,13 @@ size_t xe_eu_stall_data_record_size(struct xe_device *xe) > { > size_t record_size = 0; > > - if (xe->info.platform == XE_PVC) > - record_size = sizeof(struct xe_eu_stall_data_pvc); > + if (GRAPHICS_VER(xe) >= 35) > + record_size = sizeof(struct xe_eu_stall_data_xe3p); > else if (GRAPHICS_VER(xe) >= 20) > record_size = sizeof(struct xe_eu_stall_data_xe2); > + else if (xe->info.platform == XE_PVC) > + record_size = sizeof(struct xe_eu_stall_data_pvc); > + > > xe_assert(xe, is_power_of_2(record_size)); > > > -- > 2.51.0 >