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d="scan'208";a="108538323" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.246.130]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 01:46:26 -0800 From: Jani Nikula To: Ville =?utf-8?B?U3lyasOkbMOk?= Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: Re: [PATCH 1/5] drm/i915: Move VT-d alignment into plane->min_alignment() In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20250122151755.6928-1-ville.syrjala@linux.intel.com> <20250122151755.6928-2-ville.syrjala@linux.intel.com> <878qqwbn6d.fsf@intel.com> Date: Tue, 28 Jan 2025 11:46:23 +0200 Message-ID: <87h65j9spc.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Mon, 27 Jan 2025, Ville Syrj=C3=A4l=C3=A4 wrote: > On Mon, Jan 27, 2025 at 06:44:21PM +0200, Ville Syrj=C3=A4l=C3=A4 wrote: >> On Mon, Jan 27, 2025 at 11:50:34AM +0200, Jani Nikula wrote: >> > On Wed, 22 Jan 2025, Ville Syrjala wro= te: >> > > From: Ville Syrj=C3=A4l=C3=A4 >> > > >> > > Currently we don't account for the VT-d alignment w/a in >> > > plane->min_alignment() which means that panning inside a larger >> > > framebuffer can still cause the plane SURF to be misaligned. >> > > Fix the issue by moving the VT-d alignment w/a into >> > > plane->min_alignment() itself (for the affected platforms). >> > > >> > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 >> > > --- >> > > drivers/gpu/drm/i915/display/i9xx_plane.c | 10 ++++++++++ >> > > drivers/gpu/drm/i915/display/intel_cursor.c | 5 +++++ >> > > drivers/gpu/drm/i915/display/intel_fb_pin.c | 8 -------- >> > > drivers/gpu/drm/i915/display/intel_sprite.c | 5 +++++ >> > > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++++ >> > > 5 files changed, 24 insertions(+), 8 deletions(-) >> > > >> > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu= /drm/i915/display/i9xx_plane.c >> > > index ed171fbf8720..19cc34babef3 100644 >> > > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c >> > > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c >> > > @@ -780,9 +780,14 @@ unsigned int vlv_plane_min_alignment(struct int= el_plane *plane, >> > > const struct drm_framebuffer *fb, >> > > int color_plane) >> > > { >> > > + struct drm_i915_private *i915 =3D to_i915(plane->base.dev); >> > > + >> > > if (intel_plane_can_async_flip(plane, fb->modifier)) >> > > return 256 * 1024; >> > >=20=20 >> > > + if (intel_scanout_needs_vtd_wa(i915)) >> > > + return 256 * 1024; >> >=20 >> > Nitpick, would be great to convert intel_scanout_needs_vtd_wa() to >> > struct intel_display first, so we wouldn't have to introduce so many n= ew >> > struct drm_i915_private uses. >>=20 >> I didn't really want to add intel_display stuff to the >> gem side (where this is being used currently). Once >> its all moved into the display code (patch 3) then it >> makes more sense. Roger. > BTW I do have full conversion of all the low level > plane code (+ a bunch of other stuff including > intel_display_power_{put,get}() stuff) done locally. > But I have quite a few series on the list already > needing review, so not sure I should also post that > one right now. I can, if you especially want something > mundane to read? I might be up for just that, actually. BR, Jani. --=20 Jani Nikula, Intel