From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B8C7C3DA4A for ; Tue, 20 Aug 2024 01:34:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 44E8E10E493; Tue, 20 Aug 2024 01:34:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XML+Z64i"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id B08D610E493 for ; Tue, 20 Aug 2024 01:34:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724117654; x=1755653654; h=date:message-id:from:to:cc:subject:references: mime-version; bh=0SOM96DbeB/XCkA6EnQ2MM8X/UzUlWdhjyp4/Y60uZI=; b=XML+Z64i9cJ0WsLazxnj6CphOqQ6Hk8NdbsOmVVmsTBBpiBcF8KZWuXE 30Q1X22MeHggbW2O93bCfxg4Ua+/oxiSldjInWOamtjgLGwHfW+8/cvmy qbq7CijCLV5dcIC6WNBNmbY5lr6WpgEA6TWCmT67x9kLvVLDJz+brXST1 zfJhpGLIoXnqpqn+ZpjU0tpmaz2Oe4wSKoxj3A0yqzHdPCbuZemtFlKLx srhYLFtjYuKp87M3VEx8qRnYw8iT9ocCffXRkfgPvvwfwq2akZZm8SQtV sKrtJoyDYmdj1rrHb+PjjHqnd//eymxO1eRLcGNj8wuQ84bBhryN+2ATN w==; X-CSE-ConnectionGUID: h+RnatADQYmM4w5oi3wwPg== X-CSE-MsgGUID: tIkmr/gnSKqRjxSffot49Q== X-IronPort-AV: E=McAfee;i="6700,10204,11169"; a="22555177" X-IronPort-AV: E=Sophos;i="6.10,160,1719903600"; d="scan'208";a="22555177" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2024 18:34:13 -0700 X-CSE-ConnectionGUID: Pw5WzLJqS86+uA4Gj6KtKg== X-CSE-MsgGUID: PigiUg9UTGCpk4xIaLHbiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,160,1719903600"; d="scan'208";a="60539569" Received: from peterval-mobl1.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.124.114.37]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2024 18:34:14 -0700 Date: Mon, 19 Aug 2024 18:30:03 -0700 Message-ID: <87h6bgdlr8.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: "Cavitt, Jonathan" Cc: "intel-xe@lists.freedesktop.org" , "Nerlige Ramappa, Umesh" , "Souza, Jose" , "Landwerlin, Lionel G" Subject: Re: [PATCH 5/8] drm/xe/oa: Signal output fences References: <20240808174139.4027534-1-ashutosh.dixit@intel.com> <20240808174139.4027534-6-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Some time ago, Dixit, Ashutosh wrote: > > On Thu, 08 Aug 2024 14:16:24 -0700, Cavitt, Jonathan wrote: > > > > -----Original Message----- > > From: Intel-xe On Behalf Of Ashutosh Dixit > > Sent: Thursday, August 8, 2024 10:42 AM > > To: intel-xe@lists.freedesktop.org > > Cc: Nerlige Ramappa, Umesh ; Souza, Jose ; Landwerlin, Lionel G > > Subject: [PATCH 5/8] drm/xe/oa: Signal output fences > > > > > > Complete 'struct xe_oa_fence' to include the dma_fence used to signal > > > output fences in the xe_sync array. The fences are signalled > > > asynchronously. When there are no output fences to signal, the OA > > > configuration wait is synchronously re-introduced into the ioctl. > > > > s/signalled/signaled Done. > > > > Also, it might be best to elaborate on why the dma_fence base > > and spinlock_t lock weren't added as a part of patch 2, when > > the xe_oa_fence was initially declared. Mostly to make the review easier. But in v2 series these two patches are indeed squashed into a single patch, since there are significant changes to this patch suggested by Matt and it didn't make sense to split them. > > > > Otherwise: > > Reviewed-by: Jonathan Cavitt Thanks. -- Ashutosh > > -Jonathan Cavitt > > > > > > > > Signed-off-by: Ashutosh Dixit > > > --- > > > drivers/gpu/drm/xe/xe_oa.c | 46 +++++++++++++++++++++++++++++++++++--- > > > 1 file changed, 43 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c > > > index 416e031ac454b..bc421cd0af6ba 100644 > > > --- a/drivers/gpu/drm/xe/xe_oa.c > > > +++ b/drivers/gpu/drm/xe/xe_oa.c > > > @@ -96,6 +96,10 @@ struct xe_oa_config_bo { > > > }; > > > > > > struct xe_oa_fence { > > > + /* @base: dma fence base */ > > > + struct dma_fence base; > > > + /* @lock: lock for the fence */ > > > + spinlock_t lock; > > > /* @xe: pointer to xe device */ > > > struct xe_device *xe; > > > /* @work: work to signal that OA configuration is applied */ > > > @@ -953,9 +957,26 @@ static void xe_oa_fence_work_fn(struct work_struct *w) > > > /* Additional empirical delay needed for NOA programming after registers are written */ > > > usleep_range(us, 2 * us); > > > > > > - kfree(ofence); > > > + /* Now signal fence to indicate new OA configuration is active */ > > > + dma_fence_signal(&ofence->base); > > > + dma_fence_put(&ofence->base); > > > } > > > > > > +static const char *xe_oa_get_driver_name(struct dma_fence *fence) > > > +{ > > > + return "xe_oa"; > > > +} > > > + > > > +static const char *xe_oa_get_timeline_name(struct dma_fence *fence) > > > +{ > > > + return "unbound"; > > > +} > > > + > > > +static const struct dma_fence_ops xe_oa_fence_ops = { > > > + .get_driver_name = xe_oa_get_driver_name, > > > + .get_timeline_name = xe_oa_get_timeline_name, > > > +}; > > > + > > > static struct xe_oa_fence *xe_oa_fence_init(struct xe_device *xe, struct dma_fence *config_fence) > > > { > > > struct xe_oa_fence *ofence; > > > @@ -967,6 +988,8 @@ static struct xe_oa_fence *xe_oa_fence_init(struct xe_device *xe, struct dma_fen > > > ofence->xe = xe; > > > INIT_WORK(&ofence->work, xe_oa_fence_work_fn); > > > ofence->config_fence = config_fence; > > > + spin_lock_init(&ofence->lock); > > > + dma_fence_init(&ofence->base, &xe_oa_fence_ops, &ofence->lock, 0, 0); > > > > > > return ofence; > > > } > > > @@ -975,8 +998,8 @@ static int xe_oa_emit_oa_config(struct xe_oa_stream *stream, struct xe_oa_config > > > { > > > struct xe_oa_config_bo *oa_bo; > > > struct xe_oa_fence *ofence; > > > + int i, err, num_signal = 0; > > > struct dma_fence *fence; > > > - int err; > > > > > > /* Emit OA configuration batch */ > > > oa_bo = xe_oa_alloc_config_buffer(stream, config); > > > @@ -989,13 +1012,30 @@ static int xe_oa_emit_oa_config(struct xe_oa_stream *stream, struct xe_oa_config > > > if (err) > > > goto exit; > > > > > > + /* Initialize and set fence to signal */ > > > ofence = xe_oa_fence_init(stream->oa->xe, fence); > > > if (IS_ERR(ofence)) { > > > err = PTR_ERR(ofence); > > > goto put_fence; > > > } > > > > > > - xe_oa_fence_work_fn(&ofence->work); > > > + for (i = 0; i < stream->num_syncs; i++) > > > + xe_sync_entry_signal(&stream->syncs[i], &ofence->base); > > > + > > > + /* Schedule work to signal the fence */ > > > + queue_work(system_unbound_wq, &ofence->work); > > > + > > > + /* If nothing needs to be signaled we wait synchronously */ > > > + for (i = 0; i < stream->num_syncs; i++) > > > + if (stream->syncs[i].flags & DRM_XE_SYNC_FLAG_SIGNAL) > > > + num_signal++; > > > + if (!num_signal) > > > + flush_work(&ofence->work); > > > + > > > + /* Done with syncs */ > > > + for (i = 0; i < stream->num_syncs; i++) > > > + xe_sync_entry_cleanup(&stream->syncs[i]); > > > + kfree(stream->syncs); > > > > > > return 0; > > > put_fence: > > > -- > > > 2.41.0 > > > > > >