From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F6CAE9A03B for ; Thu, 19 Feb 2026 02:23:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 58AC210E243; Thu, 19 Feb 2026 02:23:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="f3adFpBn"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 60C9C10E243 for ; Thu, 19 Feb 2026 02:23:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1771467824; x=1803003824; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=k6mvP3EGaTRutZvZP0nuShZ6CVSFWQamGXG+V+pgnQk=; b=f3adFpBnCfEG2x7Au+sQCpi6mGRK4NJzmWoMgnpdHGdsInrBPMKC8KX4 X+tjEj0WDgypse2z2eeGjrLXkX/l3DzRPsOd7Y/c7fGBFoGrJacjpWwmc oqp2yfqDtfqs9yfwCJZZ31rzw2wmHebMFYwP4OjnBxUThgDveDborjFgz jw2f8DaaVeQfdO6QXHPC1iMMYZE4/mt4WgK26wNDfWivPcRzKITi6ADrK XG9RGvZlxMtSOUH0s3eVcwMz86STAkXkT2acIGWAW0dylnjQsr7V2N+6b SwarmzUgFsRrMqBeUorFxjHtzjkMsLByEjehodwkqxfRZhkBVm7q8qKdy w==; X-CSE-ConnectionGUID: c6WsDqBQS2iIa7gVJs2YlA== X-CSE-MsgGUID: g1SBuSFBS96Kus/+lAoHQw== X-IronPort-AV: E=McAfee;i="6800,10657,11705"; a="72440404" X-IronPort-AV: E=Sophos;i="6.21,299,1763452800"; d="scan'208";a="72440404" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2026 18:23:44 -0800 X-CSE-ConnectionGUID: zSZk3IWFQFG71LyGfj2yCw== X-CSE-MsgGUID: l7hRQXbGTVaYNCGdA4EbpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,299,1763452800"; d="scan'208";a="218520523" Received: from unknown (HELO adixit-MOBL3.intel.com) ([10.125.136.209]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2026 18:23:44 -0800 Date: Wed, 18 Feb 2026 18:23:43 -0800 Message-ID: <87ikbtwjww.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Matt Roper Cc: , Michal Wajdeczko Subject: Re: [PATCH v4 4/4] drm/xe/reg_sr: Allow register_save_restore_check debugfs to verify LRC values In-Reply-To: <20260218-sr_verify-v4-4-35d6deeb3421@intel.com> References: <20260218-sr_verify-v4-0-35d6deeb3421@intel.com> <20260218-sr_verify-v4-4-35d6deeb3421@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 18 Feb 2026 14:09:15 -0800, Matt Roper wrote: > > reg_sr programming that applies to an engines LRC cannot be verified by > a simple CPU-based register readout because the reg_sr's values may not > be in effect if no context is executing on the hardware at the time we > check. Instead, we should verify correct reg_sr application by > searching for the register in the default_lrc. > This too LGTM: Reviewed-by: Ashutosh Dixit > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/xe/xe_gt_debugfs.c | 4 ++-- > drivers/gpu/drm/xe/xe_reg_sr.c | 30 ++++++++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_reg_sr.h | 4 ++++ > 3 files changed, 36 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c > index aa43427a9f4b824b8ad41d02f634c07c76d989b2..f45306308cd66c87b261edaa8de532f6cc56499d 100644 > --- a/drivers/gpu/drm/xe/xe_gt_debugfs.c > +++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c > @@ -173,8 +173,8 @@ static int register_save_restore_check(struct xe_gt *gt, struct drm_printer *p) > xe_reg_sr_readback_check(>->reg_sr, gt, p); > for_each_hw_engine(hwe, gt, id) > xe_reg_sr_readback_check(&hwe->reg_sr, gt, p); > - > - /* TODO: Check hwe->reg_lrc against contents of default_lrc. */ > + for_each_hw_engine(hwe, gt, id) > + xe_reg_sr_lrc_check(&hwe->reg_lrc, gt, hwe, p); > > return 0; > } > diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c > index 75aa4426b3ec6026bc13095df3c3f9cb0a794b97..83a668f2a0d5f16ea3f0b93eafb6b8e66abe3fe8 100644 > --- a/drivers/gpu/drm/xe/xe_reg_sr.c > +++ b/drivers/gpu/drm/xe/xe_reg_sr.c > @@ -21,6 +21,7 @@ > #include "xe_gt_printk.h" > #include "xe_gt_types.h" > #include "xe_hw_engine_types.h" > +#include "xe_lrc.h" > #include "xe_mmio.h" > #include "xe_rtp_types.h" > > @@ -242,3 +243,32 @@ void xe_reg_sr_readback_check(struct xe_reg_sr *sr, > offset, mask, entry->set_bits, val & mask); > } > } > + > +/** > + * xe_reg_sr_lrc_check() - Check LRC for registers referenced in save/restore > + * entries and check whether the programming is in place. > + * @sr: Save/restore entries > + * @gt: GT to read register from > + * @hwe: Hardware engine type to check LRC for > + * @p: DRM printer to report discrepancies on > + */ > +void xe_reg_sr_lrc_check(struct xe_reg_sr *sr, > + struct xe_gt *gt, > + struct xe_hw_engine *hwe, > + struct drm_printer *p) > +{ > + struct xe_reg_sr_entry *entry; > + unsigned long offset; > + > + xa_for_each(&sr->xa, offset, entry) { > + u32 val; > + int ret = xe_lrc_lookup_default_reg_value(gt, hwe->class, offset, &val); > + u32 mask = entry->clr_bits | entry->set_bits; > + > + if (ret == -ENOENT) > + drm_printf(p, "%#8lx :: not found in LRC for %s\n", offset, hwe->name); > + else if ((val & mask) != entry->set_bits) > + drm_printf(p, "%#8lx & %#10x :: expected %#10x got %#10x\n", > + offset, mask, entry->set_bits, val & mask); > + } > +} > diff --git a/drivers/gpu/drm/xe/xe_reg_sr.h b/drivers/gpu/drm/xe/xe_reg_sr.h > index cd133a09aa9b3f046dbd913aa9711250e771ee1a..1ec6e8ecf2784a3a832f30b7005f116ab7a368db 100644 > --- a/drivers/gpu/drm/xe/xe_reg_sr.h > +++ b/drivers/gpu/drm/xe/xe_reg_sr.h > @@ -22,6 +22,10 @@ void xe_reg_sr_dump(struct xe_reg_sr *sr, struct drm_printer *p); > void xe_reg_sr_readback_check(struct xe_reg_sr *sr, > struct xe_gt *gt, > struct drm_printer *p); > +void xe_reg_sr_lrc_check(struct xe_reg_sr *sr, > + struct xe_gt *gt, > + struct xe_hw_engine *hwe, > + struct drm_printer *p); > > int xe_reg_sr_add(struct xe_reg_sr *sr, const struct xe_reg_sr_entry *e, > struct xe_gt *gt); > > -- > 2.53.0 >