From: Jani Nikula <jani.nikula@intel.com>
To: imre.deak@intel.com
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v2 16/16] drm/i915/dp: compute config for 128b/132b SST w/o DSC
Date: Tue, 04 Feb 2025 17:50:53 +0200 [thread overview]
Message-ID: <87ikpp674y.fsf@intel.com> (raw)
In-Reply-To: <Z6I0knh2Kt5T0JrT@ideak-desk.fi.intel.com>
On Tue, 04 Feb 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Dec 19, 2024 at 11:34:05PM +0200, Jani Nikula wrote:
>> Enable basic 128b/132b SST functionality without compression. Reuse
>> intel_dp_mtp_tu_compute_config() to figure out the TU after we've
>> determined we need to use an UHBR rate.
>>
>> It's slightly complicated as the M/N computation is done in different
>> places in MST and SST paths, so we need to avoid trashing the values
>> later for UHBR.
>>
>> If uncompressed UHBR fails, we drop to compressed non-UHBR, which is
>> quite likely to fail as well. We still lack 128b/132b SST+DSC.
>>
>> We need mst_master_transcoder also for 128b/132b SST. Use cpu_transcoder
>> directly. Enhanced framing is "don't care" for 128b/132b link.
>>
>> v2: mst_master_transcoder, enhanced framing (Imre)
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
>> 1 file changed, 24 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index fba3af338280..d14a42f02ba8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2525,8 +2525,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>> limits->min_rate = intel_dp_min_link_rate(intel_dp);
>> limits->max_rate = intel_dp_max_link_rate(intel_dp);
>>
>> - /* FIXME 128b/132b SST support missing */
>> - if (!is_mst)
>> + /* FIXME 128b/132b SST+DSC support missing */
>> + if (!is_mst && dsc)
>> limits->max_rate = min(limits->max_rate, 810000);
>> limits->min_rate = min(limits->min_rate, limits->max_rate);
>>
>> @@ -2640,6 +2640,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>> */
>> ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
>> conn_state, &limits);
>> + if (!ret && intel_dp_is_uhbr(pipe_config))
>> + ret = intel_dp_mtp_tu_compute_config(intel_dp,
>> + pipe_config,
>> + pipe_config->pipe_bpp,
>> + pipe_config->pipe_bpp,
>> + conn_state,
>> + 0, false);
>
> Missed this in my review: intel_dp_mtp_tu_compute_config() for this to
> work, it needs to handle step == 0, i.e. if (step == 0) break; at the
> end of the bpp loop.
Right, good catch!
I wanted to pass 0 step to be explicit about doing it just once, but it
really only happens once if it succeeds! Otherwise it results in an
infinite loop.
Fix on the list.
Thanks,
Jani.
>
>> if (ret)
>> dsc_needed = true;
>> }
>> @@ -3148,8 +3155,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>> pipe_config->limited_color_range =
>> intel_dp_limited_color_range(pipe_config, conn_state);
>>
>> - pipe_config->enhanced_framing =
>> - drm_dp_enhanced_frame_cap(intel_dp->dpcd);
>> + if (intel_dp_is_uhbr(pipe_config)) {
>> + /* 128b/132b SST also needs this */
>> + pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
>> + } else {
>> + pipe_config->enhanced_framing =
>> + drm_dp_enhanced_frame_cap(intel_dp->dpcd);
>> + }
>>
>> if (pipe_config->dsc.compression_enable)
>> link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
>> @@ -3180,12 +3192,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>>
>> intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
>>
>> - intel_link_compute_m_n(link_bpp_x16,
>> - pipe_config->lane_count,
>> - adjusted_mode->crtc_clock,
>> - pipe_config->port_clock,
>> - intel_dp_bw_fec_overhead(pipe_config->fec_enable),
>> - &pipe_config->dp_m_n);
>> + if (!intel_dp_is_uhbr(pipe_config)) {
>> + intel_link_compute_m_n(link_bpp_x16,
>> + pipe_config->lane_count,
>> + adjusted_mode->crtc_clock,
>> + pipe_config->port_clock,
>> + intel_dp_bw_fec_overhead(pipe_config->fec_enable),
>> + &pipe_config->dp_m_n);
>> + }
>>
>> /* FIXME: abstract this better */
>> if (pipe_config->splitter.enable)
>> --
>> 2.39.5
>>
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-02-04 15:51 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-19 21:33 [PATCH v2 00/16] drm/i915/dp: 128b/132b uncompressed SST Jani Nikula
2024-12-19 21:33 ` [PATCH v2 01/16] drm/mst: remove mgr parameter and debug logging from drm_dp_get_vc_payload_bw() Jani Nikula
2024-12-31 15:24 ` Imre Deak
2025-01-02 10:15 ` [PATCH] " Jani Nikula
2025-01-02 11:50 ` Jani Nikula
2024-12-19 21:33 ` [PATCH v2 02/16] drm/i915/mst: drop connector parameter from intel_dp_mst_bw_overhead() Jani Nikula
2024-12-31 15:26 ` Imre Deak
2024-12-19 21:33 ` [PATCH v2 03/16] drm/i915/mst: drop connector parameter from intel_dp_mst_compute_m_n() Jani Nikula
2024-12-31 15:27 ` Imre Deak
2024-12-19 21:33 ` [PATCH v2 04/16] drm/i915/mst: change return value of mst_stream_find_vcpi_slots_for_bpp() Jani Nikula
2024-12-31 15:34 ` Imre Deak
2024-12-19 21:33 ` [PATCH v2 05/16] drm/i915/mst: remove crtc_state->pbn Jani Nikula
2024-12-31 15:35 ` Imre Deak
2024-12-19 21:33 ` [PATCH v2 06/16] drm/i915/mst: split out a helper for figuring out the TU Jani Nikula
2024-12-31 15:51 ` Imre Deak
2025-01-02 10:19 ` Jani Nikula
2024-12-19 21:33 ` [PATCH v2 07/16] drm/i915/mst: adapt intel_dp_mtp_tu_compute_config() for 128b/132b SST Jani Nikula
2024-12-31 16:16 ` Imre Deak
2025-01-02 10:30 ` Jani Nikula
2025-01-02 13:40 ` Imre Deak
2024-12-19 21:33 ` [PATCH v2 08/16] drm/i915/ddi: enable 128b/132b TRANS_DDI_FUNC_CTL mode for UHBR SST Jani Nikula
2024-12-31 16:21 ` Imre Deak
2024-12-19 21:33 ` [PATCH v2 09/16] drm/i915/ddi: 128b/132b SST also needs DP_TP_CTL_MODE_MST Jani Nikula
2024-12-31 16:27 ` Imre Deak
2024-12-19 21:33 ` [PATCH v2 10/16] drm/i915/ddi: write payload for 128b/132b SST Jani Nikula
2024-12-31 16:41 ` Imre Deak
2025-01-02 10:52 ` Jani Nikula
2025-01-02 13:54 ` Imre Deak
2024-12-19 21:34 ` [PATCH v2 11/16] drm/i915/ddi: initialize 128b/132b SST DP2 VFREQ registers Jani Nikula
2024-12-31 16:44 ` Imre Deak
2024-12-31 16:52 ` Imre Deak
2025-01-02 9:39 ` Jani Nikula
2025-01-02 12:09 ` Imre Deak
2024-12-19 21:34 ` [PATCH v2 12/16] drm/i915/ddi: enable ACT handling for 128b/132b SST Jani Nikula
2025-01-02 15:59 ` Imre Deak
2024-12-19 21:34 ` [PATCH v2 13/16] drm/i915/ddi: start distinguishing 128b/132b SST and MST at state readout Jani Nikula
2025-01-02 14:41 ` Imre Deak
2025-01-03 11:30 ` Jani Nikula
2024-12-19 21:34 ` [PATCH v2 14/16] drm/i915/ddi: handle 128b/132b SST in intel_ddi_read_func_ctl() Jani Nikula
2025-01-02 14:45 ` Imre Deak
2024-12-19 21:34 ` [PATCH v2 15/16] drm/i915/ddi: disable trancoder port select for 128b/132b SST Jani Nikula
2025-01-02 15:03 ` Imre Deak
2024-12-19 21:34 ` [PATCH v2 16/16] drm/i915/dp: compute config for 128b/132b SST w/o DSC Jani Nikula
2025-01-02 15:13 ` Imre Deak
2025-01-03 11:35 ` Jani Nikula
2025-02-04 15:38 ` Imre Deak
2025-02-04 15:50 ` Jani Nikula [this message]
2024-12-19 21:40 ` ✓ CI.Patch_applied: success for drm/i915/dp: 128b/132b uncompressed SST (rev2) Patchwork
2024-12-19 21:41 ` ✗ CI.checkpatch: warning " Patchwork
2024-12-19 21:42 ` ✓ CI.KUnit: success " Patchwork
2024-12-19 22:00 ` ✓ CI.Build: " Patchwork
2024-12-19 22:02 ` ✓ CI.Hooks: " Patchwork
2024-12-19 22:04 ` ✗ CI.checksparse: warning " Patchwork
2024-12-19 22:43 ` ✓ Xe.CI.BAT: success " Patchwork
2024-12-20 22:05 ` ✗ Xe.CI.Full: failure " Patchwork
2025-01-02 10:23 ` ✓ CI.Patch_applied: success for drm/i915/dp: 128b/132b uncompressed SST (rev3) Patchwork
2025-01-02 10:24 ` ✗ CI.checkpatch: warning " Patchwork
2025-01-02 10:25 ` ✓ CI.KUnit: success " Patchwork
2025-01-02 10:43 ` ✓ CI.Build: " Patchwork
2025-01-02 10:45 ` ✓ CI.Hooks: " Patchwork
2025-01-02 10:47 ` ✗ CI.checksparse: warning " Patchwork
2025-01-02 11:21 ` ✓ Xe.CI.BAT: success " Patchwork
2025-01-02 12:47 ` ✗ Xe.CI.Full: failure " Patchwork
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