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d="scan'208";a="106979263" Received: from ettammin-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.246.80]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 04:12:47 -0700 From: Jani Nikula To: Ville Syrjala , intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: Re: [PATCH 2/4] drm/i915/gt: s/gen3/gen2/ In-Reply-To: <20241008214349.23331-3-ville.syrjala@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20241008214349.23331-1-ville.syrjala@linux.intel.com> <20241008214349.23331-3-ville.syrjala@linux.intel.com> Date: Wed, 09 Oct 2024 14:12:43 +0300 Message-ID: <87iku1a5sk.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 09 Oct 2024, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Now that we use the gen3 codepaths also for gen2 > rename everything to gen2_ to match. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 8 ++++---- > drivers/gpu/drm/i915/gt/gen2_engine_cs.h | 8 ++++---- > drivers/gpu/drm/i915/gt/intel_ring_submission.c | 8 ++++---- > 3 files changed, 12 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i= 915/gt/gen2_engine_cs.c > index 54077cab8e16..4904d0f4162c 100644 > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > @@ -169,7 +169,7 @@ static u32 *__gen2_emit_breadcrumb(struct i915_reques= t *rq, u32 *cs, > return cs; > } >=20=20 > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > +u32 *gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs) > { > return __gen2_emit_breadcrumb(rq, cs, 16, 8); > } > @@ -248,7 +248,7 @@ int i830_emit_bb_start(struct i915_request *rq, > return 0; > } >=20=20 > -int gen3_emit_bb_start(struct i915_request *rq, > +int gen2_emit_bb_start(struct i915_request *rq, > u64 offset, u32 len, > unsigned int dispatch_flags) > { > @@ -290,14 +290,14 @@ int gen4_emit_bb_start(struct i915_request *rq, > return 0; > } >=20=20 > -void gen3_irq_enable(struct intel_engine_cs *engine) > +void gen2_irq_enable(struct intel_engine_cs *engine) > { > engine->i915->irq_mask &=3D ~engine->irq_enable_mask; > intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); > intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); > } >=20=20 > -void gen3_irq_disable(struct intel_engine_cs *engine) > +void gen2_irq_disable(struct intel_engine_cs *engine) > { > engine->i915->irq_mask |=3D engine->irq_enable_mask; > intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h b/drivers/gpu/drm/i= 915/gt/gen2_engine_cs.h > index 2f707620b3d4..7b37560fc356 100644 > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h > @@ -15,21 +15,21 @@ int gen2_emit_flush(struct i915_request *rq, u32 mode= ); > int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode); > int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode); >=20=20 > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs); > +u32 *gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs); > u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs); >=20=20 > int i830_emit_bb_start(struct i915_request *rq, > u64 offset, u32 len, > unsigned int dispatch_flags); > -int gen3_emit_bb_start(struct i915_request *rq, > +int gen2_emit_bb_start(struct i915_request *rq, > u64 offset, u32 len, > unsigned int dispatch_flags); > int gen4_emit_bb_start(struct i915_request *rq, > u64 offset, u32 length, > unsigned int dispatch_flags); >=20=20 > -void gen3_irq_enable(struct intel_engine_cs *engine); > -void gen3_irq_disable(struct intel_engine_cs *engine); > +void gen2_irq_enable(struct intel_engine_cs *engine); > +void gen2_irq_disable(struct intel_engine_cs *engine); > void gen5_irq_enable(struct intel_engine_cs *engine); > void gen5_irq_disable(struct intel_engine_cs *engine); >=20=20 > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gp= u/drm/i915/gt/intel_ring_submission.c > index 694cb79d5452..3ec8bc01058b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -1091,8 +1091,8 @@ static void setup_irq(struct intel_engine_cs *engin= e) > engine->irq_enable =3D gen5_irq_enable; > engine->irq_disable =3D gen5_irq_disable; > } else { > - engine->irq_enable =3D gen3_irq_enable; > - engine->irq_disable =3D gen3_irq_disable; > + engine->irq_enable =3D gen2_irq_enable; > + engine->irq_disable =3D gen2_irq_disable; > } > } >=20=20 > @@ -1143,7 +1143,7 @@ static void setup_common(struct intel_engine_cs *en= gine) > * equivalent to our next initial bread so we can elide > * engine->emit_init_breadcrumb(). > */ > - engine->emit_fini_breadcrumb =3D gen3_emit_breadcrumb; > + engine->emit_fini_breadcrumb =3D gen2_emit_breadcrumb; > if (GRAPHICS_VER(i915) =3D=3D 5) > engine->emit_fini_breadcrumb =3D gen5_emit_breadcrumb; >=20=20 > @@ -1156,7 +1156,7 @@ static void setup_common(struct intel_engine_cs *en= gine) > else if (IS_I830(i915) || IS_I845G(i915)) > engine->emit_bb_start =3D i830_emit_bb_start; > else > - engine->emit_bb_start =3D gen3_emit_bb_start; > + engine->emit_bb_start =3D gen2_emit_bb_start; > } >=20=20 > static void setup_rcs(struct intel_engine_cs *engine) --=20 Jani Nikula, Intel