From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3DCDD3749C for ; Fri, 5 Dec 2025 20:36:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9247210E27E; Fri, 5 Dec 2025 20:36:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bt0okMPU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 730A710E27E for ; Fri, 5 Dec 2025 20:36:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764966962; x=1796502962; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=8NTiqLfRJa90GWwVumg8CAGImocJYJHP4xXgc8rkKDg=; b=bt0okMPU2YMlANUHsJ4wfEgiru4cEyUL35jtTTneRVldcA+YQuOsl1Tq qi2r6zMtJjz5OQDiRJwriI74L+vR3B0VjaBI6T8yDHyUu7w9y8eZTKYWJ lIma6ebFYgy1jsId+azvsDVHcBV4118DDecZMzwivIlN6Fid4IDOwDBhU H64oRQI05jnjASTPbd7qdgQHIAy/swmfgDykVmFwq15Xd/nn+VGWUtv7+ YUqUEoHrStFtqz1K/BJiUnoZA167BjoFR0qZiotIsw22zCpSLcqnyJA9h qmnIirlYFTiyb43oaGYGQ185hHX7fTRfq9xNjsOgp1dXyYDiSy/b6ySDP g==; X-CSE-ConnectionGUID: dOQNSqCfSFq6sXtnBL3GPA== X-CSE-MsgGUID: 8O3bWagzS0GwysptZjjcfw== X-IronPort-AV: E=McAfee;i="6800,10657,11633"; a="54551369" X-IronPort-AV: E=Sophos;i="6.20,252,1758610800"; d="scan'208";a="54551369" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2025 12:36:02 -0800 X-CSE-ConnectionGUID: goLNyZjsShCMnwu4PdtDwg== X-CSE-MsgGUID: LyFMO/wBSGaloxVqU0YgBQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,252,1758610800"; d="scan'208";a="200327670" Received: from pgopalap-mobl2.amr.corp.intel.com (HELO adixit-MOBL3.intel.com) ([10.124.162.149]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2025 12:36:02 -0800 Date: Fri, 05 Dec 2025 12:36:01 -0800 Message-ID: <87ms3wpsy6.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Shuicheng Lin Cc: , Matthew Brost Subject: Re: [PATCH 3/3] drm/xe/oa: Limit num_syncs to prevent oversized allocations In-Reply-To: <20251205190506.2426471-8-shuicheng.lin@intel.com> References: <20251205190506.2426471-5-shuicheng.lin@intel.com> <20251205190506.2426471-8-shuicheng.lin@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Fri, 05 Dec 2025 11:05:10 -0800, Shuicheng Lin wrote: > Hi Shuicheng, > The OA open parameters did not validate num_syncs, allowing > userspace to pass arbitrarily large values, potentially > leading to excessive allocations. > > Add checks to ensure that num_syncs does not exceed XE_MAX_SYNCS, > returning -EINVAL when the limit is violated. > > Fixes: c8507a25cebd ("drm/xe/oa/uapi: Define and parse OA sync properties") > Cc: Matthew Brost > Cc: Ashutosh Dixit > Signed-off-by: Shuicheng Lin > --- > drivers/gpu/drm/xe/xe_oa.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c > index cc48663c2b48..7477c27a4ba2 100644 > --- a/drivers/gpu/drm/xe/xe_oa.c > +++ b/drivers/gpu/drm/xe/xe_oa.c > @@ -1254,6 +1254,11 @@ static int xe_oa_set_no_preempt(struct xe_oa *oa, u64 value, > static int xe_oa_set_prop_num_syncs(struct xe_oa *oa, u64 value, > struct xe_oa_open_param *param) > { > + if (value > XE_MAX_SYNCS) { > + drm_dbg(&oa->xe->drm, "num_syncs %llu must be <= %u\n", > + value, XE_MAX_SYNCS); > + return -EINVAL; > + } Like the other patches, let's just do: if (XE_IOCTL_DBG(xe, value > XE_MAX_SYNCS)) return -EINVAL; I might change the other functions here to also use XE_IOCTL_DBG(). They may have been written before XE_IOCTL_DBG() was implemented. > param->num_syncs = value; > return 0; > } > @@ -1404,6 +1409,12 @@ static int xe_oa_parse_syncs(struct xe_oa *oa, > } > > if (param->num_syncs) { > + if (param->num_syncs > XE_MAX_SYNCS) { > + drm_dbg(&oa->xe->drm, "num_syncs %d must be <= %u\n", > + param->num_syncs, XE_MAX_SYNCS); > + ret = -EINVAL; > + goto exit; > + } This is not needed. If we return -EINVAL from the code at the top, this will never get executed. Also, maybe squash the 3 patches into a single patch? Not sure if we need 3 patches, a single patch with XE_IOCTL_DBG() in all 3 places might make more sense? > param->syncs = kcalloc(param->num_syncs, sizeof(*param->syncs), GFP_KERNEL); > if (!param->syncs) { > ret = -ENOMEM; > -- > 2.50.1 > Thanks. -- Ashutosh