From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E7C5C3DA4A for ; Tue, 20 Aug 2024 01:18:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E8B910E331; Tue, 20 Aug 2024 01:18:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hYI7H9sx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB16F10E331 for ; Tue, 20 Aug 2024 01:18:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724116702; x=1755652702; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=+aC5Ga1jBluKWYEQGAP9pfh7H8/FkDd075mGY9wMReU=; b=hYI7H9sxglDR/M2NfAn6WFUbH5YSpEPgCTVrs8AjgBzLtdCMbMZnnIZc oPsLKDAcAwyF4qQgsqTZq8/f/PbLCqdR33LnMjD/IPGbuELLXP0/+XWb1 4Shvuftpww3YSYOaUdhwCfZs8JqKpjIkIUSQV5ZNbNtscXlCYtz2hHjxN 8gEsAFvxi6Gw3exCoBwqgDdn6rkiuy2vWESmc1KsNPDqPoUSpvD4wxg2g 7dwqjD6F+Vd3BWJCZTR6Z+L85pblIQracUNvcbT4dknQ5CHS33JPy3uOL yBTPFtMfxQBQUZXf3U+0NjmRDfrLbnLFyZYIwn812O0Jb18cucSD50jgQ w==; X-CSE-ConnectionGUID: dnAJ00kDTN+aXCyvOgjsBw== X-CSE-MsgGUID: vgDczWgtRWKYnR5kZ7mj1w== X-IronPort-AV: E=McAfee;i="6700,10204,11169"; a="22535121" X-IronPort-AV: E=Sophos;i="6.10,160,1719903600"; d="scan'208";a="22535121" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2024 18:18:22 -0700 X-CSE-ConnectionGUID: b4o/eVGVTyqOE1XOkzk+MQ== X-CSE-MsgGUID: CANSM+2ET86yJGls9CiM1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,160,1719903600"; d="scan'208";a="98017227" Received: from peterval-mobl1.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.124.114.37]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2024 18:18:20 -0700 Date: Mon, 19 Aug 2024 18:03:32 -0700 Message-ID: <87msl8dmzf.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: "Cavitt, Jonathan" Cc: "intel-xe@lists.freedesktop.org" , "Nerlige Ramappa, Umesh" , "Souza, Jose" , "Landwerlin, Lionel G" Subject: Re: [PATCH 2/8] drm/xe/oa: Introduce 'struct xe_oa_fence' In-Reply-To: References: <20240808174139.4027534-1-ashutosh.dixit@intel.com> <20240808174139.4027534-3-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Thu, 08 Aug 2024 13:58:52 -0700, Cavitt, Jonathan wrote: > > -----Original Message----- > From: Intel-xe On Behalf Of Ashutosh Dixit > Sent: Thursday, August 8, 2024 10:42 AM > To: intel-xe@lists.freedesktop.org > Cc: Nerlige Ramappa, Umesh ; Souza, Jose ; Landwerlin, Lionel G > Subject: [PATCH 2/8] drm/xe/oa: Introduce 'struct xe_oa_fence' > > > > Here we introduce 'struct xe_oa_fence' which will contain the fence used > > for signalling xe_syncs (in a later patch). The struct also contains the > > work struct used for signalling the fences. Otherwise, this patch is a > > simple refactor of the previous patch. In this patch the work function is > > executed synchronously. > > > > Signed-off-by: Ashutosh Dixit > > If I understand correctly, it seems this is moving the fence > wait and put section to part of a work fini function that > executes when the xe_oa_fence is closed? The work function is scheduled to run, so that the wait can be executed asynchronously after which the fence will be signalled (in Patch 5/8). Though there are few changes here in v2, but the basic concept is the same. See Patch 4 "drm/xe/oa: Signal output fences" in v2. > LGTM. > Reviewed-by: Jonathan Cavitt Thanks. -- Ashutosh > -Jonathan Cavitt > > > --- > > drivers/gpu/drm/xe/xe_oa.c | 73 ++++++++++++++++++++++++++++++-------- > > 1 file changed, 59 insertions(+), 14 deletions(-) > > > > diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c > > index d842c801fb9f1..f97d64ffb460f 100644 > > --- a/drivers/gpu/drm/xe/xe_oa.c > > +++ b/drivers/gpu/drm/xe/xe_oa.c > > @@ -90,6 +90,15 @@ struct xe_oa_config_bo { > > struct xe_bb *bb; > > }; > > > > +struct xe_oa_fence { > > + /* @xe: pointer to xe device */ > > + struct xe_device *xe; > > + /* @work: work to signal that OA configuration is applied */ > > + struct work_struct work; > > + /* @config_fence: dma fence for OA config to be applied */ > > + struct dma_fence *config_fence; > > +}; > > + > > #define DRM_FMT(x) DRM_XE_OA_FMT_TYPE_##x > > > > static const struct xe_oa_format oa_formats[] = { > > @@ -905,14 +914,51 @@ xe_oa_alloc_config_buffer(struct xe_oa_stream *stream, struct xe_oa_config *oa_c > > return oa_bo; > > } > > > > -static int xe_oa_emit_oa_config(struct xe_oa_stream *stream, struct xe_oa_config *config) > > +static void xe_oa_fence_work_fn(struct work_struct *w) > > { > > #define NOA_PROGRAM_ADDITIONAL_DELAY_US 500 > > - struct xe_oa_config_bo *oa_bo; > > + struct xe_oa_fence *ofence = container_of(w, typeof(*ofence), work); > > int err = 0, us = NOA_PROGRAM_ADDITIONAL_DELAY_US; > > - struct dma_fence *fence; > > long timeout; > > > > + /* Wait till all previous batches have executed */ > > + timeout = dma_fence_wait_timeout(ofence->config_fence, false, 5 * HZ); > > + dma_fence_put(ofence->config_fence); > > + if (timeout < 0) > > + err = timeout; > > + else if (!timeout) > > + err = -ETIME; > > + if (err) > > + drm_dbg(&ofence->xe->drm, "dma_fence_wait_timeout err %d\n", err); > > + > > + /* Additional empirical delay needed for NOA programming after registers are written */ > > + usleep_range(us, 2 * us); > > + > > + kfree(ofence); > > +} > > + > > +static struct xe_oa_fence *xe_oa_fence_init(struct xe_device *xe, struct dma_fence *config_fence) > > +{ > > + struct xe_oa_fence *ofence; > > + > > + ofence = kzalloc(sizeof(*ofence), GFP_KERNEL); > > + if (!ofence) > > + return ERR_PTR(-ENOMEM); > > + > > + ofence->xe = xe; > > + INIT_WORK(&ofence->work, xe_oa_fence_work_fn); > > + ofence->config_fence = config_fence; > > + > > + return ofence; > > +} > > + > > +static int xe_oa_emit_oa_config(struct xe_oa_stream *stream, struct xe_oa_config *config) > > +{ > > + struct xe_oa_config_bo *oa_bo; > > + struct xe_oa_fence *ofence; > > + struct dma_fence *fence; > > + int err; > > + > > /* Emit OA configuration batch */ > > oa_bo = xe_oa_alloc_config_buffer(stream, config); > > if (IS_ERR(oa_bo)) { > > @@ -924,18 +970,17 @@ static int xe_oa_emit_oa_config(struct xe_oa_stream *stream, struct xe_oa_config > > if (err) > > goto exit; > > > > - /* Wait till all previous batches have executed */ > > - timeout = dma_fence_wait_timeout(fence, false, 5 * HZ); > > - dma_fence_put(fence); > > - if (timeout < 0) > > - err = timeout; > > - else if (!timeout) > > - err = -ETIME; > > - if (err) > > - drm_dbg(&stream->oa->xe->drm, "dma_fence_wait_timeout err %d\n", err); > > + ofence = xe_oa_fence_init(stream->oa->xe, fence); > > + if (IS_ERR(ofence)) { > > + err = PTR_ERR(ofence); > > + goto put_fence; > > + } > > > > - /* Additional empirical delay needed for NOA programming after registers are written */ > > - usleep_range(us, 2 * us); > > + xe_oa_fence_work_fn(&ofence->work); > > + > > + return 0; > > +put_fence: > > + dma_fence_put(fence); > > exit: > > return err; > > } > > -- > > 2.41.0 > > > >