From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3E13EB64DD for ; Thu, 10 Aug 2023 02:40:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 80B8D10E14D; Thu, 10 Aug 2023 02:40:11 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 91E2210E14D for ; Thu, 10 Aug 2023 02:40:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691635209; x=1723171209; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=A5jRzbhb81wya7/kzqQyMShC2lceQlzol1PYok+Hs+0=; b=B84ZLOSPsN4dmnTuK9+pDvHJXoTC33EKHUVtiLkJVyvpC+LYN5pcAAsa 5SLRviRcV/b6sKkR9iwZIP9LYW/2+jX0CfgCbZtR9F84Wo3XhwKgMW2lG GApOwNAwmYuQ89vztmHCWrZfaxbcx3M7V8cIFTWJdJTEgoDA30/NSOpgS UKk6yJZzZ19kaGalriJkBMzqg1anHAEUyvQbZSguyEkiCF12ahB7od5/i j2aGfhTZ3YWl2Uxcjz0cWzFcWpszvK4+n6lCuckL7mzXeqSU74Tl72ehv q6rrtrNPzv/JuF+U0Fyurm794+oc6P0RiL0wERwn20f9es51+LpeUxAr9 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10797"; a="351584421" X-IronPort-AV: E=Sophos;i="6.01,160,1684825200"; d="scan'208";a="351584421" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2023 19:40:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="875506272" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.56.194]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2023 19:40:11 -0700 Date: Wed, 09 Aug 2023 19:40:08 -0700 Message-ID: <87msyz39iv.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: "Iddamsetty, Aravind" In-Reply-To: References: <20230808115436.400611-1-aravind.iddamsetty@intel.com> <20230808115436.400611-3-aravind.iddamsetty@intel.com> <877cq4y8s3.wl-ashutosh.dixit@intel.com> <95750d7f-df24-a9c5-ab39-86db69767bac@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-xe] [PATCH v3 2/2] drm/xe/pmu: Enable PMU interface X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bommu Krishnaiah , intel-xe@lists.freedesktop.org, Tvrtko Ursulin Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, 09 Aug 2023 06:11:48 -0700, Iddamsetty, Aravind wrote: Hi Aravind, > On 09-08-2023 17:27, Iddamsetty, Aravind wrote: > > On 09-08-2023 15:25, Iddamsetty, Aravind wrote: > >> On 09-08-2023 12:58, Dixit, Ashutosh wrote: > >>> On Tue, 08 Aug 2023 04:54:36 -0700, Aravind Iddamsetty wrote: > >>> > >>> Spotted a few remaining things. See if it's possible to fix these up and > >>> send another version. > >>> > >>>> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c > >>>> new file mode 100644 > >>>> index 000000000000..9637f8283641 > >>>> --- /dev/null > >>>> +++ b/drivers/gpu/drm/xe/xe_pmu.c > >>>> @@ -0,0 +1,673 @@ > >> > >> > >>>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, int sample_type) > >>>> +{ > >>>> + u64 val = 0; > >>>> + > >>> > >>> What is the forcewake domain for these registers? Don't we need to get > >>> forcewake before reading these. Something like: > >>> > >>> XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL)); > >> > >> based on BSPEC:67609 these belong to GT power domain, so acquiring that > >> should be sufficient. > > > > But if i understand correctly taking forcewake is not allowed here as it > > is an atomic context and forcewake can sleep and that is what I'm seeing > > as well, might also be the reason why i915 didn't do that as well. > > > > [ 899.114316] BUG: sleeping function called from invalid context at > > kernel/locking/mutex.c:580 > > [ 899.115768] in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: > > 290, name: kworker/27:1 > > that is the reason why in i915 we were doing similar thing of storing > the counter as we enter rc6, not sure how do we do that in xe. Just to check, which code path(s) is/are aotmic context: a. xe_pm_suspend b. xe_pm_runtime_suspend c. xe_pmu_event_read Now I am wondering if GuC should provide these counters too along with other busyness values it provides, since GuC is what control RC6 entry/exit. But let's try to understand the issue some more first. Thanks. -- Ashutosh > >>> > >>>> + switch (sample_type) { > >>>> + case __XE_SAMPLE_RENDER_GROUP_BUSY: > >>>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE); > >>>> + break; > >>>> + case __XE_SAMPLE_COPY_GROUP_BUSY: > >>>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE); > >>>> + break; > >>>> + case __XE_SAMPLE_MEDIA_GROUP_BUSY: > >>>> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE); > >>>> + break; > >>>> + case __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY: > >>>> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE); > >>>> + break; > >>>> + default: > >>>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n"); > >>>> + } > >>> > >>> And similarly here: > >>> > >>> XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));