Re: [PATCH] drm/xe/xe3p_lpg: Add missing indirect ring state feature flag

[Gustavo Sousa <gustavo.sousa@intel.com>]

Matt Roper <matthew.d.roper@intel.com> writes:

> On Wed, Apr 01, 2026 at 07:10:51PM -0300, Gustavo Sousa wrote:
>> Even though commit 8fcb7dfb8bbf ("drm/xe/xe3p_lpg: Add support for
>> graphics IP 35.10") mentions that the support for Indirect Ring State
>> exists for Xe3p_LPG, it missed actually setting the feature flag in
>> graphics_xe3p_lpg.  Fix that by adding the missing member.
>> 
>> Fixes: 8fcb7dfb8bbf ("drm/xe/xe3p_lpg: Add support for graphics IP 35.10")
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Pushed to drm-xe-next. Thanks for the review!

--
Gustavo Sousa

>
>> ---
>>  drivers/gpu/drm/xe/xe_pci.c | 1 +
>>  1 file changed, 1 insertion(+)
>> 
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index 1df3f08e2e1c..6e560ef84a97 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -118,6 +118,7 @@ static const struct xe_graphics_desc graphics_xe2 = {
>>  
>>  static const struct xe_graphics_desc graphics_xe3p_lpg = {
>>  	XE2_GFX_FEATURES,
>> +	.has_indirect_ring_state = 1,
>>  	.multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE),
>>  	.num_geometry_xecore_fuse_regs = 3,
>>  	.num_compute_xecore_fuse_regs = 3,
>> 
>> ---
>> base-commit: 40f5b5bc2d3df4c7c2d4e27b35b2d8179ac3f10b
>> change-id: 20260401-xe3p_lpg-indirect-ring-state-6220d15b2322
>> 
>> Best regards,
>> --  
>> Gustavo Sousa <gustavo.sousa@intel.com>
>> 
>
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation